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| author | 2021-02-25 00:46:40 -0500 | |
|---|---|---|
| committer | 2021-07-22 21:51:22 -0400 | |
| commit | cc55d289494c991e7e0e456e428a110569708c2e (patch) | |
| tree | 36e869098e87528ab7b7f668e232d7e909a2258a /src/shader_recompiler/backend | |
| parent | shader: Implement SEL (diff) | |
| download | yuzu-cc55d289494c991e7e0e456e428a110569708c2e.tar.gz yuzu-cc55d289494c991e7e0e456e428a110569708c2e.tar.xz yuzu-cc55d289494c991e7e0e456e428a110569708c2e.zip | |
shader: Implement SHR
Diffstat (limited to 'src/shader_recompiler/backend')
| -rw-r--r-- | src/shader_recompiler/backend/spirv/emit_spirv.h | 5 | ||||
| -rw-r--r-- | src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp | 12 |
2 files changed, 11 insertions, 6 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv.h b/src/shader_recompiler/backend/spirv/emit_spirv.h index 4b74cf04d..90afbcc90 100644 --- a/src/shader_recompiler/backend/spirv/emit_spirv.h +++ b/src/shader_recompiler/backend/spirv/emit_spirv.h | |||
| @@ -219,14 +219,15 @@ Id EmitIMul32(EmitContext& ctx, Id a, Id b); | |||
| 219 | Id EmitINeg32(EmitContext& ctx, Id value); | 219 | Id EmitINeg32(EmitContext& ctx, Id value); |
| 220 | Id EmitIAbs32(EmitContext& ctx, Id value); | 220 | Id EmitIAbs32(EmitContext& ctx, Id value); |
| 221 | Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift); | 221 | Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift); |
| 222 | void EmitShiftRightLogical32(EmitContext& ctx); | 222 | Id EmitShiftRightLogical32(EmitContext& ctx, Id a, Id b); |
| 223 | void EmitShiftRightArithmetic32(EmitContext& ctx); | 223 | Id EmitShiftRightArithmetic32(EmitContext& ctx, Id a, Id b); |
| 224 | Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b); | 224 | Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b); |
| 225 | Id EmitBitwiseOr32(EmitContext& ctx, Id a, Id b); | 225 | Id EmitBitwiseOr32(EmitContext& ctx, Id a, Id b); |
| 226 | Id EmitBitwiseXor32(EmitContext& ctx, Id a, Id b); | 226 | Id EmitBitwiseXor32(EmitContext& ctx, Id a, Id b); |
| 227 | Id EmitBitFieldInsert(EmitContext& ctx, Id base, Id insert, Id offset, Id count); | 227 | Id EmitBitFieldInsert(EmitContext& ctx, Id base, Id insert, Id offset, Id count); |
| 228 | Id EmitBitFieldSExtract(EmitContext& ctx, Id base, Id offset, Id count); | 228 | Id EmitBitFieldSExtract(EmitContext& ctx, Id base, Id offset, Id count); |
| 229 | Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count); | 229 | Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count); |
| 230 | Id EmitBitReverse32(EmitContext& ctx, Id value); | ||
| 230 | Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs); | 231 | Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs); |
| 231 | Id EmitULessThan(EmitContext& ctx, Id lhs, Id rhs); | 232 | Id EmitULessThan(EmitContext& ctx, Id lhs, Id rhs); |
| 232 | Id EmitIEqual(EmitContext& ctx, Id lhs, Id rhs); | 233 | Id EmitIEqual(EmitContext& ctx, Id lhs, Id rhs); |
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp index 8aaa0e381..406df1b78 100644 --- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp +++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp | |||
| @@ -70,12 +70,12 @@ Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift) { | |||
| 70 | return ctx.OpShiftLeftLogical(ctx.U32[1], base, shift); | 70 | return ctx.OpShiftLeftLogical(ctx.U32[1], base, shift); |
| 71 | } | 71 | } |
| 72 | 72 | ||
| 73 | void EmitShiftRightLogical32(EmitContext&) { | 73 | Id EmitShiftRightLogical32(EmitContext& ctx, Id a, Id b) { |
| 74 | throw NotImplementedException("SPIR-V Instruction"); | 74 | return ctx.OpShiftRightLogical(ctx.U32[1], a, b); |
| 75 | } | 75 | } |
| 76 | 76 | ||
| 77 | void EmitShiftRightArithmetic32(EmitContext&) { | 77 | Id EmitShiftRightArithmetic32(EmitContext& ctx, Id a, Id b) { |
| 78 | throw NotImplementedException("SPIR-V Instruction"); | 78 | return ctx.OpShiftRightArithmetic(ctx.U32[1], a, b); |
| 79 | } | 79 | } |
| 80 | 80 | ||
| 81 | Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b) { | 81 | Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b) { |
| @@ -102,6 +102,10 @@ Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count) { | |||
| 102 | return ctx.OpBitFieldUExtract(ctx.U32[1], base, offset, count); | 102 | return ctx.OpBitFieldUExtract(ctx.U32[1], base, offset, count); |
| 103 | } | 103 | } |
| 104 | 104 | ||
| 105 | Id EmitBitReverse32(EmitContext& ctx, Id value) { | ||
| 106 | return ctx.OpBitReverse(ctx.U32[1], value); | ||
| 107 | } | ||
| 108 | |||
| 105 | Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) { | 109 | Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) { |
| 106 | return ctx.OpSLessThan(ctx.U1, lhs, rhs); | 110 | return ctx.OpSLessThan(ctx.U1, lhs, rhs); |
| 107 | } | 111 | } |