shader: Implement R2P

3 files changed, 13 insertions, 3 deletions

diff --git a/src/shader_recompiler/backend/spirv/emit_spirv.h b/src/shader_recompiler/backend/spirv/emit_spirv.h
index bf1b5ace6..92387ca28 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv.h
+++ b/src/shader_recompiler/backend/spirv/emit_spirv.h
@@ -120,6 +120,7 @@ void EmitCompositeExtractF64x4(EmitContext& ctx);
 Id EmitCompositeInsertF64x2(EmitContext& ctx, Id composite, Id object, u32 index);
 Id EmitCompositeInsertF64x3(EmitContext& ctx, Id composite, Id object, u32 index);
 Id EmitCompositeInsertF64x4(EmitContext& ctx, Id composite, Id object, u32 index);
+Id EmitSelectU1(EmitContext& ctx, Id cond, Id true_value, Id false_value);
 Id EmitSelectU8(EmitContext& ctx, Id cond, Id true_value, Id false_value);
 Id EmitSelectU16(EmitContext& ctx, Id cond, Id true_value, Id false_value);
 Id EmitSelectU32(EmitContext& ctx, Id cond, Id true_value, Id false_value);
@@ -242,7 +243,7 @@ Id EmitBitwiseOr32(EmitContext& ctx, Id a, Id b);
 Id EmitBitwiseXor32(EmitContext& ctx, Id a, Id b);
 Id EmitBitFieldInsert(EmitContext& ctx, Id base, Id insert, Id offset, Id count);
 Id EmitBitFieldSExtract(EmitContext& ctx, Id base, Id offset, Id count);
-Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count);
+Id EmitBitFieldUExtract(EmitContext& ctx, IR::Inst* inst, Id base, Id offset, Id count);
 Id EmitBitReverse32(EmitContext& ctx, Id value);
 Id EmitBitCount32(EmitContext& ctx, Id value);
 Id EmitBitwiseNot32(EmitContext& ctx, Id value);
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
index 5ab3b5e86..c9de204b0 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
@@ -114,8 +114,13 @@ Id EmitBitFieldSExtract(EmitContext& ctx, Id base, Id offset, Id count) {
     return ctx.OpBitFieldSExtract(ctx.U32[1], base, offset, count);
 }
 
-Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count) {
-    return ctx.OpBitFieldUExtract(ctx.U32[1], base, offset, count);
+Id EmitBitFieldUExtract(EmitContext& ctx, IR::Inst* inst, Id base, Id offset, Id count) {
+    const Id result{ctx.OpBitFieldUExtract(ctx.U32[1], base, offset, count)};
+    if (IR::Inst* const zero{inst->GetAssociatedPseudoOperation(IR::Opcode::GetZeroFromOp)}) {
+        zero->SetDefinition(ctx.OpIEqual(ctx.U1, result, ctx.u32_zero_value));
+        zero->Invalidate();
+    }
+    return result;
 }
 
 Id EmitBitReverse32(EmitContext& ctx, Id value) {
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_select.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_select.cpp
index 21cca4455..0ae127d50 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_select.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_select.cpp
@@ -6,6 +6,10 @@
 
 namespace Shader::Backend::SPIRV {
 
+Id EmitSelectU1(EmitContext& ctx, Id cond, Id true_value, Id false_value) {
+    return ctx.OpSelect(ctx.U1, cond, true_value, false_value);
+}
+
 Id EmitSelectU8([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] Id cond,
                 [[maybe_unused]] Id true_value, [[maybe_unused]] Id false_value) {
     throw NotImplementedException("SPIR-V Instruction");