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| author | 2021-07-11 22:10:38 -0400 | |
|---|---|---|
| committer | 2021-07-22 21:51:40 -0400 | |
| commit | 49946cf780c317b4c5ccabb52ec433eba01c1970 (patch) | |
| tree | 628060b15b133cf3a1aaf716fba3517fc5c983f0 /src/shader_recompiler/backend | |
| parent | main: Update Shader Cache menu options (diff) | |
| download | yuzu-49946cf780c317b4c5ccabb52ec433eba01c1970.tar.gz yuzu-49946cf780c317b4c5ccabb52ec433eba01c1970.tar.xz yuzu-49946cf780c317b4c5ccabb52ec433eba01c1970.zip | |
shader_recompiler, video_core: Resolve clang errors
Silences the following warnings-turned-errors:
-Wsign-conversion
-Wunused-private-field
-Wbraced-scalar-init
-Wunused-variable
And some other errors
Diffstat (limited to 'src/shader_recompiler/backend')
4 files changed, 13 insertions, 9 deletions
diff --git a/src/shader_recompiler/backend/glasm/emit_context.h b/src/shader_recompiler/backend/glasm/emit_context.h index 1da51a996..8433e5c00 100644 --- a/src/shader_recompiler/backend/glasm/emit_context.h +++ b/src/shader_recompiler/backend/glasm/emit_context.h | |||
| @@ -59,7 +59,7 @@ public: | |||
| 59 | } | 59 | } |
| 60 | 60 | ||
| 61 | std::string code; | 61 | std::string code; |
| 62 | RegAlloc reg_alloc{*this}; | 62 | RegAlloc reg_alloc{}; |
| 63 | const Info& info; | 63 | const Info& info; |
| 64 | const Profile& profile; | 64 | const Profile& profile; |
| 65 | const RuntimeInfo& runtime_info; | 65 | const RuntimeInfo& runtime_info; |
diff --git a/src/shader_recompiler/backend/glasm/reg_alloc.h b/src/shader_recompiler/backend/glasm/reg_alloc.h index 5a703daf2..82aec66c6 100644 --- a/src/shader_recompiler/backend/glasm/reg_alloc.h +++ b/src/shader_recompiler/backend/glasm/reg_alloc.h | |||
| @@ -86,7 +86,7 @@ struct ScalarF64 : Value {}; | |||
| 86 | 86 | ||
| 87 | class RegAlloc { | 87 | class RegAlloc { |
| 88 | public: | 88 | public: |
| 89 | RegAlloc(EmitContext& ctx_) : ctx{ctx_} {} | 89 | RegAlloc() = default; |
| 90 | 90 | ||
| 91 | Register Define(IR::Inst& inst); | 91 | Register Define(IR::Inst& inst); |
| 92 | 92 | ||
| @@ -142,7 +142,6 @@ private: | |||
| 142 | 142 | ||
| 143 | void Free(Id id); | 143 | void Free(Id id); |
| 144 | 144 | ||
| 145 | EmitContext& ctx; | ||
| 146 | size_t num_used_registers{}; | 145 | size_t num_used_registers{}; |
| 147 | size_t num_used_long_registers{}; | 146 | size_t num_used_long_registers{}; |
| 148 | std::bitset<NUM_REGS> register_use{}; | 147 | std::bitset<NUM_REGS> register_use{}; |
diff --git a/src/shader_recompiler/backend/glsl/emit_glsl_floating_point.cpp b/src/shader_recompiler/backend/glsl/emit_glsl_floating_point.cpp index b11be5bd7..2edcf592e 100644 --- a/src/shader_recompiler/backend/glsl/emit_glsl_floating_point.cpp +++ b/src/shader_recompiler/backend/glsl/emit_glsl_floating_point.cpp | |||
| @@ -22,7 +22,7 @@ void Compare(EmitContext& ctx, IR::Inst& inst, std::string_view lhs, std::string | |||
| 22 | } | 22 | } |
| 23 | 23 | ||
| 24 | bool IsPrecise(const IR::Inst& inst) { | 24 | bool IsPrecise(const IR::Inst& inst) { |
| 25 | return {inst.Flags<IR::FpControl>().no_contraction}; | 25 | return inst.Flags<IR::FpControl>().no_contraction; |
| 26 | } | 26 | } |
| 27 | } // Anonymous namespace | 27 | } // Anonymous namespace |
| 28 | 28 | ||
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp index 647804814..3588f052b 100644 --- a/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp +++ b/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp | |||
| @@ -109,7 +109,7 @@ private: | |||
| 109 | return; | 109 | return; |
| 110 | } | 110 | } |
| 111 | if (offset.IsImmediate()) { | 111 | if (offset.IsImmediate()) { |
| 112 | Add(spv::ImageOperandsMask::ConstOffset, ctx.SConst(offset.U32())); | 112 | Add(spv::ImageOperandsMask::ConstOffset, ctx.SConst(static_cast<s32>(offset.U32()))); |
| 113 | return; | 113 | return; |
| 114 | } | 114 | } |
| 115 | IR::Inst* const inst{offset.InstRecursive()}; | 115 | IR::Inst* const inst{offset.InstRecursive()}; |
| @@ -117,16 +117,21 @@ private: | |||
| 117 | switch (inst->GetOpcode()) { | 117 | switch (inst->GetOpcode()) { |
| 118 | case IR::Opcode::CompositeConstructU32x2: | 118 | case IR::Opcode::CompositeConstructU32x2: |
| 119 | Add(spv::ImageOperandsMask::ConstOffset, | 119 | Add(spv::ImageOperandsMask::ConstOffset, |
| 120 | ctx.SConst(inst->Arg(0).U32(), inst->Arg(1).U32())); | 120 | ctx.SConst(static_cast<s32>(inst->Arg(0).U32()), |
| 121 | static_cast<s32>(inst->Arg(1).U32()))); | ||
| 121 | return; | 122 | return; |
| 122 | case IR::Opcode::CompositeConstructU32x3: | 123 | case IR::Opcode::CompositeConstructU32x3: |
| 123 | Add(spv::ImageOperandsMask::ConstOffset, | 124 | Add(spv::ImageOperandsMask::ConstOffset, |
| 124 | ctx.SConst(inst->Arg(0).U32(), inst->Arg(1).U32(), inst->Arg(2).U32())); | 125 | ctx.SConst(static_cast<s32>(inst->Arg(0).U32()), |
| 126 | static_cast<s32>(inst->Arg(1).U32()), | ||
| 127 | static_cast<s32>(inst->Arg(2).U32()))); | ||
| 125 | return; | 128 | return; |
| 126 | case IR::Opcode::CompositeConstructU32x4: | 129 | case IR::Opcode::CompositeConstructU32x4: |
| 127 | Add(spv::ImageOperandsMask::ConstOffset, | 130 | Add(spv::ImageOperandsMask::ConstOffset, |
| 128 | ctx.SConst(inst->Arg(0).U32(), inst->Arg(1).U32(), inst->Arg(2).U32(), | 131 | ctx.SConst(static_cast<s32>(inst->Arg(0).U32()), |
| 129 | inst->Arg(3).U32())); | 132 | static_cast<s32>(inst->Arg(1).U32()), |
| 133 | static_cast<s32>(inst->Arg(2).U32()), | ||
| 134 | static_cast<s32>(inst->Arg(3).U32()))); | ||
| 130 | return; | 135 | return; |
| 131 | default: | 136 | default: |
| 132 | break; | 137 | break; |