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| author | 2021-04-11 19:16:47 -0300 | |
|---|---|---|
| committer | 2021-07-22 21:51:27 -0400 | |
| commit | 2ed80f6b1e85823d7a13dfbb119545a0a0ec7427 (patch) | |
| tree | 5025ced89b185ae325f0c490699889a2b8dad415 /src/shader_recompiler/backend | |
| parent | shader: Implement SR_THREAD_KILL (diff) | |
| download | yuzu-2ed80f6b1e85823d7a13dfbb119545a0a0ec7427.tar.gz yuzu-2ed80f6b1e85823d7a13dfbb119545a0a0ec7427.tar.xz yuzu-2ed80f6b1e85823d7a13dfbb119545a0a0ec7427.zip | |
shader: Implement LOP CC
Diffstat (limited to 'src/shader_recompiler/backend')
| -rw-r--r-- | src/shader_recompiler/backend/spirv/emit_spirv.h | 6 | ||||
| -rw-r--r-- | src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp | 21 |
2 files changed, 18 insertions, 9 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv.h b/src/shader_recompiler/backend/spirv/emit_spirv.h index 04340fa70..150477ff6 100644 --- a/src/shader_recompiler/backend/spirv/emit_spirv.h +++ b/src/shader_recompiler/backend/spirv/emit_spirv.h | |||
| @@ -280,9 +280,9 @@ Id EmitShiftRightLogical32(EmitContext& ctx, Id base, Id shift); | |||
| 280 | Id EmitShiftRightLogical64(EmitContext& ctx, Id base, Id shift); | 280 | Id EmitShiftRightLogical64(EmitContext& ctx, Id base, Id shift); |
| 281 | Id EmitShiftRightArithmetic32(EmitContext& ctx, Id base, Id shift); | 281 | Id EmitShiftRightArithmetic32(EmitContext& ctx, Id base, Id shift); |
| 282 | Id EmitShiftRightArithmetic64(EmitContext& ctx, Id base, Id shift); | 282 | Id EmitShiftRightArithmetic64(EmitContext& ctx, Id base, Id shift); |
| 283 | Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b); | 283 | Id EmitBitwiseAnd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b); |
| 284 | Id EmitBitwiseOr32(EmitContext& ctx, Id a, Id b); | 284 | Id EmitBitwiseOr32(EmitContext& ctx, IR::Inst* inst, Id a, Id b); |
| 285 | Id EmitBitwiseXor32(EmitContext& ctx, Id a, Id b); | 285 | Id EmitBitwiseXor32(EmitContext& ctx, IR::Inst* inst, Id a, Id b); |
| 286 | Id EmitBitFieldInsert(EmitContext& ctx, Id base, Id insert, Id offset, Id count); | 286 | Id EmitBitFieldInsert(EmitContext& ctx, Id base, Id insert, Id offset, Id count); |
| 287 | Id EmitBitFieldSExtract(EmitContext& ctx, IR::Inst* inst, Id base, Id offset, Id count); | 287 | Id EmitBitFieldSExtract(EmitContext& ctx, IR::Inst* inst, Id base, Id offset, Id count); |
| 288 | Id EmitBitFieldUExtract(EmitContext& ctx, IR::Inst* inst, Id base, Id offset, Id count); | 288 | Id EmitBitFieldUExtract(EmitContext& ctx, IR::Inst* inst, Id base, Id offset, Id count); |
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp index 8bf43b91d..944f1e429 100644 --- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp +++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp | |||
| @@ -111,16 +111,25 @@ Id EmitShiftRightArithmetic64(EmitContext& ctx, Id base, Id shift) { | |||
| 111 | return ctx.OpShiftRightArithmetic(ctx.U64, base, shift); | 111 | return ctx.OpShiftRightArithmetic(ctx.U64, base, shift); |
| 112 | } | 112 | } |
| 113 | 113 | ||
| 114 | Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b) { | 114 | Id EmitBitwiseAnd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) { |
| 115 | return ctx.OpBitwiseAnd(ctx.U32[1], a, b); | 115 | const Id result{ctx.OpBitwiseAnd(ctx.U32[1], a, b)}; |
| 116 | SetZeroFlag(ctx, inst, result); | ||
| 117 | SetSignFlag(ctx, inst, result); | ||
| 118 | return result; | ||
| 116 | } | 119 | } |
| 117 | 120 | ||
| 118 | Id EmitBitwiseOr32(EmitContext& ctx, Id a, Id b) { | 121 | Id EmitBitwiseOr32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) { |
| 119 | return ctx.OpBitwiseOr(ctx.U32[1], a, b); | 122 | const Id result{ctx.OpBitwiseOr(ctx.U32[1], a, b)}; |
| 123 | SetZeroFlag(ctx, inst, result); | ||
| 124 | SetSignFlag(ctx, inst, result); | ||
| 125 | return result; | ||
| 120 | } | 126 | } |
| 121 | 127 | ||
| 122 | Id EmitBitwiseXor32(EmitContext& ctx, Id a, Id b) { | 128 | Id EmitBitwiseXor32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) { |
| 123 | return ctx.OpBitwiseXor(ctx.U32[1], a, b); | 129 | const Id result{ctx.OpBitwiseXor(ctx.U32[1], a, b)}; |
| 130 | SetZeroFlag(ctx, inst, result); | ||
| 131 | SetSignFlag(ctx, inst, result); | ||
| 132 | return result; | ||
| 124 | } | 133 | } |
| 125 | 134 | ||
| 126 | Id EmitBitFieldInsert(EmitContext& ctx, Id base, Id insert, Id offset, Id count) { | 135 | Id EmitBitFieldInsert(EmitContext& ctx, Id base, Id insert, Id offset, Id count) { |