diff options
| author | 2021-02-22 22:59:16 -0300 | |
|---|---|---|
| committer | 2021-07-22 21:51:22 -0400 | |
| commit | e44752ddc8804961eb84f8c225bb36d5b4c77bc1 (patch) | |
| tree | 84df0e38680470a0ee8c2230625193c4156ddea6 /src/shader_recompiler/backend/spirv | |
| parent | shader: Fix MOV(reg), add SHL variants and emit neg and abs instructions (diff) | |
| download | yuzu-e44752ddc8804961eb84f8c225bb36d5b4c77bc1.tar.gz yuzu-e44752ddc8804961eb84f8c225bb36d5b4c77bc1.tar.xz yuzu-e44752ddc8804961eb84f8c225bb36d5b4c77bc1.zip | |
shader: FMUL, select, RRO, and MUFU fixes
Diffstat (limited to 'src/shader_recompiler/backend/spirv')
3 files changed, 228 insertions, 52 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv.h b/src/shader_recompiler/backend/spirv/emit_spirv.h index 1b9be445e..130c71996 100644 --- a/src/shader_recompiler/backend/spirv/emit_spirv.h +++ b/src/shader_recompiler/backend/spirv/emit_spirv.h | |||
| @@ -108,10 +108,12 @@ void EmitCompositeConstructF64x4(EmitContext& ctx); | |||
| 108 | void EmitCompositeExtractF64x2(EmitContext& ctx); | 108 | void EmitCompositeExtractF64x2(EmitContext& ctx); |
| 109 | void EmitCompositeExtractF64x3(EmitContext& ctx); | 109 | void EmitCompositeExtractF64x3(EmitContext& ctx); |
| 110 | void EmitCompositeExtractF64x4(EmitContext& ctx); | 110 | void EmitCompositeExtractF64x4(EmitContext& ctx); |
| 111 | void EmitSelect8(EmitContext& ctx); | 111 | Id EmitSelectU8(EmitContext& ctx, Id cond, Id true_value, Id false_value); |
| 112 | void EmitSelect16(EmitContext& ctx); | 112 | Id EmitSelectU16(EmitContext& ctx, Id cond, Id true_value, Id false_value); |
| 113 | Id EmitSelect32(EmitContext& ctx, Id cond, Id true_value, Id false_value); | 113 | Id EmitSelectU32(EmitContext& ctx, Id cond, Id true_value, Id false_value); |
| 114 | void EmitSelect64(EmitContext& ctx); | 114 | Id EmitSelectU64(EmitContext& ctx, Id cond, Id true_value, Id false_value); |
| 115 | Id EmitSelectF16(EmitContext& ctx, Id cond, Id true_value, Id false_value); | ||
| 116 | Id EmitSelectF32(EmitContext& ctx, Id cond, Id true_value, Id false_value); | ||
| 115 | void EmitBitCastU16F16(EmitContext& ctx); | 117 | void EmitBitCastU16F16(EmitContext& ctx); |
| 116 | Id EmitBitCastU32F32(EmitContext& ctx, Id value); | 118 | Id EmitBitCastU32F32(EmitContext& ctx, Id value); |
| 117 | void EmitBitCastU64F64(EmitContext& ctx); | 119 | void EmitBitCastU64F64(EmitContext& ctx); |
| @@ -149,18 +151,15 @@ Id EmitFPMul64(EmitContext& ctx, IR::Inst* inst, Id a, Id b); | |||
| 149 | Id EmitFPNeg16(EmitContext& ctx, Id value); | 151 | Id EmitFPNeg16(EmitContext& ctx, Id value); |
| 150 | Id EmitFPNeg32(EmitContext& ctx, Id value); | 152 | Id EmitFPNeg32(EmitContext& ctx, Id value); |
| 151 | Id EmitFPNeg64(EmitContext& ctx, Id value); | 153 | Id EmitFPNeg64(EmitContext& ctx, Id value); |
| 152 | void EmitFPRecip32(EmitContext& ctx); | 154 | Id EmitFPSin(EmitContext& ctx, Id value); |
| 153 | void EmitFPRecip64(EmitContext& ctx); | 155 | Id EmitFPCos(EmitContext& ctx, Id value); |
| 154 | void EmitFPRecipSqrt32(EmitContext& ctx); | 156 | Id EmitFPExp2(EmitContext& ctx, Id value); |
| 155 | void EmitFPRecipSqrt64(EmitContext& ctx); | 157 | Id EmitFPLog2(EmitContext& ctx, Id value); |
| 156 | void EmitFPSqrt(EmitContext& ctx); | 158 | Id EmitFPRecip32(EmitContext& ctx, Id value); |
| 157 | void EmitFPSin(EmitContext& ctx); | 159 | Id EmitFPRecip64(EmitContext& ctx, Id value); |
| 158 | void EmitFPSinNotReduced(EmitContext& ctx); | 160 | Id EmitFPRecipSqrt32(EmitContext& ctx, Id value); |
| 159 | void EmitFPExp2(EmitContext& ctx); | 161 | Id EmitFPRecipSqrt64(EmitContext& ctx, Id value); |
| 160 | void EmitFPExp2NotReduced(EmitContext& ctx); | 162 | Id EmitFPSqrt(EmitContext& ctx, Id value); |
| 161 | void EmitFPCos(EmitContext& ctx); | ||
| 162 | void EmitFPCosNotReduced(EmitContext& ctx); | ||
| 163 | void EmitFPLog2(EmitContext& ctx); | ||
| 164 | Id EmitFPSaturate16(EmitContext& ctx, Id value); | 163 | Id EmitFPSaturate16(EmitContext& ctx, Id value); |
| 165 | Id EmitFPSaturate32(EmitContext& ctx, Id value); | 164 | Id EmitFPSaturate32(EmitContext& ctx, Id value); |
| 166 | Id EmitFPSaturate64(EmitContext& ctx, Id value); | 165 | Id EmitFPSaturate64(EmitContext& ctx, Id value); |
| @@ -176,6 +175,42 @@ Id EmitFPCeil64(EmitContext& ctx, Id value); | |||
| 176 | Id EmitFPTrunc16(EmitContext& ctx, Id value); | 175 | Id EmitFPTrunc16(EmitContext& ctx, Id value); |
| 177 | Id EmitFPTrunc32(EmitContext& ctx, Id value); | 176 | Id EmitFPTrunc32(EmitContext& ctx, Id value); |
| 178 | Id EmitFPTrunc64(EmitContext& ctx, Id value); | 177 | Id EmitFPTrunc64(EmitContext& ctx, Id value); |
| 178 | Id EmitFPOrdEqual16(EmitContext& ctx, Id lhs, Id rhs); | ||
| 179 | Id EmitFPOrdEqual32(EmitContext& ctx, Id lhs, Id rhs); | ||
| 180 | Id EmitFPOrdEqual64(EmitContext& ctx, Id lhs, Id rhs); | ||
| 181 | Id EmitFPUnordEqual16(EmitContext& ctx, Id lhs, Id rhs); | ||
| 182 | Id EmitFPUnordEqual32(EmitContext& ctx, Id lhs, Id rhs); | ||
| 183 | Id EmitFPUnordEqual64(EmitContext& ctx, Id lhs, Id rhs); | ||
| 184 | Id EmitFPOrdNotEqual16(EmitContext& ctx, Id lhs, Id rhs); | ||
| 185 | Id EmitFPOrdNotEqual32(EmitContext& ctx, Id lhs, Id rhs); | ||
| 186 | Id EmitFPOrdNotEqual64(EmitContext& ctx, Id lhs, Id rhs); | ||
| 187 | Id EmitFPUnordNotEqual16(EmitContext& ctx, Id lhs, Id rhs); | ||
| 188 | Id EmitFPUnordNotEqual32(EmitContext& ctx, Id lhs, Id rhs); | ||
| 189 | Id EmitFPUnordNotEqual64(EmitContext& ctx, Id lhs, Id rhs); | ||
| 190 | Id EmitFPOrdLessThan16(EmitContext& ctx, Id lhs, Id rhs); | ||
| 191 | Id EmitFPOrdLessThan32(EmitContext& ctx, Id lhs, Id rhs); | ||
| 192 | Id EmitFPOrdLessThan64(EmitContext& ctx, Id lhs, Id rhs); | ||
| 193 | Id EmitFPUnordLessThan16(EmitContext& ctx, Id lhs, Id rhs); | ||
| 194 | Id EmitFPUnordLessThan32(EmitContext& ctx, Id lhs, Id rhs); | ||
| 195 | Id EmitFPUnordLessThan64(EmitContext& ctx, Id lhs, Id rhs); | ||
| 196 | Id EmitFPOrdGreaterThan16(EmitContext& ctx, Id lhs, Id rhs); | ||
| 197 | Id EmitFPOrdGreaterThan32(EmitContext& ctx, Id lhs, Id rhs); | ||
| 198 | Id EmitFPOrdGreaterThan64(EmitContext& ctx, Id lhs, Id rhs); | ||
| 199 | Id EmitFPUnordGreaterThan16(EmitContext& ctx, Id lhs, Id rhs); | ||
| 200 | Id EmitFPUnordGreaterThan32(EmitContext& ctx, Id lhs, Id rhs); | ||
| 201 | Id EmitFPUnordGreaterThan64(EmitContext& ctx, Id lhs, Id rhs); | ||
| 202 | Id EmitFPOrdLessThanEqual16(EmitContext& ctx, Id lhs, Id rhs); | ||
| 203 | Id EmitFPOrdLessThanEqual32(EmitContext& ctx, Id lhs, Id rhs); | ||
| 204 | Id EmitFPOrdLessThanEqual64(EmitContext& ctx, Id lhs, Id rhs); | ||
| 205 | Id EmitFPUnordLessThanEqual16(EmitContext& ctx, Id lhs, Id rhs); | ||
| 206 | Id EmitFPUnordLessThanEqual32(EmitContext& ctx, Id lhs, Id rhs); | ||
| 207 | Id EmitFPUnordLessThanEqual64(EmitContext& ctx, Id lhs, Id rhs); | ||
| 208 | Id EmitFPOrdGreaterThanEqual16(EmitContext& ctx, Id lhs, Id rhs); | ||
| 209 | Id EmitFPOrdGreaterThanEqual32(EmitContext& ctx, Id lhs, Id rhs); | ||
| 210 | Id EmitFPOrdGreaterThanEqual64(EmitContext& ctx, Id lhs, Id rhs); | ||
| 211 | Id EmitFPUnordGreaterThanEqual16(EmitContext& ctx, Id lhs, Id rhs); | ||
| 212 | Id EmitFPUnordGreaterThanEqual32(EmitContext& ctx, Id lhs, Id rhs); | ||
| 213 | Id EmitFPUnordGreaterThanEqual64(EmitContext& ctx, Id lhs, Id rhs); | ||
| 179 | Id EmitIAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b); | 214 | Id EmitIAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b); |
| 180 | void EmitIAdd64(EmitContext& ctx); | 215 | void EmitIAdd64(EmitContext& ctx); |
| 181 | Id EmitISub32(EmitContext& ctx, Id a, Id b); | 216 | Id EmitISub32(EmitContext& ctx, Id a, Id b); |
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_floating_point.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_floating_point.cpp index 5d0b74f9b..749f11742 100644 --- a/src/shader_recompiler/backend/spirv/emit_spirv_floating_point.cpp +++ b/src/shader_recompiler/backend/spirv/emit_spirv_floating_point.cpp | |||
| @@ -100,52 +100,40 @@ Id EmitFPNeg64(EmitContext& ctx, Id value) { | |||
| 100 | return ctx.OpFNegate(ctx.F64[1], value); | 100 | return ctx.OpFNegate(ctx.F64[1], value); |
| 101 | } | 101 | } |
| 102 | 102 | ||
| 103 | void EmitFPRecip32(EmitContext&) { | 103 | Id EmitFPSin(EmitContext& ctx, Id value) { |
| 104 | throw NotImplementedException("SPIR-V Instruction"); | 104 | return ctx.OpSin(ctx.F32[1], value); |
| 105 | } | ||
| 106 | |||
| 107 | void EmitFPRecip64(EmitContext&) { | ||
| 108 | throw NotImplementedException("SPIR-V Instruction"); | ||
| 109 | } | 105 | } |
| 110 | 106 | ||
| 111 | void EmitFPRecipSqrt32(EmitContext&) { | 107 | Id EmitFPCos(EmitContext& ctx, Id value) { |
| 112 | throw NotImplementedException("SPIR-V Instruction"); | 108 | return ctx.OpCos(ctx.F32[1], value); |
| 113 | } | 109 | } |
| 114 | 110 | ||
| 115 | void EmitFPRecipSqrt64(EmitContext&) { | 111 | Id EmitFPExp2(EmitContext& ctx, Id value) { |
| 116 | throw NotImplementedException("SPIR-V Instruction"); | 112 | return ctx.OpExp2(ctx.F32[1], value); |
| 117 | } | 113 | } |
| 118 | 114 | ||
| 119 | void EmitFPSqrt(EmitContext&) { | 115 | Id EmitFPLog2(EmitContext& ctx, Id value) { |
| 120 | throw NotImplementedException("SPIR-V Instruction"); | 116 | return ctx.OpLog2(ctx.F32[1], value); |
| 121 | } | 117 | } |
| 122 | 118 | ||
| 123 | void EmitFPSin(EmitContext&) { | 119 | Id EmitFPRecip32(EmitContext& ctx, Id value) { |
| 124 | throw NotImplementedException("SPIR-V Instruction"); | 120 | return ctx.OpFDiv(ctx.F32[1], ctx.Constant(ctx.F32[1], 1.0f), value); |
| 125 | } | 121 | } |
| 126 | 122 | ||
| 127 | void EmitFPSinNotReduced(EmitContext&) { | 123 | Id EmitFPRecip64(EmitContext& ctx, Id value) { |
| 128 | throw NotImplementedException("SPIR-V Instruction"); | 124 | return ctx.OpFDiv(ctx.F64[1], ctx.Constant(ctx.F64[1], 1.0f), value); |
| 129 | } | 125 | } |
| 130 | 126 | ||
| 131 | void EmitFPExp2(EmitContext&) { | 127 | Id EmitFPRecipSqrt32(EmitContext& ctx, Id value) { |
| 132 | throw NotImplementedException("SPIR-V Instruction"); | 128 | return ctx.OpInverseSqrt(ctx.F32[1], value); |
| 133 | } | 129 | } |
| 134 | 130 | ||
| 135 | void EmitFPExp2NotReduced(EmitContext&) { | 131 | Id EmitFPRecipSqrt64(EmitContext& ctx, Id value) { |
| 136 | throw NotImplementedException("SPIR-V Instruction"); | 132 | return ctx.OpInverseSqrt(ctx.F64[1], value); |
| 137 | } | 133 | } |
| 138 | 134 | ||
| 139 | void EmitFPCos(EmitContext&) { | 135 | Id EmitFPSqrt(EmitContext& ctx, Id value) { |
| 140 | throw NotImplementedException("SPIR-V Instruction"); | 136 | return ctx.OpSqrt(ctx.F32[1], value); |
| 141 | } | ||
| 142 | |||
| 143 | void EmitFPCosNotReduced(EmitContext&) { | ||
| 144 | throw NotImplementedException("SPIR-V Instruction"); | ||
| 145 | } | ||
| 146 | |||
| 147 | void EmitFPLog2(EmitContext&) { | ||
| 148 | throw NotImplementedException("SPIR-V Instruction"); | ||
| 149 | } | 137 | } |
| 150 | 138 | ||
| 151 | Id EmitFPSaturate16(EmitContext& ctx, Id value) { | 139 | Id EmitFPSaturate16(EmitContext& ctx, Id value) { |
| @@ -214,4 +202,148 @@ Id EmitFPTrunc64(EmitContext& ctx, Id value) { | |||
| 214 | return ctx.OpTrunc(ctx.F64[1], value); | 202 | return ctx.OpTrunc(ctx.F64[1], value); |
| 215 | } | 203 | } |
| 216 | 204 | ||
| 205 | Id EmitFPOrdEqual16(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 206 | return ctx.OpFOrdEqual(ctx.U1, lhs, rhs); | ||
| 207 | } | ||
| 208 | |||
| 209 | Id EmitFPOrdEqual32(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 210 | return ctx.OpFOrdEqual(ctx.U1, lhs, rhs); | ||
| 211 | } | ||
| 212 | |||
| 213 | Id EmitFPOrdEqual64(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 214 | return ctx.OpFOrdEqual(ctx.U1, lhs, rhs); | ||
| 215 | } | ||
| 216 | |||
| 217 | Id EmitFPUnordEqual16(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 218 | return ctx.OpFUnordEqual(ctx.U1, lhs, rhs); | ||
| 219 | } | ||
| 220 | |||
| 221 | Id EmitFPUnordEqual32(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 222 | return ctx.OpFUnordEqual(ctx.U1, lhs, rhs); | ||
| 223 | } | ||
| 224 | |||
| 225 | Id EmitFPUnordEqual64(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 226 | return ctx.OpFUnordEqual(ctx.U1, lhs, rhs); | ||
| 227 | } | ||
| 228 | |||
| 229 | Id EmitFPOrdNotEqual16(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 230 | return ctx.OpFOrdNotEqual(ctx.U1, lhs, rhs); | ||
| 231 | } | ||
| 232 | |||
| 233 | Id EmitFPOrdNotEqual32(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 234 | return ctx.OpFOrdNotEqual(ctx.U1, lhs, rhs); | ||
| 235 | } | ||
| 236 | |||
| 237 | Id EmitFPOrdNotEqual64(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 238 | return ctx.OpFOrdNotEqual(ctx.U1, lhs, rhs); | ||
| 239 | } | ||
| 240 | |||
| 241 | Id EmitFPUnordNotEqual16(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 242 | return ctx.OpFUnordNotEqual(ctx.U1, lhs, rhs); | ||
| 243 | } | ||
| 244 | |||
| 245 | Id EmitFPUnordNotEqual32(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 246 | return ctx.OpFUnordNotEqual(ctx.U1, lhs, rhs); | ||
| 247 | } | ||
| 248 | |||
| 249 | Id EmitFPUnordNotEqual64(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 250 | return ctx.OpFUnordNotEqual(ctx.U1, lhs, rhs); | ||
| 251 | } | ||
| 252 | |||
| 253 | Id EmitFPOrdLessThan16(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 254 | return ctx.OpFOrdLessThan(ctx.U1, lhs, rhs); | ||
| 255 | } | ||
| 256 | |||
| 257 | Id EmitFPOrdLessThan32(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 258 | return ctx.OpFOrdLessThan(ctx.U1, lhs, rhs); | ||
| 259 | } | ||
| 260 | |||
| 261 | Id EmitFPOrdLessThan64(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 262 | return ctx.OpFOrdLessThan(ctx.U1, lhs, rhs); | ||
| 263 | } | ||
| 264 | |||
| 265 | Id EmitFPUnordLessThan16(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 266 | return ctx.OpFUnordLessThan(ctx.U1, lhs, rhs); | ||
| 267 | } | ||
| 268 | |||
| 269 | Id EmitFPUnordLessThan32(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 270 | return ctx.OpFUnordLessThan(ctx.U1, lhs, rhs); | ||
| 271 | } | ||
| 272 | |||
| 273 | Id EmitFPUnordLessThan64(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 274 | return ctx.OpFUnordLessThan(ctx.U1, lhs, rhs); | ||
| 275 | } | ||
| 276 | |||
| 277 | Id EmitFPOrdGreaterThan16(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 278 | return ctx.OpFOrdGreaterThan(ctx.U1, lhs, rhs); | ||
| 279 | } | ||
| 280 | |||
| 281 | Id EmitFPOrdGreaterThan32(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 282 | return ctx.OpFOrdGreaterThan(ctx.U1, lhs, rhs); | ||
| 283 | } | ||
| 284 | |||
| 285 | Id EmitFPOrdGreaterThan64(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 286 | return ctx.OpFOrdGreaterThan(ctx.U1, lhs, rhs); | ||
| 287 | } | ||
| 288 | |||
| 289 | Id EmitFPUnordGreaterThan16(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 290 | return ctx.OpFUnordGreaterThan(ctx.U1, lhs, rhs); | ||
| 291 | } | ||
| 292 | |||
| 293 | Id EmitFPUnordGreaterThan32(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 294 | return ctx.OpFUnordGreaterThan(ctx.U1, lhs, rhs); | ||
| 295 | } | ||
| 296 | |||
| 297 | Id EmitFPUnordGreaterThan64(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 298 | return ctx.OpFUnordGreaterThan(ctx.U1, lhs, rhs); | ||
| 299 | } | ||
| 300 | |||
| 301 | Id EmitFPOrdLessThanEqual16(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 302 | return ctx.OpFOrdLessThanEqual(ctx.U1, lhs, rhs); | ||
| 303 | } | ||
| 304 | |||
| 305 | Id EmitFPOrdLessThanEqual32(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 306 | return ctx.OpFOrdLessThanEqual(ctx.U1, lhs, rhs); | ||
| 307 | } | ||
| 308 | |||
| 309 | Id EmitFPOrdLessThanEqual64(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 310 | return ctx.OpFOrdLessThanEqual(ctx.U1, lhs, rhs); | ||
| 311 | } | ||
| 312 | |||
| 313 | Id EmitFPUnordLessThanEqual16(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 314 | return ctx.OpFUnordLessThanEqual(ctx.U1, lhs, rhs); | ||
| 315 | } | ||
| 316 | |||
| 317 | Id EmitFPUnordLessThanEqual32(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 318 | return ctx.OpFUnordLessThanEqual(ctx.U1, lhs, rhs); | ||
| 319 | } | ||
| 320 | |||
| 321 | Id EmitFPUnordLessThanEqual64(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 322 | return ctx.OpFUnordLessThanEqual(ctx.U1, lhs, rhs); | ||
| 323 | } | ||
| 324 | |||
| 325 | Id EmitFPOrdGreaterThanEqual16(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 326 | return ctx.OpFOrdGreaterThanEqual(ctx.U1, lhs, rhs); | ||
| 327 | } | ||
| 328 | |||
| 329 | Id EmitFPOrdGreaterThanEqual32(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 330 | return ctx.OpFOrdGreaterThanEqual(ctx.U1, lhs, rhs); | ||
| 331 | } | ||
| 332 | |||
| 333 | Id EmitFPOrdGreaterThanEqual64(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 334 | return ctx.OpFOrdGreaterThanEqual(ctx.U1, lhs, rhs); | ||
| 335 | } | ||
| 336 | |||
| 337 | Id EmitFPUnordGreaterThanEqual16(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 338 | return ctx.OpFUnordGreaterThanEqual(ctx.U1, lhs, rhs); | ||
| 339 | } | ||
| 340 | |||
| 341 | Id EmitFPUnordGreaterThanEqual32(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 342 | return ctx.OpFUnordGreaterThanEqual(ctx.U1, lhs, rhs); | ||
| 343 | } | ||
| 344 | |||
| 345 | Id EmitFPUnordGreaterThanEqual64(EmitContext& ctx, Id lhs, Id rhs) { | ||
| 346 | return ctx.OpFUnordGreaterThanEqual(ctx.U1, lhs, rhs); | ||
| 347 | } | ||
| 348 | |||
| 217 | } // namespace Shader::Backend::SPIRV | 349 | } // namespace Shader::Backend::SPIRV |
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_select.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_select.cpp index eb1926a4d..21cca4455 100644 --- a/src/shader_recompiler/backend/spirv/emit_spirv_select.cpp +++ b/src/shader_recompiler/backend/spirv/emit_spirv_select.cpp | |||
| @@ -6,20 +6,29 @@ | |||
| 6 | 6 | ||
| 7 | namespace Shader::Backend::SPIRV { | 7 | namespace Shader::Backend::SPIRV { |
| 8 | 8 | ||
| 9 | void EmitSelect8(EmitContext&) { | 9 | Id EmitSelectU8([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] Id cond, |
| 10 | [[maybe_unused]] Id true_value, [[maybe_unused]] Id false_value) { | ||
| 10 | throw NotImplementedException("SPIR-V Instruction"); | 11 | throw NotImplementedException("SPIR-V Instruction"); |
| 11 | } | 12 | } |
| 12 | 13 | ||
| 13 | void EmitSelect16(EmitContext&) { | 14 | Id EmitSelectU16(EmitContext& ctx, Id cond, Id true_value, Id false_value) { |
| 14 | throw NotImplementedException("SPIR-V Instruction"); | 15 | return ctx.OpSelect(ctx.U16, cond, true_value, false_value); |
| 15 | } | 16 | } |
| 16 | 17 | ||
| 17 | Id EmitSelect32(EmitContext& ctx, Id cond, Id true_value, Id false_value) { | 18 | Id EmitSelectU32(EmitContext& ctx, Id cond, Id true_value, Id false_value) { |
| 18 | return ctx.OpSelect(ctx.U32[1], cond, true_value, false_value); | 19 | return ctx.OpSelect(ctx.U32[1], cond, true_value, false_value); |
| 19 | } | 20 | } |
| 20 | 21 | ||
| 21 | void EmitSelect64(EmitContext&) { | 22 | Id EmitSelectU64(EmitContext& ctx, Id cond, Id true_value, Id false_value) { |
| 22 | throw NotImplementedException("SPIR-V Instruction"); | 23 | return ctx.OpSelect(ctx.U64, cond, true_value, false_value); |
| 24 | } | ||
| 25 | |||
| 26 | Id EmitSelectF16(EmitContext& ctx, Id cond, Id true_value, Id false_value) { | ||
| 27 | return ctx.OpSelect(ctx.F16[1], cond, true_value, false_value); | ||
| 28 | } | ||
| 29 | |||
| 30 | Id EmitSelectF32(EmitContext& ctx, Id cond, Id true_value, Id false_value) { | ||
| 31 | return ctx.OpSelect(ctx.F32[1], cond, true_value, false_value); | ||
| 23 | } | 32 | } |
| 24 | 33 | ||
| 25 | } // namespace Shader::Backend::SPIRV | 34 | } // namespace Shader::Backend::SPIRV |