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| author | 2021-03-07 14:48:03 -0500 | |
|---|---|---|
| committer | 2021-07-22 21:51:23 -0400 | |
| commit | 924f0a9149b6777782347be3d2c833a5f8e90058 (patch) | |
| tree | 1bd15a053df1f337410b9a9c95809c4095afa459 /src/shader_recompiler/backend/spirv | |
| parent | shader: Implement LEA (diff) | |
| download | yuzu-924f0a9149b6777782347be3d2c833a5f8e90058.tar.gz yuzu-924f0a9149b6777782347be3d2c833a5f8e90058.tar.xz yuzu-924f0a9149b6777782347be3d2c833a5f8e90058.zip | |
shader: Implement SHF
Diffstat (limited to 'src/shader_recompiler/backend/spirv')
| -rw-r--r-- | src/shader_recompiler/backend/spirv/emit_spirv.h | 8 | ||||
| -rw-r--r-- | src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp | 20 |
2 files changed, 19 insertions, 9 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv.h b/src/shader_recompiler/backend/spirv/emit_spirv.h index 1f7d84871..bf1b5ace6 100644 --- a/src/shader_recompiler/backend/spirv/emit_spirv.h +++ b/src/shader_recompiler/backend/spirv/emit_spirv.h | |||
| @@ -232,9 +232,11 @@ Id EmitINeg32(EmitContext& ctx, Id value); | |||
| 232 | Id EmitINeg64(EmitContext& ctx, Id value); | 232 | Id EmitINeg64(EmitContext& ctx, Id value); |
| 233 | Id EmitIAbs32(EmitContext& ctx, Id value); | 233 | Id EmitIAbs32(EmitContext& ctx, Id value); |
| 234 | Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift); | 234 | Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift); |
| 235 | Id EmitShiftRightLogical32(EmitContext& ctx, Id a, Id b); | 235 | Id EmitShiftLeftLogical64(EmitContext& ctx, Id base, Id shift); |
| 236 | Id EmitShiftRightLogical64(EmitContext& ctx, Id a, Id b); | 236 | Id EmitShiftRightLogical32(EmitContext& ctx, Id base, Id shift); |
| 237 | Id EmitShiftRightArithmetic32(EmitContext& ctx, Id a, Id b); | 237 | Id EmitShiftRightLogical64(EmitContext& ctx, Id base, Id shift); |
| 238 | Id EmitShiftRightArithmetic32(EmitContext& ctx, Id base, Id shift); | ||
| 239 | Id EmitShiftRightArithmetic64(EmitContext& ctx, Id base, Id shift); | ||
| 238 | Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b); | 240 | Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b); |
| 239 | Id EmitBitwiseOr32(EmitContext& ctx, Id a, Id b); | 241 | Id EmitBitwiseOr32(EmitContext& ctx, Id a, Id b); |
| 240 | Id EmitBitwiseXor32(EmitContext& ctx, Id a, Id b); | 242 | Id EmitBitwiseXor32(EmitContext& ctx, Id a, Id b); |
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp index f5001cdaa..5ab3b5e86 100644 --- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp +++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp | |||
| @@ -74,16 +74,24 @@ Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift) { | |||
| 74 | return ctx.OpShiftLeftLogical(ctx.U32[1], base, shift); | 74 | return ctx.OpShiftLeftLogical(ctx.U32[1], base, shift); |
| 75 | } | 75 | } |
| 76 | 76 | ||
| 77 | Id EmitShiftRightLogical32(EmitContext& ctx, Id a, Id b) { | 77 | Id EmitShiftLeftLogical64(EmitContext& ctx, Id base, Id shift) { |
| 78 | return ctx.OpShiftRightLogical(ctx.U32[1], a, b); | 78 | return ctx.OpShiftLeftLogical(ctx.U64, base, shift); |
| 79 | } | 79 | } |
| 80 | 80 | ||
| 81 | Id EmitShiftRightLogical64(EmitContext& ctx, Id a, Id b) { | 81 | Id EmitShiftRightLogical32(EmitContext& ctx, Id base, Id shift) { |
| 82 | return ctx.OpShiftRightLogical(ctx.U64, a, b); | 82 | return ctx.OpShiftRightLogical(ctx.U32[1], base, shift); |
| 83 | } | 83 | } |
| 84 | 84 | ||
| 85 | Id EmitShiftRightArithmetic32(EmitContext& ctx, Id a, Id b) { | 85 | Id EmitShiftRightLogical64(EmitContext& ctx, Id base, Id shift) { |
| 86 | return ctx.OpShiftRightArithmetic(ctx.U32[1], a, b); | 86 | return ctx.OpShiftRightLogical(ctx.U64, base, shift); |
| 87 | } | ||
| 88 | |||
| 89 | Id EmitShiftRightArithmetic32(EmitContext& ctx, Id base, Id shift) { | ||
| 90 | return ctx.OpShiftRightArithmetic(ctx.U32[1], base, shift); | ||
| 91 | } | ||
| 92 | |||
| 93 | Id EmitShiftRightArithmetic64(EmitContext& ctx, Id base, Id shift) { | ||
| 94 | return ctx.OpShiftRightArithmetic(ctx.U64, base, shift); | ||
| 87 | } | 95 | } |
| 88 | 96 | ||
| 89 | Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b) { | 97 | Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b) { |