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| author | 2021-04-17 03:07:31 -0300 | |
|---|---|---|
| committer | 2021-07-22 21:51:28 -0400 | |
| commit | 7cfa403683f46cfca71ef2caf4ff53355eac47b2 (patch) | |
| tree | 29c3357670adce555fc1c6d710a7b2f2d7b78519 /src/shader_recompiler/backend/spirv | |
| parent | spirv: Use ConstOffset instead of Offset when possible (diff) | |
| download | yuzu-7cfa403683f46cfca71ef2caf4ff53355eac47b2.tar.gz yuzu-7cfa403683f46cfca71ef2caf4ff53355eac47b2.tar.xz yuzu-7cfa403683f46cfca71ef2caf4ff53355eac47b2.zip | |
spirv: Use explicit lods outside of fragment shaders
Diffstat (limited to 'src/shader_recompiler/backend/spirv')
| -rw-r--r-- | src/shader_recompiler/backend/spirv/emit_spirv_image.cpp | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp index 021933a8c..fea3bc112 100644 --- a/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp +++ b/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp | |||
| @@ -310,11 +310,22 @@ Id EmitBoundImageWrite(EmitContext&) { | |||
| 310 | Id EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords, | 310 | Id EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords, |
| 311 | Id bias_lc, const IR::Value& offset) { | 311 | Id bias_lc, const IR::Value& offset) { |
| 312 | const auto info{inst->Flags<IR::TextureInstInfo>()}; | 312 | const auto info{inst->Flags<IR::TextureInstInfo>()}; |
| 313 | const ImageOperands operands(ctx, info.has_bias != 0, false, info.has_lod_clamp != 0, bias_lc, | 313 | if (ctx.stage == Stage::Fragment) { |
| 314 | offset); | 314 | const ImageOperands operands(ctx, info.has_bias != 0, false, info.has_lod_clamp != 0, |
| 315 | return Emit(&EmitContext::OpImageSparseSampleImplicitLod, | 315 | bias_lc, offset); |
| 316 | &EmitContext::OpImageSampleImplicitLod, ctx, inst, ctx.F32[4], Texture(ctx, index), | 316 | return Emit(&EmitContext::OpImageSparseSampleImplicitLod, |
| 317 | coords, operands.Mask(), operands.Span()); | 317 | &EmitContext::OpImageSampleImplicitLod, ctx, inst, ctx.F32[4], |
| 318 | Texture(ctx, index), coords, operands.Mask(), operands.Span()); | ||
| 319 | } else { | ||
| 320 | // We can't use implicit lods on non-fragment stages on SPIR-V. Maxwell hardware behaves as | ||
| 321 | // if the lod was explicitly zero. This may change on Turing with implicit compute | ||
| 322 | // derivatives | ||
| 323 | const Id lod{ctx.Const(0)}; | ||
| 324 | const ImageOperands operands(ctx, false, true, info.has_lod_clamp != 0, lod, offset); | ||
| 325 | return Emit(&EmitContext::OpImageSparseSampleExplicitLod, | ||
| 326 | &EmitContext::OpImageSampleExplicitLod, ctx, inst, ctx.F32[4], | ||
| 327 | Texture(ctx, index), coords, operands.Mask(), operands.Span()); | ||
| 328 | } | ||
| 318 | } | 329 | } |
| 319 | 330 | ||
| 320 | Id EmitImageSampleExplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords, | 331 | Id EmitImageSampleExplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords, |