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authorGravatar ReinUsesLisp2021-02-21 23:42:38 -0300
committerGravatar ameerj2021-07-22 21:51:22 -0400
commit274897dfd59b4d08029ab7e93be4f84654abcdc8 (patch)
tree083336a4d665476a87b888368878a311a7edab2a /src/shader_recompiler/backend/spirv/emit_spirv_logical.cpp
parentshader: Rename, implement FADD.SAT and P2R (imm) (diff)
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spirv: Fixes and Intel specific workarounds
Diffstat (limited to 'src/shader_recompiler/backend/spirv/emit_spirv_logical.cpp')
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_logical.cpp16
1 files changed, 8 insertions, 8 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_logical.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_logical.cpp
index c5a07252f..bb434def2 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_logical.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_logical.cpp
@@ -6,20 +6,20 @@
6 6
7namespace Shader::Backend::SPIRV { 7namespace Shader::Backend::SPIRV {
8 8
9void EmitLogicalOr(EmitContext&) { 9Id EmitLogicalOr(EmitContext& ctx, Id a, Id b) {
10 throw NotImplementedException("SPIR-V Instruction"); 10 return ctx.OpLogicalOr(ctx.U1, a, b);
11} 11}
12 12
13void EmitLogicalAnd(EmitContext&) { 13Id EmitLogicalAnd(EmitContext& ctx, Id a, Id b) {
14 throw NotImplementedException("SPIR-V Instruction"); 14 return ctx.OpLogicalAnd(ctx.U1, a, b);
15} 15}
16 16
17void EmitLogicalXor(EmitContext&) { 17Id EmitLogicalXor(EmitContext& ctx, Id a, Id b) {
18 throw NotImplementedException("SPIR-V Instruction"); 18 return ctx.OpLogicalNotEqual(ctx.U1, a, b);
19} 19}
20 20
21void EmitLogicalNot(EmitContext&) { 21Id EmitLogicalNot(EmitContext& ctx, Id value) {
22 throw NotImplementedException("SPIR-V Instruction"); 22 return ctx.OpLogicalNot(ctx.U1, value);
23} 23}
24 24
25} // namespace Shader::Backend::SPIRV 25} // namespace Shader::Backend::SPIRV