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authorGravatar ameerj2021-03-27 23:01:28 -0400
committerGravatar ameerj2021-07-22 21:51:25 -0400
commitdbc1e5cde79b9165605741e1ea7158513ef6499f (patch)
treeba55cdcda905c716ac1bde0463103b425b20bed6 /src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
parentvk_pipeline_cache: Fix size hashing of shaders (diff)
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shader: Implement I2I SAT
Diffstat (limited to 'src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp')
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
index a9c5e9cca..37fc7c7a2 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
@@ -163,6 +163,14 @@ Id EmitUMax32(EmitContext& ctx, Id a, Id b) {
163 return ctx.OpUMax(ctx.U32[1], a, b); 163 return ctx.OpUMax(ctx.U32[1], a, b);
164} 164}
165 165
166Id EmitSClamp32(EmitContext& ctx, Id value, Id min, Id max) {
167 return ctx.OpSClamp(ctx.U32[1], value, min, max);
168}
169
170Id EmitUClamp32(EmitContext& ctx, Id value, Id min, Id max) {
171 return ctx.OpUClamp(ctx.U32[1], value, min, max);
172}
173
166Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) { 174Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) {
167 return ctx.OpSLessThan(ctx.U1, lhs, rhs); 175 return ctx.OpSLessThan(ctx.U1, lhs, rhs);
168} 176}