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authorGravatar ReinUsesLisp2021-02-23 04:46:39 -0300
committerGravatar ameerj2021-07-22 21:51:22 -0400
commit9d6a98d950da39dd2a7ca5ad25525de4fb825415 (patch)
treeed7374adf60d5330f78d48f0ccea65fd65702fac /src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
parentshader: FMUL, select, RRO, and MUFU fixes (diff)
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shader: Implement more of XMAD and FFMA32I and fix XMAD.CBCC
Diffstat (limited to 'src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp')
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
index 329dcb351..8aaa0e381 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
@@ -90,12 +90,12 @@ Id EmitBitwiseXor32(EmitContext& ctx, Id a, Id b) {
90 return ctx.OpBitwiseXor(ctx.U32[1], a, b); 90 return ctx.OpBitwiseXor(ctx.U32[1], a, b);
91} 91}
92 92
93void EmitBitFieldInsert(EmitContext&) { 93Id EmitBitFieldInsert(EmitContext& ctx, Id base, Id insert, Id offset, Id count) {
94 throw NotImplementedException("SPIR-V Instruction"); 94 return ctx.OpBitFieldInsert(ctx.U32[1], base, insert, offset, count);
95} 95}
96 96
97void EmitBitFieldSExtract(EmitContext&) { 97Id EmitBitFieldSExtract(EmitContext& ctx, Id base, Id offset, Id count) {
98 throw NotImplementedException("SPIR-V Instruction"); 98 return ctx.OpBitFieldSExtract(ctx.U32[1], base, offset, count);
99} 99}
100 100
101Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count) { 101Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count) {