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authorGravatar ameerj2021-03-07 14:48:03 -0500
committerGravatar ameerj2021-07-22 21:51:23 -0400
commit924f0a9149b6777782347be3d2c833a5f8e90058 (patch)
tree1bd15a053df1f337410b9a9c95809c4095afa459 /src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
parentshader: Implement LEA (diff)
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shader: Implement SHF
Diffstat (limited to 'src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp')
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp20
1 files changed, 14 insertions, 6 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
index f5001cdaa..5ab3b5e86 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
@@ -74,16 +74,24 @@ Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift) {
74 return ctx.OpShiftLeftLogical(ctx.U32[1], base, shift); 74 return ctx.OpShiftLeftLogical(ctx.U32[1], base, shift);
75} 75}
76 76
77Id EmitShiftRightLogical32(EmitContext& ctx, Id a, Id b) { 77Id EmitShiftLeftLogical64(EmitContext& ctx, Id base, Id shift) {
78 return ctx.OpShiftRightLogical(ctx.U32[1], a, b); 78 return ctx.OpShiftLeftLogical(ctx.U64, base, shift);
79} 79}
80 80
81Id EmitShiftRightLogical64(EmitContext& ctx, Id a, Id b) { 81Id EmitShiftRightLogical32(EmitContext& ctx, Id base, Id shift) {
82 return ctx.OpShiftRightLogical(ctx.U64, a, b); 82 return ctx.OpShiftRightLogical(ctx.U32[1], base, shift);
83} 83}
84 84
85Id EmitShiftRightArithmetic32(EmitContext& ctx, Id a, Id b) { 85Id EmitShiftRightLogical64(EmitContext& ctx, Id base, Id shift) {
86 return ctx.OpShiftRightArithmetic(ctx.U32[1], a, b); 86 return ctx.OpShiftRightLogical(ctx.U64, base, shift);
87}
88
89Id EmitShiftRightArithmetic32(EmitContext& ctx, Id base, Id shift) {
90 return ctx.OpShiftRightArithmetic(ctx.U32[1], base, shift);
91}
92
93Id EmitShiftRightArithmetic64(EmitContext& ctx, Id base, Id shift) {
94 return ctx.OpShiftRightArithmetic(ctx.U64, base, shift);
87} 95}
88 96
89Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b) { 97Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b) {