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| author | 2021-02-28 23:33:53 -0500 | |
|---|---|---|
| committer | 2021-07-22 21:51:22 -0400 | |
| commit | 20390c0548d6eef2af67a363ee120a630267b741 (patch) | |
| tree | 0df880552f80d79c769403f04df5c364397396d1 /src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp | |
| parent | shader: Implement BFI (diff) | |
| download | yuzu-20390c0548d6eef2af67a363ee120a630267b741.tar.gz yuzu-20390c0548d6eef2af67a363ee120a630267b741.tar.xz yuzu-20390c0548d6eef2af67a363ee120a630267b741.zip | |
shader: Implement IMNMX
Diffstat (limited to 'src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp')
| -rw-r--r-- | src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp index e49ca7bde..5bdd943a4 100644 --- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp +++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp | |||
| @@ -114,6 +114,22 @@ Id EmitBitwiseNot32(EmitContext& ctx, Id a) { | |||
| 114 | return ctx.OpNot(ctx.U32[1], a); | 114 | return ctx.OpNot(ctx.U32[1], a); |
| 115 | } | 115 | } |
| 116 | 116 | ||
| 117 | Id EmitSMin32(EmitContext& ctx, Id a, Id b) { | ||
| 118 | return ctx.OpSMin(ctx.U32[1], a, b); | ||
| 119 | } | ||
| 120 | |||
| 121 | Id EmitUMin32(EmitContext& ctx, Id a, Id b) { | ||
| 122 | return ctx.OpUMin(ctx.U32[1], a, b); | ||
| 123 | } | ||
| 124 | |||
| 125 | Id EmitSMax32(EmitContext& ctx, Id a, Id b) { | ||
| 126 | return ctx.OpSMax(ctx.U32[1], a, b); | ||
| 127 | } | ||
| 128 | |||
| 129 | Id EmitUMax32(EmitContext& ctx, Id a, Id b) { | ||
| 130 | return ctx.OpUMax(ctx.U32[1], a, b); | ||
| 131 | } | ||
| 132 | |||
| 117 | Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) { | 133 | Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) { |
| 118 | return ctx.OpSLessThan(ctx.U1, lhs, rhs); | 134 | return ctx.OpSLessThan(ctx.U1, lhs, rhs); |
| 119 | } | 135 | } |