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| author |  ReinUsesLisp | 2021-02-22 02:45:50 -0300 |
|---|---|---|
| committer |  ameerj | 2021-07-22 21:51:22 -0400 |
| commit | 18a766b3622baa40596490dbd4912f94e9980a76 (patch) | |
| tree | de34dbbbd81f6f980308b165a812445b224bd8fb /src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp | |
| parent | spirv: Fixes and Intel specific workarounds (diff) | |
| download | yuzu-18a766b3622baa40596490dbd4912f94e9980a76.tar.gz yuzu-18a766b3622baa40596490dbd4912f94e9980a76.tar.xz yuzu-18a766b3622baa40596490dbd4912f94e9980a76.zip | |
shader: Fix MOV(reg), add SHL variants and emit neg and abs instructions
Diffstat (limited to 'src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp')
| -rw-r--r-- | src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp index 4c0b5990d..329dcb351 100644 --- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp +++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp | |||
| @@ -58,12 +58,12 @@ Id EmitIMul32(EmitContext& ctx, Id a, Id b) { | |||
| 58 | return ctx.OpIMul(ctx.U32[1], a, b); | 58 | return ctx.OpIMul(ctx.U32[1], a, b); |
| 59 | } | 59 | } |
| 60 | 60 | ||
| 61 | void EmitINeg32(EmitContext&) { | 61 | Id EmitINeg32(EmitContext& ctx, Id value) { |
| 62 | throw NotImplementedException("SPIR-V Instruction"); | 62 | return ctx.OpSNegate(ctx.U32[1], value); |
| 63 | } | 63 | } |
| 64 | 64 | ||
| 65 | void EmitIAbs32(EmitContext&) { | 65 | Id EmitIAbs32(EmitContext& ctx, Id value) { |
| 66 | throw NotImplementedException("SPIR-V Instruction"); | 66 | return ctx.OpSAbs(ctx.U32[1], value); |
| 67 | } | 67 | } |
| 68 | 68 | ||
| 69 | Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift) { | 69 | Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift) { |