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| author | 2021-03-08 18:31:53 -0300 | |
|---|---|---|
| committer | 2021-07-22 21:51:23 -0400 | |
| commit | ab463712474de5f99eec137a9c6233e55fe184f0 (patch) | |
| tree | 30d79ac64dd03d5cfafd07c0c42c2baadc82de98 /src/shader_recompiler/backend/spirv/emit_spirv_convert.cpp | |
| parent | shader: Implement R2P (diff) | |
| download | yuzu-ab463712474de5f99eec137a9c6233e55fe184f0.tar.gz yuzu-ab463712474de5f99eec137a9c6233e55fe184f0.tar.xz yuzu-ab463712474de5f99eec137a9c6233e55fe184f0.zip | |
shader: Initial support for textures and TEX
Diffstat (limited to 'src/shader_recompiler/backend/spirv/emit_spirv_convert.cpp')
| -rw-r--r-- | src/shader_recompiler/backend/spirv/emit_spirv_convert.cpp | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_convert.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_convert.cpp index edcc2a1cc..2aff673aa 100644 --- a/src/shader_recompiler/backend/spirv/emit_spirv_convert.cpp +++ b/src/shader_recompiler/backend/spirv/emit_spirv_convert.cpp | |||
| @@ -102,4 +102,52 @@ Id EmitConvertF64F32(EmitContext& ctx, Id value) { | |||
| 102 | return ctx.OpFConvert(ctx.F64[1], value); | 102 | return ctx.OpFConvert(ctx.F64[1], value); |
| 103 | } | 103 | } |
| 104 | 104 | ||
| 105 | Id EmitConvertF16S32(EmitContext& ctx, Id value) { | ||
| 106 | return ctx.OpConvertSToF(ctx.F16[1], value); | ||
| 107 | } | ||
| 108 | |||
| 109 | Id EmitConvertF16S64(EmitContext& ctx, Id value) { | ||
| 110 | return ctx.OpConvertSToF(ctx.F16[1], value); | ||
| 111 | } | ||
| 112 | |||
| 113 | Id EmitConvertF16U32(EmitContext& ctx, Id value) { | ||
| 114 | return ctx.OpConvertUToF(ctx.F16[1], value); | ||
| 115 | } | ||
| 116 | |||
| 117 | Id EmitConvertF16U64(EmitContext& ctx, Id value) { | ||
| 118 | return ctx.OpConvertUToF(ctx.F16[1], value); | ||
| 119 | } | ||
| 120 | |||
| 121 | Id EmitConvertF32S32(EmitContext& ctx, Id value) { | ||
| 122 | return ctx.OpConvertSToF(ctx.F32[1], value); | ||
| 123 | } | ||
| 124 | |||
| 125 | Id EmitConvertF32S64(EmitContext& ctx, Id value) { | ||
| 126 | return ctx.OpConvertSToF(ctx.F32[1], value); | ||
| 127 | } | ||
| 128 | |||
| 129 | Id EmitConvertF32U32(EmitContext& ctx, Id value) { | ||
| 130 | return ctx.OpConvertUToF(ctx.F32[1], value); | ||
| 131 | } | ||
| 132 | |||
| 133 | Id EmitConvertF32U64(EmitContext& ctx, Id value) { | ||
| 134 | return ctx.OpConvertUToF(ctx.F32[1], value); | ||
| 135 | } | ||
| 136 | |||
| 137 | Id EmitConvertF64S32(EmitContext& ctx, Id value) { | ||
| 138 | return ctx.OpConvertSToF(ctx.F64[1], value); | ||
| 139 | } | ||
| 140 | |||
| 141 | Id EmitConvertF64S64(EmitContext& ctx, Id value) { | ||
| 142 | return ctx.OpConvertSToF(ctx.F64[1], value); | ||
| 143 | } | ||
| 144 | |||
| 145 | Id EmitConvertF64U32(EmitContext& ctx, Id value) { | ||
| 146 | return ctx.OpConvertUToF(ctx.F64[1], value); | ||
| 147 | } | ||
| 148 | |||
| 149 | Id EmitConvertF64U64(EmitContext& ctx, Id value) { | ||
| 150 | return ctx.OpConvertUToF(ctx.F64[1], value); | ||
| 151 | } | ||
| 152 | |||
| 105 | } // namespace Shader::Backend::SPIRV | 153 | } // namespace Shader::Backend::SPIRV |