diff options
| author | 2021-04-13 05:32:21 -0300 | |
|---|---|---|
| committer | 2021-07-22 21:51:27 -0400 | |
| commit | fa75b9b0626c8e118e27207dd1e82e2f415fc0bc (patch) | |
| tree | 29738f645876c19fd561a39b8f9d62799bf92ef9 /src/shader_recompiler/backend/spirv/emit_spirv_atomic.cpp | |
| parent | shader: Fix fixed pipeline point size on geometry shaders (diff) | |
| download | yuzu-fa75b9b0626c8e118e27207dd1e82e2f415fc0bc.tar.gz yuzu-fa75b9b0626c8e118e27207dd1e82e2f415fc0bc.tar.xz yuzu-fa75b9b0626c8e118e27207dd1e82e2f415fc0bc.zip | |
spirv: Rework storage buffers and shader memory
Diffstat (limited to 'src/shader_recompiler/backend/spirv/emit_spirv_atomic.cpp')
| -rw-r--r-- | src/shader_recompiler/backend/spirv/emit_spirv_atomic.cpp | 333 |
1 files changed, 126 insertions, 207 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_atomic.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_atomic.cpp index 03d891419..aab32dc52 100644 --- a/src/shader_recompiler/backend/spirv/emit_spirv_atomic.cpp +++ b/src/shader_recompiler/backend/spirv/emit_spirv_atomic.cpp | |||
| @@ -6,11 +6,12 @@ | |||
| 6 | 6 | ||
| 7 | namespace Shader::Backend::SPIRV { | 7 | namespace Shader::Backend::SPIRV { |
| 8 | namespace { | 8 | namespace { |
| 9 | 9 | Id SharedPointer(EmitContext& ctx, Id offset, u32 index_offset = 0) { | |
| 10 | Id GetSharedPointer(EmitContext& ctx, Id offset, u32 index_offset = 0) { | ||
| 11 | const Id shift_id{ctx.Constant(ctx.U32[1], 2U)}; | 10 | const Id shift_id{ctx.Constant(ctx.U32[1], 2U)}; |
| 12 | const Id shifted_value{ctx.OpShiftRightArithmetic(ctx.U32[1], offset, shift_id)}; | 11 | Id index{ctx.OpShiftRightArithmetic(ctx.U32[1], offset, shift_id)}; |
| 13 | const Id index{ctx.OpIAdd(ctx.U32[1], shifted_value, ctx.Constant(ctx.U32[1], index_offset))}; | 12 | if (index_offset > 0) { |
| 13 | index = ctx.OpIAdd(ctx.U32[1], index, ctx.Constant(ctx.U32[1], index_offset)); | ||
| 14 | } | ||
| 14 | return ctx.profile.support_explicit_workgroup_layout | 15 | return ctx.profile.support_explicit_workgroup_layout |
| 15 | ? ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, ctx.u32_zero_value, index) | 16 | ? ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, ctx.u32_zero_value, index) |
| 16 | : ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, index); | 17 | : ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, index); |
| @@ -30,340 +31,258 @@ Id StorageIndex(EmitContext& ctx, const IR::Value& offset, size_t element_size) | |||
| 30 | return ctx.OpShiftRightLogical(ctx.U32[1], index, shift_id); | 31 | return ctx.OpShiftRightLogical(ctx.U32[1], index, shift_id); |
| 31 | } | 32 | } |
| 32 | 33 | ||
| 33 | Id GetStoragePointer(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 34 | Id StoragePointer(EmitContext& ctx, const StorageTypeDefinition& type_def, |
| 34 | u32 index_offset = 0) { | 35 | Id StorageDefinitions::*member_ptr, const IR::Value& binding, |
| 35 | // TODO: Support reinterpreting bindings, guaranteed to be aligned | 36 | const IR::Value& offset, size_t element_size) { |
| 36 | if (!binding.IsImmediate()) { | 37 | if (!binding.IsImmediate()) { |
| 37 | throw NotImplementedException("Dynamic storage buffer indexing"); | 38 | throw NotImplementedException("Dynamic storage buffer indexing"); |
| 38 | } | 39 | } |
| 39 | const Id ssbo{ctx.ssbos[binding.U32()]}; | 40 | const Id ssbo{ctx.ssbos[binding.U32()].*member_ptr}; |
| 40 | const Id base_index{StorageIndex(ctx, offset, sizeof(u32))}; | 41 | const Id index{StorageIndex(ctx, offset, element_size)}; |
| 41 | const Id index{ctx.OpIAdd(ctx.U32[1], base_index, ctx.Constant(ctx.U32[1], index_offset))}; | 42 | return ctx.OpAccessChain(type_def.element, ssbo, ctx.u32_zero_value, index); |
| 42 | return ctx.OpAccessChain(ctx.storage_u32, ssbo, ctx.u32_zero_value, index); | ||
| 43 | } | 43 | } |
| 44 | 44 | ||
| 45 | std::pair<Id, Id> GetAtomicArgs(EmitContext& ctx) { | 45 | std::pair<Id, Id> AtomicArgs(EmitContext& ctx) { |
| 46 | const Id scope{ctx.Constant(ctx.U32[1], static_cast<u32>(spv::Scope::Device))}; | 46 | const Id scope{ctx.Constant(ctx.U32[1], static_cast<u32>(spv::Scope::Device))}; |
| 47 | const Id semantics{ctx.u32_zero_value}; | 47 | const Id semantics{ctx.u32_zero_value}; |
| 48 | return {scope, semantics}; | 48 | return {scope, semantics}; |
| 49 | } | 49 | } |
| 50 | 50 | ||
| 51 | Id LoadU64(EmitContext& ctx, Id pointer_1, Id pointer_2) { | 51 | Id SharedAtomicU32(EmitContext& ctx, Id offset, Id value, |
| 52 | const Id value_1{ctx.OpLoad(ctx.U32[1], pointer_1)}; | 52 | Id (Sirit::Module::*atomic_func)(Id, Id, Id, Id, Id)) { |
| 53 | const Id value_2{ctx.OpLoad(ctx.U32[1], pointer_2)}; | 53 | const Id pointer{SharedPointer(ctx, offset)}; |
| 54 | const Id original_composite{ctx.OpCompositeConstruct(ctx.U32[2], value_1, value_2)}; | 54 | const auto [scope, semantics]{AtomicArgs(ctx)}; |
| 55 | return ctx.OpBitcast(ctx.U64, original_composite); | 55 | return (ctx.*atomic_func)(ctx.U32[1], pointer, scope, semantics, value); |
| 56 | } | 56 | } |
| 57 | 57 | ||
| 58 | void StoreResult(EmitContext& ctx, Id pointer_1, Id pointer_2, Id result) { | 58 | Id StorageAtomicU32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, Id value, |
| 59 | const Id composite{ctx.OpBitcast(ctx.U32[2], result)}; | 59 | Id (Sirit::Module::*atomic_func)(Id, Id, Id, Id, Id)) { |
| 60 | ctx.OpStore(pointer_1, ctx.OpCompositeExtract(ctx.U32[1], composite, 0)); | 60 | const Id pointer{StoragePointer(ctx, ctx.storage_types.U32, &StorageDefinitions::U32, binding, |
| 61 | ctx.OpStore(pointer_2, ctx.OpCompositeExtract(ctx.U32[1], composite, 1)); | 61 | offset, sizeof(u32))}; |
| 62 | const auto [scope, semantics]{AtomicArgs(ctx)}; | ||
| 63 | return (ctx.*atomic_func)(ctx.U32[1], pointer, scope, semantics, value); | ||
| 64 | } | ||
| 65 | |||
| 66 | Id StorageAtomicU64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, Id value, | ||
| 67 | Id (Sirit::Module::*atomic_func)(Id, Id, Id, Id, Id), | ||
| 68 | Id (Sirit::Module::*non_atomic_func)(Id, Id, Id)) { | ||
| 69 | if (ctx.profile.support_int64_atomics) { | ||
| 70 | const Id pointer{StoragePointer(ctx, ctx.storage_types.U64, &StorageDefinitions::U64, | ||
| 71 | binding, offset, sizeof(u64))}; | ||
| 72 | const auto [scope, semantics]{AtomicArgs(ctx)}; | ||
| 73 | return (ctx.*atomic_func)(ctx.U64, pointer, scope, semantics, value); | ||
| 74 | } | ||
| 75 | // LOG_WARNING(..., "Int64 Atomics not supported, fallback to non-atomic"); | ||
| 76 | const Id pointer{StoragePointer(ctx, ctx.storage_types.U32x2, &StorageDefinitions::U32x2, | ||
| 77 | binding, offset, sizeof(u32[2]))}; | ||
| 78 | const Id original_value{ctx.OpBitcast(ctx.U64, ctx.OpLoad(ctx.U32[2], pointer))}; | ||
| 79 | const Id result{(ctx.*non_atomic_func)(ctx.U64, value, original_value)}; | ||
| 80 | ctx.OpStore(pointer, result); | ||
| 81 | return original_value; | ||
| 62 | } | 82 | } |
| 63 | } // Anonymous namespace | 83 | } // Anonymous namespace |
| 64 | 84 | ||
| 65 | Id EmitSharedAtomicIAdd32(EmitContext& ctx, Id pointer_offset, Id value) { | 85 | Id EmitSharedAtomicIAdd32(EmitContext& ctx, Id offset, Id value) { |
| 66 | const Id pointer{GetSharedPointer(ctx, pointer_offset)}; | 86 | return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicIAdd); |
| 67 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | ||
| 68 | return ctx.OpAtomicIAdd(ctx.U32[1], pointer, scope, semantics, value); | ||
| 69 | } | 87 | } |
| 70 | 88 | ||
| 71 | Id EmitSharedAtomicSMin32(EmitContext& ctx, Id pointer_offset, Id value) { | 89 | Id EmitSharedAtomicSMin32(EmitContext& ctx, Id offset, Id value) { |
| 72 | const Id pointer{GetSharedPointer(ctx, pointer_offset)}; | 90 | return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicSMin); |
| 73 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | ||
| 74 | return ctx.OpAtomicSMin(ctx.U32[1], pointer, scope, semantics, value); | ||
| 75 | } | 91 | } |
| 76 | 92 | ||
| 77 | Id EmitSharedAtomicUMin32(EmitContext& ctx, Id pointer_offset, Id value) { | 93 | Id EmitSharedAtomicUMin32(EmitContext& ctx, Id offset, Id value) { |
| 78 | const Id pointer{GetSharedPointer(ctx, pointer_offset)}; | 94 | return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicUMin); |
| 79 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | ||
| 80 | return ctx.OpAtomicUMin(ctx.U32[1], pointer, scope, semantics, value); | ||
| 81 | } | 95 | } |
| 82 | 96 | ||
| 83 | Id EmitSharedAtomicSMax32(EmitContext& ctx, Id pointer_offset, Id value) { | 97 | Id EmitSharedAtomicSMax32(EmitContext& ctx, Id offset, Id value) { |
| 84 | const Id pointer{GetSharedPointer(ctx, pointer_offset)}; | 98 | return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicSMax); |
| 85 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | ||
| 86 | return ctx.OpAtomicSMax(ctx.U32[1], pointer, scope, semantics, value); | ||
| 87 | } | 99 | } |
| 88 | 100 | ||
| 89 | Id EmitSharedAtomicUMax32(EmitContext& ctx, Id pointer_offset, Id value) { | 101 | Id EmitSharedAtomicUMax32(EmitContext& ctx, Id offset, Id value) { |
| 90 | const Id pointer{GetSharedPointer(ctx, pointer_offset)}; | 102 | return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicUMax); |
| 91 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | ||
| 92 | return ctx.OpAtomicUMax(ctx.U32[1], pointer, scope, semantics, value); | ||
| 93 | } | 103 | } |
| 94 | 104 | ||
| 95 | Id EmitSharedAtomicInc32(EmitContext& ctx, Id pointer_offset, Id value) { | 105 | Id EmitSharedAtomicInc32(EmitContext& ctx, Id offset, Id value) { |
| 96 | const Id shift_id{ctx.Constant(ctx.U32[1], 2U)}; | 106 | const Id shift_id{ctx.Constant(ctx.U32[1], 2U)}; |
| 97 | const Id index{ctx.OpShiftRightArithmetic(ctx.U32[1], pointer_offset, shift_id)}; | 107 | const Id index{ctx.OpShiftRightArithmetic(ctx.U32[1], offset, shift_id)}; |
| 98 | return ctx.OpFunctionCall(ctx.U32[1], ctx.increment_cas_shared, index, value, | 108 | return ctx.OpFunctionCall(ctx.U32[1], ctx.increment_cas_shared, index, value); |
| 99 | ctx.shared_memory_u32); | ||
| 100 | } | 109 | } |
| 101 | 110 | ||
| 102 | Id EmitSharedAtomicDec32(EmitContext& ctx, Id pointer_offset, Id value) { | 111 | Id EmitSharedAtomicDec32(EmitContext& ctx, Id offset, Id value) { |
| 103 | const Id shift_id{ctx.Constant(ctx.U32[1], 2U)}; | 112 | const Id shift_id{ctx.Constant(ctx.U32[1], 2U)}; |
| 104 | const Id index{ctx.OpShiftRightArithmetic(ctx.U32[1], pointer_offset, shift_id)}; | 113 | const Id index{ctx.OpShiftRightArithmetic(ctx.U32[1], offset, shift_id)}; |
| 105 | return ctx.OpFunctionCall(ctx.U32[1], ctx.decrement_cas_shared, index, value, | 114 | return ctx.OpFunctionCall(ctx.U32[1], ctx.decrement_cas_shared, index, value); |
| 106 | ctx.shared_memory_u32); | ||
| 107 | } | 115 | } |
| 108 | 116 | ||
| 109 | Id EmitSharedAtomicAnd32(EmitContext& ctx, Id pointer_offset, Id value) { | 117 | Id EmitSharedAtomicAnd32(EmitContext& ctx, Id offset, Id value) { |
| 110 | const Id pointer{GetSharedPointer(ctx, pointer_offset)}; | 118 | return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicAnd); |
| 111 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | ||
| 112 | return ctx.OpAtomicAnd(ctx.U32[1], pointer, scope, semantics, value); | ||
| 113 | } | 119 | } |
| 114 | 120 | ||
| 115 | Id EmitSharedAtomicOr32(EmitContext& ctx, Id pointer_offset, Id value) { | 121 | Id EmitSharedAtomicOr32(EmitContext& ctx, Id offset, Id value) { |
| 116 | const Id pointer{GetSharedPointer(ctx, pointer_offset)}; | 122 | return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicOr); |
| 117 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | ||
| 118 | return ctx.OpAtomicOr(ctx.U32[1], pointer, scope, semantics, value); | ||
| 119 | } | 123 | } |
| 120 | 124 | ||
| 121 | Id EmitSharedAtomicXor32(EmitContext& ctx, Id pointer_offset, Id value) { | 125 | Id EmitSharedAtomicXor32(EmitContext& ctx, Id offset, Id value) { |
| 122 | const Id pointer{GetSharedPointer(ctx, pointer_offset)}; | 126 | return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicXor); |
| 123 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | ||
| 124 | return ctx.OpAtomicXor(ctx.U32[1], pointer, scope, semantics, value); | ||
| 125 | } | 127 | } |
| 126 | 128 | ||
| 127 | Id EmitSharedAtomicExchange32(EmitContext& ctx, Id pointer_offset, Id value) { | 129 | Id EmitSharedAtomicExchange32(EmitContext& ctx, Id offset, Id value) { |
| 128 | const Id pointer{GetSharedPointer(ctx, pointer_offset)}; | 130 | return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicExchange); |
| 129 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | ||
| 130 | return ctx.OpAtomicExchange(ctx.U32[1], pointer, scope, semantics, value); | ||
| 131 | } | 131 | } |
| 132 | 132 | ||
| 133 | Id EmitSharedAtomicExchange64(EmitContext& ctx, Id pointer_offset, Id value) { | 133 | Id EmitSharedAtomicExchange64(EmitContext& ctx, Id offset, Id value) { |
| 134 | const Id pointer_1{GetSharedPointer(ctx, pointer_offset)}; | 134 | if (ctx.profile.support_int64_atomics && ctx.profile.support_explicit_workgroup_layout) { |
| 135 | if (ctx.profile.support_int64_atomics) { | 135 | const Id shift_id{ctx.Constant(ctx.U32[1], 3U)}; |
| 136 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | 136 | const Id index{ctx.OpShiftRightArithmetic(ctx.U32[1], offset, shift_id)}; |
| 137 | return ctx.OpAtomicExchange(ctx.U64, pointer_1, scope, semantics, value); | 137 | const Id pointer{ |
| 138 | ctx.OpAccessChain(ctx.shared_u64, ctx.shared_memory_u64, ctx.u32_zero_value, index)}; | ||
| 139 | const auto [scope, semantics]{AtomicArgs(ctx)}; | ||
| 140 | return ctx.OpAtomicExchange(ctx.U64, pointer, scope, semantics, value); | ||
| 138 | } | 141 | } |
| 139 | // LOG_WARNING(Render_Vulkan, "Int64 Atomics not supported, fallback to non-atomic"); | 142 | // LOG_WARNING("Int64 Atomics not supported, fallback to non-atomic"); |
| 140 | const Id pointer_2{GetSharedPointer(ctx, pointer_offset, 1)}; | 143 | const Id pointer_1{SharedPointer(ctx, offset, 0)}; |
| 141 | const Id original_value{LoadU64(ctx, pointer_1, pointer_2)}; | 144 | const Id pointer_2{SharedPointer(ctx, offset, 1)}; |
| 142 | StoreResult(ctx, pointer_1, pointer_2, value); | 145 | const Id value_1{ctx.OpLoad(ctx.U32[1], pointer_1)}; |
| 143 | return original_value; | 146 | const Id value_2{ctx.OpLoad(ctx.U32[1], pointer_2)}; |
| 147 | const Id new_vector{ctx.OpBitcast(ctx.U32[2], value)}; | ||
| 148 | ctx.OpStore(pointer_1, ctx.OpCompositeExtract(ctx.U32[1], new_vector, 0U)); | ||
| 149 | ctx.OpStore(pointer_2, ctx.OpCompositeExtract(ctx.U32[1], new_vector, 1U)); | ||
| 150 | return ctx.OpBitcast(ctx.U64, ctx.OpCompositeConstruct(ctx.U32[2], value_1, value_2)); | ||
| 144 | } | 151 | } |
| 145 | 152 | ||
| 146 | Id EmitStorageAtomicIAdd32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 153 | Id EmitStorageAtomicIAdd32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, |
| 147 | Id value) { | 154 | Id value) { |
| 148 | const Id pointer{GetStoragePointer(ctx, binding, offset)}; | 155 | return StorageAtomicU32(ctx, binding, offset, value, &Sirit::Module::OpAtomicIAdd); |
| 149 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | ||
| 150 | return ctx.OpAtomicIAdd(ctx.U32[1], pointer, scope, semantics, value); | ||
| 151 | } | 156 | } |
| 152 | 157 | ||
| 153 | Id EmitStorageAtomicSMin32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 158 | Id EmitStorageAtomicSMin32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, |
| 154 | Id value) { | 159 | Id value) { |
| 155 | const Id pointer{GetStoragePointer(ctx, binding, offset)}; | 160 | return StorageAtomicU32(ctx, binding, offset, value, &Sirit::Module::OpAtomicSMin); |
| 156 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | ||
| 157 | return ctx.OpAtomicSMin(ctx.U32[1], pointer, scope, semantics, value); | ||
| 158 | } | 161 | } |
| 159 | 162 | ||
| 160 | Id EmitStorageAtomicUMin32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 163 | Id EmitStorageAtomicUMin32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, |
| 161 | Id value) { | 164 | Id value) { |
| 162 | const Id pointer{GetStoragePointer(ctx, binding, offset)}; | 165 | return StorageAtomicU32(ctx, binding, offset, value, &Sirit::Module::OpAtomicUMin); |
| 163 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | ||
| 164 | return ctx.OpAtomicUMin(ctx.U32[1], pointer, scope, semantics, value); | ||
| 165 | } | 166 | } |
| 166 | 167 | ||
| 167 | Id EmitStorageAtomicSMax32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 168 | Id EmitStorageAtomicSMax32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, |
| 168 | Id value) { | 169 | Id value) { |
| 169 | const Id pointer{GetStoragePointer(ctx, binding, offset)}; | 170 | return StorageAtomicU32(ctx, binding, offset, value, &Sirit::Module::OpAtomicSMax); |
| 170 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | ||
| 171 | return ctx.OpAtomicSMax(ctx.U32[1], pointer, scope, semantics, value); | ||
| 172 | } | 171 | } |
| 173 | 172 | ||
| 174 | Id EmitStorageAtomicUMax32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 173 | Id EmitStorageAtomicUMax32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, |
| 175 | Id value) { | 174 | Id value) { |
| 176 | const Id pointer{GetStoragePointer(ctx, binding, offset)}; | 175 | return StorageAtomicU32(ctx, binding, offset, value, &Sirit::Module::OpAtomicUMax); |
| 177 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | ||
| 178 | return ctx.OpAtomicUMax(ctx.U32[1], pointer, scope, semantics, value); | ||
| 179 | } | 176 | } |
| 180 | 177 | ||
| 181 | Id EmitStorageAtomicInc32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 178 | Id EmitStorageAtomicInc32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, |
| 182 | Id value) { | 179 | Id value) { |
| 183 | const Id ssbo{ctx.ssbos[binding.U32()]}; | 180 | const Id ssbo{ctx.ssbos[binding.U32()].U32}; |
| 184 | const Id base_index{StorageIndex(ctx, offset, sizeof(u32))}; | 181 | const Id base_index{StorageIndex(ctx, offset, sizeof(u32))}; |
| 185 | return ctx.OpFunctionCall(ctx.U32[1], ctx.increment_cas_ssbo, base_index, value, ssbo); | 182 | return ctx.OpFunctionCall(ctx.U32[1], ctx.increment_cas_ssbo, base_index, value, ssbo); |
| 186 | } | 183 | } |
| 187 | 184 | ||
| 188 | Id EmitStorageAtomicDec32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 185 | Id EmitStorageAtomicDec32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, |
| 189 | Id value) { | 186 | Id value) { |
| 190 | const Id ssbo{ctx.ssbos[binding.U32()]}; | 187 | const Id ssbo{ctx.ssbos[binding.U32()].U32}; |
| 191 | const Id base_index{StorageIndex(ctx, offset, sizeof(u32))}; | 188 | const Id base_index{StorageIndex(ctx, offset, sizeof(u32))}; |
| 192 | return ctx.OpFunctionCall(ctx.U32[1], ctx.decrement_cas_ssbo, base_index, value, ssbo); | 189 | return ctx.OpFunctionCall(ctx.U32[1], ctx.decrement_cas_ssbo, base_index, value, ssbo); |
| 193 | } | 190 | } |
| 194 | 191 | ||
| 195 | Id EmitStorageAtomicAnd32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 192 | Id EmitStorageAtomicAnd32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, |
| 196 | Id value) { | 193 | Id value) { |
| 197 | const Id pointer{GetStoragePointer(ctx, binding, offset)}; | 194 | return StorageAtomicU32(ctx, binding, offset, value, &Sirit::Module::OpAtomicAnd); |
| 198 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | ||
| 199 | return ctx.OpAtomicAnd(ctx.U32[1], pointer, scope, semantics, value); | ||
| 200 | } | 195 | } |
| 201 | 196 | ||
| 202 | Id EmitStorageAtomicOr32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 197 | Id EmitStorageAtomicOr32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, |
| 203 | Id value) { | 198 | Id value) { |
| 204 | const Id pointer{GetStoragePointer(ctx, binding, offset)}; | 199 | return StorageAtomicU32(ctx, binding, offset, value, &Sirit::Module::OpAtomicOr); |
| 205 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | ||
| 206 | return ctx.OpAtomicOr(ctx.U32[1], pointer, scope, semantics, value); | ||
| 207 | } | 200 | } |
| 208 | 201 | ||
| 209 | Id EmitStorageAtomicXor32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 202 | Id EmitStorageAtomicXor32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, |
| 210 | Id value) { | 203 | Id value) { |
| 211 | const Id pointer{GetStoragePointer(ctx, binding, offset)}; | 204 | return StorageAtomicU32(ctx, binding, offset, value, &Sirit::Module::OpAtomicXor); |
| 212 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | ||
| 213 | return ctx.OpAtomicXor(ctx.U32[1], pointer, scope, semantics, value); | ||
| 214 | } | 205 | } |
| 215 | 206 | ||
| 216 | Id EmitStorageAtomicExchange32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 207 | Id EmitStorageAtomicExchange32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, |
| 217 | Id value) { | 208 | Id value) { |
| 218 | const Id pointer{GetStoragePointer(ctx, binding, offset)}; | 209 | return StorageAtomicU32(ctx, binding, offset, value, &Sirit::Module::OpAtomicExchange); |
| 219 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | ||
| 220 | return ctx.OpAtomicExchange(ctx.U32[1], pointer, scope, semantics, value); | ||
| 221 | } | 210 | } |
| 222 | 211 | ||
| 223 | Id EmitStorageAtomicIAdd64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 212 | Id EmitStorageAtomicIAdd64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, |
| 224 | Id value) { | 213 | Id value) { |
| 225 | const Id pointer_1{GetStoragePointer(ctx, binding, offset)}; | 214 | return StorageAtomicU64(ctx, binding, offset, value, &Sirit::Module::OpAtomicIAdd, |
| 226 | if (ctx.profile.support_int64_atomics) { | 215 | &Sirit::Module::OpIAdd); |
| 227 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | ||
| 228 | return ctx.OpAtomicIAdd(ctx.U64, pointer_1, scope, semantics, value); | ||
| 229 | } | ||
| 230 | // LOG_WARNING(Render_Vulkan, "Int64 Atomics not supported, fallback to non-atomic"); | ||
| 231 | const Id pointer_2{GetStoragePointer(ctx, binding, offset, 1)}; | ||
| 232 | const Id original_value{LoadU64(ctx, pointer_1, pointer_2)}; | ||
| 233 | const Id result{ctx.OpIAdd(ctx.U64, value, original_value)}; | ||
| 234 | StoreResult(ctx, pointer_1, pointer_2, result); | ||
| 235 | return original_value; | ||
| 236 | } | 216 | } |
| 237 | 217 | ||
| 238 | Id EmitStorageAtomicSMin64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 218 | Id EmitStorageAtomicSMin64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, |
| 239 | Id value) { | 219 | Id value) { |
| 240 | const Id pointer_1{GetStoragePointer(ctx, binding, offset)}; | 220 | return StorageAtomicU64(ctx, binding, offset, value, &Sirit::Module::OpAtomicSMin, |
| 241 | if (ctx.profile.support_int64_atomics) { | 221 | &Sirit::Module::OpSMin); |
| 242 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | ||
| 243 | return ctx.OpAtomicSMin(ctx.U64, pointer_1, scope, semantics, value); | ||
| 244 | } | ||
| 245 | // LOG_WARNING(Render_Vulkan, "Int64 Atomics not supported, fallback to non-atomic"); | ||
| 246 | const Id pointer_2{GetStoragePointer(ctx, binding, offset, 1)}; | ||
| 247 | const Id original_value{LoadU64(ctx, pointer_1, pointer_2)}; | ||
| 248 | const Id result{ctx.OpSMin(ctx.U64, value, original_value)}; | ||
| 249 | StoreResult(ctx, pointer_1, pointer_2, result); | ||
| 250 | return original_value; | ||
| 251 | } | 222 | } |
| 252 | 223 | ||
| 253 | Id EmitStorageAtomicUMin64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 224 | Id EmitStorageAtomicUMin64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, |
| 254 | Id value) { | 225 | Id value) { |
| 255 | const Id pointer_1{GetStoragePointer(ctx, binding, offset)}; | 226 | return StorageAtomicU64(ctx, binding, offset, value, &Sirit::Module::OpAtomicUMin, |
| 256 | if (ctx.profile.support_int64_atomics) { | 227 | &Sirit::Module::OpUMin); |
| 257 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | ||
| 258 | return ctx.OpAtomicUMin(ctx.U64, pointer_1, scope, semantics, value); | ||
| 259 | } | ||
| 260 | // LOG_WARNING(Render_Vulkan, "Int64 Atomics not supported, fallback to non-atomic"); | ||
| 261 | const Id pointer_2{GetStoragePointer(ctx, binding, offset, 1)}; | ||
| 262 | const Id original_value{LoadU64(ctx, pointer_1, pointer_2)}; | ||
| 263 | const Id result{ctx.OpUMin(ctx.U64, value, original_value)}; | ||
| 264 | StoreResult(ctx, pointer_1, pointer_2, result); | ||
| 265 | return original_value; | ||
| 266 | } | 228 | } |
| 267 | 229 | ||
| 268 | Id EmitStorageAtomicSMax64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 230 | Id EmitStorageAtomicSMax64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, |
| 269 | Id value) { | 231 | Id value) { |
| 270 | const Id pointer_1{GetStoragePointer(ctx, binding, offset)}; | 232 | return StorageAtomicU64(ctx, binding, offset, value, &Sirit::Module::OpAtomicSMax, |
| 271 | if (ctx.profile.support_int64_atomics) { | 233 | &Sirit::Module::OpSMax); |
| 272 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | ||
| 273 | return ctx.OpAtomicSMax(ctx.U64, pointer_1, scope, semantics, value); | ||
| 274 | } | ||
| 275 | // LOG_WARNING(Render_Vulkan, "Int64 Atomics not supported, fallback to non-atomic"); | ||
| 276 | const Id pointer_2{GetStoragePointer(ctx, binding, offset, 1)}; | ||
| 277 | const Id original_value{LoadU64(ctx, pointer_1, pointer_2)}; | ||
| 278 | const Id result{ctx.OpSMax(ctx.U64, value, original_value)}; | ||
| 279 | StoreResult(ctx, pointer_1, pointer_2, result); | ||
| 280 | return original_value; | ||
| 281 | } | 234 | } |
| 282 | 235 | ||
| 283 | Id EmitStorageAtomicUMax64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 236 | Id EmitStorageAtomicUMax64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, |
| 284 | Id value) { | 237 | Id value) { |
| 285 | const Id pointer_1{GetStoragePointer(ctx, binding, offset)}; | 238 | return StorageAtomicU64(ctx, binding, offset, value, &Sirit::Module::OpAtomicUMax, |
| 286 | if (ctx.profile.support_int64_atomics) { | 239 | &Sirit::Module::OpUMax); |
| 287 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | ||
| 288 | return ctx.OpAtomicUMax(ctx.U64, pointer_1, scope, semantics, value); | ||
| 289 | } | ||
| 290 | // LOG_WARNING(Render_Vulkan, "Int64 Atomics not supported, fallback to non-atomic"); | ||
| 291 | const Id pointer_2{GetStoragePointer(ctx, binding, offset, 1)}; | ||
| 292 | const Id original_value{LoadU64(ctx, pointer_1, pointer_2)}; | ||
| 293 | const Id result{ctx.OpUMax(ctx.U64, value, original_value)}; | ||
| 294 | StoreResult(ctx, pointer_1, pointer_2, result); | ||
| 295 | return original_value; | ||
| 296 | } | 240 | } |
| 297 | 241 | ||
| 298 | Id EmitStorageAtomicAnd64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 242 | Id EmitStorageAtomicAnd64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, |
| 299 | Id value) { | 243 | Id value) { |
| 300 | const Id pointer_1{GetStoragePointer(ctx, binding, offset)}; | 244 | return StorageAtomicU64(ctx, binding, offset, value, &Sirit::Module::OpAtomicAnd, |
| 301 | if (ctx.profile.support_int64_atomics) { | 245 | &Sirit::Module::OpBitwiseAnd); |
| 302 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | ||
| 303 | return ctx.OpAtomicAnd(ctx.U64, pointer_1, scope, semantics, value); | ||
| 304 | } | ||
| 305 | // LOG_WARNING(Render_Vulkan, "Int64 Atomics not supported, fallback to non-atomic"); | ||
| 306 | const Id pointer_2{GetStoragePointer(ctx, binding, offset, 1)}; | ||
| 307 | const Id original_value{LoadU64(ctx, pointer_1, pointer_2)}; | ||
| 308 | const Id result{ctx.OpBitwiseAnd(ctx.U64, value, original_value)}; | ||
| 309 | StoreResult(ctx, pointer_1, pointer_2, result); | ||
| 310 | return original_value; | ||
| 311 | } | 246 | } |
| 312 | 247 | ||
| 313 | Id EmitStorageAtomicOr64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 248 | Id EmitStorageAtomicOr64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, |
| 314 | Id value) { | 249 | Id value) { |
| 315 | const Id pointer_1{GetStoragePointer(ctx, binding, offset)}; | 250 | return StorageAtomicU64(ctx, binding, offset, value, &Sirit::Module::OpAtomicOr, |
| 316 | if (ctx.profile.support_int64_atomics) { | 251 | &Sirit::Module::OpBitwiseOr); |
| 317 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | ||
| 318 | return ctx.OpAtomicOr(ctx.U64, pointer_1, scope, semantics, value); | ||
| 319 | } | ||
| 320 | // LOG_WARNING(Render_Vulkan, "Int64 Atomics not supported, fallback to non-atomic"); | ||
| 321 | const Id pointer_2{GetStoragePointer(ctx, binding, offset, 1)}; | ||
| 322 | const Id original_value{LoadU64(ctx, pointer_1, pointer_2)}; | ||
| 323 | const Id result{ctx.OpBitwiseOr(ctx.U64, value, original_value)}; | ||
| 324 | StoreResult(ctx, pointer_1, pointer_2, result); | ||
| 325 | return original_value; | ||
| 326 | } | 252 | } |
| 327 | 253 | ||
| 328 | Id EmitStorageAtomicXor64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 254 | Id EmitStorageAtomicXor64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, |
| 329 | Id value) { | 255 | Id value) { |
| 330 | const Id pointer_1{GetStoragePointer(ctx, binding, offset)}; | 256 | return StorageAtomicU64(ctx, binding, offset, value, &Sirit::Module::OpAtomicXor, |
| 331 | if (ctx.profile.support_int64_atomics) { | 257 | &Sirit::Module::OpBitwiseXor); |
| 332 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | ||
| 333 | return ctx.OpAtomicXor(ctx.U64, pointer_1, scope, semantics, value); | ||
| 334 | } | ||
| 335 | // LOG_WARNING(Render_Vulkan, "Int64 Atomics not supported, fallback to non-atomic"); | ||
| 336 | const Id pointer_2{GetStoragePointer(ctx, binding, offset, 1)}; | ||
| 337 | const Id original_value{LoadU64(ctx, pointer_1, pointer_2)}; | ||
| 338 | const Id result{ctx.OpBitwiseXor(ctx.U64, value, original_value)}; | ||
| 339 | StoreResult(ctx, pointer_1, pointer_2, result); | ||
| 340 | return original_value; | ||
| 341 | } | 258 | } |
| 342 | 259 | ||
| 343 | Id EmitStorageAtomicExchange64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 260 | Id EmitStorageAtomicExchange64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, |
| 344 | Id value) { | 261 | Id value) { |
| 345 | const Id pointer_1{GetStoragePointer(ctx, binding, offset)}; | ||
| 346 | if (ctx.profile.support_int64_atomics) { | 262 | if (ctx.profile.support_int64_atomics) { |
| 347 | const auto [scope, semantics]{GetAtomicArgs(ctx)}; | 263 | const Id pointer{StoragePointer(ctx, ctx.storage_types.U64, &StorageDefinitions::U64, |
| 348 | return ctx.OpAtomicExchange(ctx.U64, pointer_1, scope, semantics, value); | 264 | binding, offset, sizeof(u64))}; |
| 265 | const auto [scope, semantics]{AtomicArgs(ctx)}; | ||
| 266 | return ctx.OpAtomicExchange(ctx.U64, pointer, scope, semantics, value); | ||
| 349 | } | 267 | } |
| 350 | // LOG_WARNING(Render_Vulkan, "Int64 Atomics not supported, fallback to non-atomic"); | 268 | // LOG_WARNING(..., "Int64 Atomics not supported, fallback to non-atomic"); |
| 351 | const Id pointer_2{GetStoragePointer(ctx, binding, offset, 1)}; | 269 | const Id pointer{StoragePointer(ctx, ctx.storage_types.U32x2, &StorageDefinitions::U32x2, |
| 352 | const Id original_value{LoadU64(ctx, pointer_1, pointer_2)}; | 270 | binding, offset, sizeof(u32[2]))}; |
| 353 | StoreResult(ctx, pointer_1, pointer_2, value); | 271 | const Id original{ctx.OpBitcast(ctx.U64, ctx.OpLoad(ctx.U32[2], pointer))}; |
| 354 | return original_value; | 272 | ctx.OpStore(pointer, value); |
| 273 | return original; | ||
| 355 | } | 274 | } |
| 356 | 275 | ||
| 357 | Id EmitStorageAtomicAddF32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 276 | Id EmitStorageAtomicAddF32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, |
| 358 | Id value) { | 277 | Id value) { |
| 359 | const Id ssbo{ctx.ssbos[binding.U32()]}; | 278 | const Id ssbo{ctx.ssbos[binding.U32()].U32}; |
| 360 | const Id base_index{StorageIndex(ctx, offset, sizeof(u32))}; | 279 | const Id base_index{StorageIndex(ctx, offset, sizeof(u32))}; |
| 361 | return ctx.OpFunctionCall(ctx.F32[1], ctx.f32_add_cas, base_index, value, ssbo); | 280 | return ctx.OpFunctionCall(ctx.F32[1], ctx.f32_add_cas, base_index, value, ssbo); |
| 362 | } | 281 | } |
| 363 | 282 | ||
| 364 | Id EmitStorageAtomicAddF16x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 283 | Id EmitStorageAtomicAddF16x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, |
| 365 | Id value) { | 284 | Id value) { |
| 366 | const Id ssbo{ctx.ssbos[binding.U32()]}; | 285 | const Id ssbo{ctx.ssbos[binding.U32()].U32}; |
| 367 | const Id base_index{StorageIndex(ctx, offset, sizeof(u32))}; | 286 | const Id base_index{StorageIndex(ctx, offset, sizeof(u32))}; |
| 368 | const Id result{ctx.OpFunctionCall(ctx.F16[2], ctx.f16x2_add_cas, base_index, value, ssbo)}; | 287 | const Id result{ctx.OpFunctionCall(ctx.F16[2], ctx.f16x2_add_cas, base_index, value, ssbo)}; |
| 369 | return ctx.OpBitcast(ctx.U32[1], result); | 288 | return ctx.OpBitcast(ctx.U32[1], result); |
| @@ -371,7 +290,7 @@ Id EmitStorageAtomicAddF16x2(EmitContext& ctx, const IR::Value& binding, const I | |||
| 371 | 290 | ||
| 372 | Id EmitStorageAtomicAddF32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 291 | Id EmitStorageAtomicAddF32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, |
| 373 | Id value) { | 292 | Id value) { |
| 374 | const Id ssbo{ctx.ssbos[binding.U32()]}; | 293 | const Id ssbo{ctx.ssbos[binding.U32()].U32}; |
| 375 | const Id base_index{StorageIndex(ctx, offset, sizeof(u32))}; | 294 | const Id base_index{StorageIndex(ctx, offset, sizeof(u32))}; |
| 376 | const Id result{ctx.OpFunctionCall(ctx.F32[2], ctx.f32x2_add_cas, base_index, value, ssbo)}; | 295 | const Id result{ctx.OpFunctionCall(ctx.F32[2], ctx.f32x2_add_cas, base_index, value, ssbo)}; |
| 377 | return ctx.OpPackHalf2x16(ctx.U32[1], result); | 296 | return ctx.OpPackHalf2x16(ctx.U32[1], result); |
| @@ -379,7 +298,7 @@ Id EmitStorageAtomicAddF32x2(EmitContext& ctx, const IR::Value& binding, const I | |||
| 379 | 298 | ||
| 380 | Id EmitStorageAtomicMinF16x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 299 | Id EmitStorageAtomicMinF16x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, |
| 381 | Id value) { | 300 | Id value) { |
| 382 | const Id ssbo{ctx.ssbos[binding.U32()]}; | 301 | const Id ssbo{ctx.ssbos[binding.U32()].U32}; |
| 383 | const Id base_index{StorageIndex(ctx, offset, sizeof(u32))}; | 302 | const Id base_index{StorageIndex(ctx, offset, sizeof(u32))}; |
| 384 | const Id result{ctx.OpFunctionCall(ctx.F16[2], ctx.f16x2_min_cas, base_index, value, ssbo)}; | 303 | const Id result{ctx.OpFunctionCall(ctx.F16[2], ctx.f16x2_min_cas, base_index, value, ssbo)}; |
| 385 | return ctx.OpBitcast(ctx.U32[1], result); | 304 | return ctx.OpBitcast(ctx.U32[1], result); |
| @@ -387,7 +306,7 @@ Id EmitStorageAtomicMinF16x2(EmitContext& ctx, const IR::Value& binding, const I | |||
| 387 | 306 | ||
| 388 | Id EmitStorageAtomicMinF32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 307 | Id EmitStorageAtomicMinF32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, |
| 389 | Id value) { | 308 | Id value) { |
| 390 | const Id ssbo{ctx.ssbos[binding.U32()]}; | 309 | const Id ssbo{ctx.ssbos[binding.U32()].U32}; |
| 391 | const Id base_index{StorageIndex(ctx, offset, sizeof(u32))}; | 310 | const Id base_index{StorageIndex(ctx, offset, sizeof(u32))}; |
| 392 | const Id result{ctx.OpFunctionCall(ctx.F32[2], ctx.f32x2_min_cas, base_index, value, ssbo)}; | 311 | const Id result{ctx.OpFunctionCall(ctx.F32[2], ctx.f32x2_min_cas, base_index, value, ssbo)}; |
| 393 | return ctx.OpPackHalf2x16(ctx.U32[1], result); | 312 | return ctx.OpPackHalf2x16(ctx.U32[1], result); |
| @@ -395,7 +314,7 @@ Id EmitStorageAtomicMinF32x2(EmitContext& ctx, const IR::Value& binding, const I | |||
| 395 | 314 | ||
| 396 | Id EmitStorageAtomicMaxF16x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 315 | Id EmitStorageAtomicMaxF16x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, |
| 397 | Id value) { | 316 | Id value) { |
| 398 | const Id ssbo{ctx.ssbos[binding.U32()]}; | 317 | const Id ssbo{ctx.ssbos[binding.U32()].U32}; |
| 399 | const Id base_index{StorageIndex(ctx, offset, sizeof(u32))}; | 318 | const Id base_index{StorageIndex(ctx, offset, sizeof(u32))}; |
| 400 | const Id result{ctx.OpFunctionCall(ctx.F16[2], ctx.f16x2_max_cas, base_index, value, ssbo)}; | 319 | const Id result{ctx.OpFunctionCall(ctx.F16[2], ctx.f16x2_max_cas, base_index, value, ssbo)}; |
| 401 | return ctx.OpBitcast(ctx.U32[1], result); | 320 | return ctx.OpBitcast(ctx.U32[1], result); |
| @@ -403,7 +322,7 @@ Id EmitStorageAtomicMaxF16x2(EmitContext& ctx, const IR::Value& binding, const I | |||
| 403 | 322 | ||
| 404 | Id EmitStorageAtomicMaxF32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, | 323 | Id EmitStorageAtomicMaxF32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, |
| 405 | Id value) { | 324 | Id value) { |
| 406 | const Id ssbo{ctx.ssbos[binding.U32()]}; | 325 | const Id ssbo{ctx.ssbos[binding.U32()].U32}; |
| 407 | const Id base_index{StorageIndex(ctx, offset, sizeof(u32))}; | 326 | const Id base_index{StorageIndex(ctx, offset, sizeof(u32))}; |
| 408 | const Id result{ctx.OpFunctionCall(ctx.F32[2], ctx.f32x2_max_cas, base_index, value, ssbo)}; | 327 | const Id result{ctx.OpFunctionCall(ctx.F32[2], ctx.f32x2_max_cas, base_index, value, ssbo)}; |
| 409 | return ctx.OpPackHalf2x16(ctx.U32[1], result); | 328 | return ctx.OpPackHalf2x16(ctx.U32[1], result); |