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| author |  ReinUsesLisp | 2021-02-22 02:45:50 -0300 |
|---|---|---|
| committer |  ameerj | 2021-07-22 21:51:22 -0400 |
| commit | 18a766b3622baa40596490dbd4912f94e9980a76 (patch) | |
| tree | de34dbbbd81f6f980308b165a812445b224bd8fb /src/shader_recompiler/backend/spirv/emit_spirv.h | |
| parent | spirv: Fixes and Intel specific workarounds (diff) | |
| download | yuzu-18a766b3622baa40596490dbd4912f94e9980a76.tar.gz yuzu-18a766b3622baa40596490dbd4912f94e9980a76.tar.xz yuzu-18a766b3622baa40596490dbd4912f94e9980a76.zip | |
shader: Fix MOV(reg), add SHL variants and emit neg and abs instructions
Diffstat (limited to 'src/shader_recompiler/backend/spirv/emit_spirv.h')
| -rw-r--r-- | src/shader_recompiler/backend/spirv/emit_spirv.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv.h b/src/shader_recompiler/backend/spirv/emit_spirv.h index cec80c13e..1b9be445e 100644 --- a/src/shader_recompiler/backend/spirv/emit_spirv.h +++ b/src/shader_recompiler/backend/spirv/emit_spirv.h | |||
| @@ -181,8 +181,8 @@ void EmitIAdd64(EmitContext& ctx); | |||
| 181 | Id EmitISub32(EmitContext& ctx, Id a, Id b); | 181 | Id EmitISub32(EmitContext& ctx, Id a, Id b); |
| 182 | void EmitISub64(EmitContext& ctx); | 182 | void EmitISub64(EmitContext& ctx); |
| 183 | Id EmitIMul32(EmitContext& ctx, Id a, Id b); | 183 | Id EmitIMul32(EmitContext& ctx, Id a, Id b); |
| 184 | void EmitINeg32(EmitContext& ctx); | 184 | Id EmitINeg32(EmitContext& ctx, Id value); |
| 185 | void EmitIAbs32(EmitContext& ctx); | 185 | Id EmitIAbs32(EmitContext& ctx, Id value); |
| 186 | Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift); | 186 | Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift); |
| 187 | void EmitShiftRightLogical32(EmitContext& ctx); | 187 | void EmitShiftRightLogical32(EmitContext& ctx); |
| 188 | void EmitShiftRightArithmetic32(EmitContext& ctx); | 188 | void EmitShiftRightArithmetic32(EmitContext& ctx); |