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authorGravatar ReinUsesLisp2021-02-11 16:39:06 -0300
committerGravatar ameerj2021-07-22 21:51:22 -0400
commit9170200a11715d131645d1ffb92e86e6ef0d7e88 (patch)
tree6c6f84c38a9b59d023ecb09c0737ea56da166b64 /src/shader_recompiler/backend/spirv/emit_spirv.cpp
parentspirv: Initial SPIR-V support (diff)
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shader: Initial implementation of an AST
Diffstat (limited to 'src/shader_recompiler/backend/spirv/emit_spirv.cpp')
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv.cpp45
1 files changed, 43 insertions, 2 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv.cpp b/src/shader_recompiler/backend/spirv/emit_spirv.cpp
index 7c4269fad..5022b5159 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv.cpp
@@ -105,8 +105,26 @@ void EmitSPIRV::EmitInst(EmitContext& ctx, IR::Inst* inst) {
105 throw LogicError("Invalid opcode {}", inst->Opcode()); 105 throw LogicError("Invalid opcode {}", inst->Opcode());
106} 106}
107 107
108void EmitSPIRV::EmitPhi(EmitContext&) { 108static Id TypeId(const EmitContext& ctx, IR::Type type) {
109 throw NotImplementedException("SPIR-V Instruction"); 109 switch (type) {
110 case IR::Type::U1:
111 return ctx.u1;
112 default:
113 throw NotImplementedException("Phi node type {}", type);
114 }
115}
116
117Id EmitSPIRV::EmitPhi(EmitContext& ctx, IR::Inst* inst) {
118 const size_t num_args{inst->NumArgs()};
119 boost::container::small_vector<Id, 64> operands;
120 operands.reserve(num_args * 2);
121 for (size_t index = 0; index < num_args; ++index) {
122 IR::Block* const phi_block{inst->PhiBlock(index)};
123 operands.push_back(ctx.Def(inst->Arg(index)));
124 operands.push_back(ctx.BlockLabel(phi_block));
125 }
126 const Id result_type{TypeId(ctx, inst->Arg(0).Type())};
127 return ctx.OpPhi(result_type, std::span(operands.data(), operands.size()));
110} 128}
111 129
112void EmitSPIRV::EmitVoid(EmitContext&) {} 130void EmitSPIRV::EmitVoid(EmitContext&) {}
@@ -115,6 +133,29 @@ void EmitSPIRV::EmitIdentity(EmitContext&) {
115 throw NotImplementedException("SPIR-V Instruction"); 133 throw NotImplementedException("SPIR-V Instruction");
116} 134}
117 135
136// FIXME: Move to its own file
137void EmitSPIRV::EmitBranch(EmitContext& ctx, IR::Inst* inst) {
138 ctx.OpBranch(ctx.BlockLabel(inst->Arg(0).Label()));
139}
140
141void EmitSPIRV::EmitBranchConditional(EmitContext& ctx, IR::Inst* inst) {
142 ctx.OpBranchConditional(ctx.Def(inst->Arg(0)), ctx.BlockLabel(inst->Arg(1).Label()),
143 ctx.BlockLabel(inst->Arg(2).Label()));
144}
145
146void EmitSPIRV::EmitLoopMerge(EmitContext& ctx, IR::Inst* inst) {
147 ctx.OpLoopMerge(ctx.BlockLabel(inst->Arg(0).Label()), ctx.BlockLabel(inst->Arg(1).Label()),
148 spv::LoopControlMask::MaskNone);
149}
150
151void EmitSPIRV::EmitSelectionMerge(EmitContext& ctx, IR::Inst* inst) {
152 ctx.OpSelectionMerge(ctx.BlockLabel(inst->Arg(0).Label()), spv::SelectionControlMask::MaskNone);
153}
154
155void EmitSPIRV::EmitReturn(EmitContext& ctx) {
156 ctx.OpReturn();
157}
158
118void EmitSPIRV::EmitGetZeroFromOp(EmitContext&) { 159void EmitSPIRV::EmitGetZeroFromOp(EmitContext&) {
119 throw LogicError("Unreachable instruction"); 160 throw LogicError("Unreachable instruction");
120} 161}