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| author | 2021-05-23 04:14:35 -0300 | |
|---|---|---|
| committer | 2021-07-22 21:51:29 -0400 | |
| commit | d2e811db2edd3829b344e96ad56ae979bccd28d2 (patch) | |
| tree | 14160c4fb0bd1dac9fb604f3a6b4767e3292a0e7 /src/shader_recompiler/backend/spirv/emit_context.h | |
| parent | spirv: Add int8 and int16 capabilities only when supported (diff) | |
| download | yuzu-d2e811db2edd3829b344e96ad56ae979bccd28d2.tar.gz yuzu-d2e811db2edd3829b344e96ad56ae979bccd28d2.tar.xz yuzu-d2e811db2edd3829b344e96ad56ae979bccd28d2.zip | |
spirv: Workaround image unsigned offset bug
Workaround bug on Nvidia's OpenGL SPIR-V compiler when using unsigned
texture offsets.
Diffstat (limited to 'src/shader_recompiler/backend/spirv/emit_context.h')
| -rw-r--r-- | src/shader_recompiler/backend/spirv/emit_context.h | 25 |
1 files changed, 21 insertions, 4 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_context.h b/src/shader_recompiler/backend/spirv/emit_context.h index baf12c217..823ed8525 100644 --- a/src/shader_recompiler/backend/spirv/emit_context.h +++ b/src/shader_recompiler/backend/spirv/emit_context.h | |||
| @@ -122,10 +122,6 @@ public: | |||
| 122 | return Constant(U32[1], value); | 122 | return Constant(U32[1], value); |
| 123 | } | 123 | } |
| 124 | 124 | ||
| 125 | Id Const(f32 value) { | ||
| 126 | return Constant(F32[1], value); | ||
| 127 | } | ||
| 128 | |||
| 129 | Id Const(u32 element_1, u32 element_2) { | 125 | Id Const(u32 element_1, u32 element_2) { |
| 130 | return ConstantComposite(U32[2], Const(element_1), Const(element_2)); | 126 | return ConstantComposite(U32[2], Const(element_1), Const(element_2)); |
| 131 | } | 127 | } |
| @@ -139,6 +135,27 @@ public: | |||
| 139 | Const(element_4)); | 135 | Const(element_4)); |
| 140 | } | 136 | } |
| 141 | 137 | ||
| 138 | Id SConst(s32 value) { | ||
| 139 | return Constant(S32[1], value); | ||
| 140 | } | ||
| 141 | |||
| 142 | Id SConst(s32 element_1, s32 element_2) { | ||
| 143 | return ConstantComposite(S32[2], SConst(element_1), SConst(element_2)); | ||
| 144 | } | ||
| 145 | |||
| 146 | Id SConst(s32 element_1, s32 element_2, s32 element_3) { | ||
| 147 | return ConstantComposite(S32[3], SConst(element_1), SConst(element_2), SConst(element_3)); | ||
| 148 | } | ||
| 149 | |||
| 150 | Id SConst(s32 element_1, s32 element_2, s32 element_3, s32 element_4) { | ||
| 151 | return ConstantComposite(S32[4], SConst(element_1), SConst(element_2), SConst(element_3), | ||
| 152 | SConst(element_4)); | ||
| 153 | } | ||
| 154 | |||
| 155 | Id Const(f32 value) { | ||
| 156 | return Constant(F32[1], value); | ||
| 157 | } | ||
| 158 | |||
| 142 | const Profile& profile; | 159 | const Profile& profile; |
| 143 | Stage stage{}; | 160 | Stage stage{}; |
| 144 | 161 | ||