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| author | 2021-05-24 19:33:11 -0400 | |
|---|---|---|
| committer | 2021-07-22 21:51:36 -0400 | |
| commit | e99d01ff5308bb239aa2007ba4363d3a77f4d202 (patch) | |
| tree | d01d0c54c42b15a140fa51f409d187ebe44016eb /src/shader_recompiler/backend/glsl/reg_alloc.h | |
| parent | glsl: Wip storage atomic ops (diff) | |
| download | yuzu-e99d01ff5308bb239aa2007ba4363d3a77f4d202.tar.gz yuzu-e99d01ff5308bb239aa2007ba4363d3a77f4d202.tar.xz yuzu-e99d01ff5308bb239aa2007ba4363d3a77f4d202.zip | |
glsl: implement phi nodes
Diffstat (limited to 'src/shader_recompiler/backend/glsl/reg_alloc.h')
| -rw-r--r-- | src/shader_recompiler/backend/glsl/reg_alloc.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/shader_recompiler/backend/glsl/reg_alloc.h b/src/shader_recompiler/backend/glsl/reg_alloc.h index 7891c30e0..581954e44 100644 --- a/src/shader_recompiler/backend/glsl/reg_alloc.h +++ b/src/shader_recompiler/backend/glsl/reg_alloc.h | |||
| @@ -12,6 +12,7 @@ | |||
| 12 | namespace Shader::IR { | 12 | namespace Shader::IR { |
| 13 | class Inst; | 13 | class Inst; |
| 14 | class Value; | 14 | class Value; |
| 15 | enum class Type; | ||
| 15 | } // namespace Shader::IR | 16 | } // namespace Shader::IR |
| 16 | 17 | ||
| 17 | namespace Shader::Backend::GLSL { | 18 | namespace Shader::Backend::GLSL { |
| @@ -50,6 +51,7 @@ class RegAlloc { | |||
| 50 | public: | 51 | public: |
| 51 | std::string Define(IR::Inst& inst); | 52 | std::string Define(IR::Inst& inst); |
| 52 | std::string Define(IR::Inst& inst, Type type); | 53 | std::string Define(IR::Inst& inst, Type type); |
| 54 | std::string Define(IR::Inst& inst, IR::Type type); | ||
| 53 | 55 | ||
| 54 | std::string Consume(const IR::Value& value); | 56 | std::string Consume(const IR::Value& value); |
| 55 | 57 | ||