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| author | 2021-05-30 17:27:00 -0400 | |
|---|---|---|
| committer | 2021-07-22 21:51:37 -0400 | |
| commit | 1269a0cf8b3844c1a9bb06c843a7698b0a9643d5 (patch) | |
| tree | a0716589fa3952bdeb0f1d19b4bb455d9cdd86e5 /src/shader_recompiler/backend/glsl/reg_alloc.h | |
| parent | glsl: Fix ATOM and implement ATOMS (diff) | |
| download | yuzu-1269a0cf8b3844c1a9bb06c843a7698b0a9643d5.tar.gz yuzu-1269a0cf8b3844c1a9bb06c843a7698b0a9643d5.tar.xz yuzu-1269a0cf8b3844c1a9bb06c843a7698b0a9643d5.zip | |
glsl: Rework variable allocator to allow for variable reuse
Diffstat (limited to 'src/shader_recompiler/backend/glsl/reg_alloc.h')
| -rw-r--r-- | src/shader_recompiler/backend/glsl/reg_alloc.h | 84 |
1 files changed, 0 insertions, 84 deletions
diff --git a/src/shader_recompiler/backend/glsl/reg_alloc.h b/src/shader_recompiler/backend/glsl/reg_alloc.h deleted file mode 100644 index 6c293f9d1..000000000 --- a/src/shader_recompiler/backend/glsl/reg_alloc.h +++ /dev/null | |||
| @@ -1,84 +0,0 @@ | |||
| 1 | // Copyright 2021 yuzu Emulator Project | ||
| 2 | // Licensed under GPLv2 or any later version | ||
| 3 | // Refer to the license.txt file included. | ||
| 4 | |||
| 5 | #pragma once | ||
| 6 | |||
| 7 | #include <bitset> | ||
| 8 | #include <vector> | ||
| 9 | |||
| 10 | #include "common/bit_field.h" | ||
| 11 | #include "common/common_types.h" | ||
| 12 | |||
| 13 | namespace Shader::IR { | ||
| 14 | class Inst; | ||
| 15 | class Value; | ||
| 16 | enum class Type; | ||
| 17 | } // namespace Shader::IR | ||
| 18 | |||
| 19 | namespace Shader::Backend::GLSL { | ||
| 20 | enum class Type : u32 { | ||
| 21 | U1, | ||
| 22 | F16x2, | ||
| 23 | S32, | ||
| 24 | U32, | ||
| 25 | F32, | ||
| 26 | S64, | ||
| 27 | U64, | ||
| 28 | F64, | ||
| 29 | U32x2, | ||
| 30 | F32x2, | ||
| 31 | U32x3, | ||
| 32 | F32x3, | ||
| 33 | U32x4, | ||
| 34 | F32x4, | ||
| 35 | Void, | ||
| 36 | }; | ||
| 37 | |||
| 38 | struct Id { | ||
| 39 | union { | ||
| 40 | u32 raw; | ||
| 41 | BitField<0, 1, u32> is_valid; | ||
| 42 | BitField<1, 1, u32> is_long; | ||
| 43 | BitField<2, 1, u32> is_spill; | ||
| 44 | BitField<3, 1, u32> is_condition_code; | ||
| 45 | BitField<4, 1, u32> is_null; | ||
| 46 | BitField<5, 27, u32> index; | ||
| 47 | }; | ||
| 48 | |||
| 49 | bool operator==(Id rhs) const noexcept { | ||
| 50 | return raw == rhs.raw; | ||
| 51 | } | ||
| 52 | bool operator!=(Id rhs) const noexcept { | ||
| 53 | return !operator==(rhs); | ||
| 54 | } | ||
| 55 | }; | ||
| 56 | static_assert(sizeof(Id) == sizeof(u32)); | ||
| 57 | |||
| 58 | class RegAlloc { | ||
| 59 | public: | ||
| 60 | std::string Define(IR::Inst& inst); | ||
| 61 | std::string Define(IR::Inst& inst, Type type); | ||
| 62 | std::string Define(IR::Inst& inst, IR::Type type); | ||
| 63 | |||
| 64 | std::string Consume(const IR::Value& value); | ||
| 65 | std::string Consume(IR::Inst& inst); | ||
| 66 | |||
| 67 | std::string GetGlslType(Type type); | ||
| 68 | std::string GetGlslType(IR::Type type); | ||
| 69 | |||
| 70 | size_t num_used_registers{}; | ||
| 71 | std::vector<std::string> reg_types; | ||
| 72 | |||
| 73 | private: | ||
| 74 | static constexpr size_t NUM_REGS = 4096; | ||
| 75 | |||
| 76 | Type RegType(IR::Type type); | ||
| 77 | Id Alloc(); | ||
| 78 | void Free(Id id); | ||
| 79 | |||
| 80 | std::bitset<NUM_REGS> register_use{}; | ||
| 81 | std::bitset<NUM_REGS> register_defined{}; | ||
| 82 | }; | ||
| 83 | |||
| 84 | } // namespace Shader::Backend::GLSL | ||