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| author | 2021-05-26 21:18:17 -0400 | |
|---|---|---|
| committer | 2021-07-22 21:51:36 -0400 | |
| commit | d171083d53e106c8c5131522fdc81d51360c562d (patch) | |
| tree | 282cbd1306616e969166e9ddc926bc51c1c15803 /src/shader_recompiler/backend/glsl/reg_alloc.cpp | |
| parent | glsl: Implement some attribute getters and setters (diff) | |
| download | yuzu-d171083d53e106c8c5131522fdc81d51360c562d.tar.gz yuzu-d171083d53e106c8c5131522fdc81d51360c562d.tar.xz yuzu-d171083d53e106c8c5131522fdc81d51360c562d.zip | |
glsl: textures wip
Diffstat (limited to 'src/shader_recompiler/backend/glsl/reg_alloc.cpp')
| -rw-r--r-- | src/shader_recompiler/backend/glsl/reg_alloc.cpp | 72 |
1 files changed, 27 insertions, 45 deletions
diff --git a/src/shader_recompiler/backend/glsl/reg_alloc.cpp b/src/shader_recompiler/backend/glsl/reg_alloc.cpp index a080d5341..06f1965b5 100644 --- a/src/shader_recompiler/backend/glsl/reg_alloc.cpp +++ b/src/shader_recompiler/backend/glsl/reg_alloc.cpp | |||
| @@ -71,26 +71,17 @@ std::string RegAlloc::Define(IR::Inst& inst) { | |||
| 71 | 71 | ||
| 72 | std::string RegAlloc::Define(IR::Inst& inst, Type type) { | 72 | std::string RegAlloc::Define(IR::Inst& inst, Type type) { |
| 73 | const Id id{Alloc()}; | 73 | const Id id{Alloc()}; |
| 74 | const auto type_str{GetType(type, id.index)}; | 74 | std::string type_str = ""; |
| 75 | if (!register_defined[id.index]) { | ||
| 76 | register_defined[id.index] = true; | ||
| 77 | type_str = GetGlslType(type); | ||
| 78 | } | ||
| 75 | inst.SetDefinition<Id>(id); | 79 | inst.SetDefinition<Id>(id); |
| 76 | return type_str + Representation(id); | 80 | return type_str + Representation(id); |
| 77 | } | 81 | } |
| 78 | 82 | ||
| 79 | std::string RegAlloc::Define(IR::Inst& inst, IR::Type type) { | 83 | std::string RegAlloc::Define(IR::Inst& inst, IR::Type type) { |
| 80 | switch (type) { | 84 | return Define(inst, RegType(type)); |
| 81 | case IR::Type::U1: | ||
| 82 | return Define(inst, Type::U1); | ||
| 83 | case IR::Type::U32: | ||
| 84 | return Define(inst, Type::U32); | ||
| 85 | case IR::Type::F32: | ||
| 86 | return Define(inst, Type::F32); | ||
| 87 | case IR::Type::U64: | ||
| 88 | return Define(inst, Type::U64); | ||
| 89 | case IR::Type::F64: | ||
| 90 | return Define(inst, Type::F64); | ||
| 91 | default: | ||
| 92 | throw NotImplementedException("IR type {}", type); | ||
| 93 | } | ||
| 94 | } | 85 | } |
| 95 | 86 | ||
| 96 | std::string RegAlloc::Consume(const IR::Value& value) { | 87 | std::string RegAlloc::Consume(const IR::Value& value) { |
| @@ -107,11 +98,24 @@ std::string RegAlloc::Consume(IR::Inst& inst) { | |||
| 107 | return Representation(inst.Definition<Id>()); | 98 | return Representation(inst.Definition<Id>()); |
| 108 | } | 99 | } |
| 109 | 100 | ||
| 110 | std::string RegAlloc::GetType(Type type, u32 index) { | 101 | Type RegAlloc::RegType(IR::Type type) { |
| 111 | if (register_defined[index]) { | 102 | switch (type) { |
| 112 | return ""; | 103 | case IR::Type::U1: |
| 104 | return Type::U1; | ||
| 105 | case IR::Type::U32: | ||
| 106 | return Type::U32; | ||
| 107 | case IR::Type::F32: | ||
| 108 | return Type::F32; | ||
| 109 | case IR::Type::U64: | ||
| 110 | return Type::U64; | ||
| 111 | case IR::Type::F64: | ||
| 112 | return Type::F64; | ||
| 113 | default: | ||
| 114 | throw NotImplementedException("IR type {}", type); | ||
| 113 | } | 115 | } |
| 114 | register_defined[index] = true; | 116 | } |
| 117 | |||
| 118 | std::string RegAlloc::GetGlslType(Type type) { | ||
| 115 | switch (type) { | 119 | switch (type) { |
| 116 | case Type::U1: | 120 | case Type::U1: |
| 117 | return "bool "; | 121 | return "bool "; |
| @@ -144,6 +148,10 @@ std::string RegAlloc::GetType(Type type, u32 index) { | |||
| 144 | } | 148 | } |
| 145 | } | 149 | } |
| 146 | 150 | ||
| 151 | std::string RegAlloc::GetGlslType(IR::Type type) { | ||
| 152 | return GetGlslType(RegType(type)); | ||
| 153 | } | ||
| 154 | |||
| 147 | Id RegAlloc::Alloc() { | 155 | Id RegAlloc::Alloc() { |
| 148 | if (num_used_registers < NUM_REGS) { | 156 | if (num_used_registers < NUM_REGS) { |
| 149 | for (size_t reg = 0; reg < NUM_REGS; ++reg) { | 157 | for (size_t reg = 0; reg < NUM_REGS; ++reg) { |
| @@ -170,30 +178,4 @@ void RegAlloc::Free(Id id) { | |||
| 170 | register_use[id.index] = false; | 178 | register_use[id.index] = false; |
| 171 | } | 179 | } |
| 172 | 180 | ||
| 173 | /*static*/ bool RegAlloc::IsAliased(const IR::Inst& inst) { | ||
| 174 | switch (inst.GetOpcode()) { | ||
| 175 | case IR::Opcode::Identity: | ||
| 176 | case IR::Opcode::BitCastU16F16: | ||
| 177 | case IR::Opcode::BitCastU32F32: | ||
| 178 | case IR::Opcode::BitCastU64F64: | ||
| 179 | case IR::Opcode::BitCastF16U16: | ||
| 180 | case IR::Opcode::BitCastF32U32: | ||
| 181 | case IR::Opcode::BitCastF64U64: | ||
| 182 | return true; | ||
| 183 | default: | ||
| 184 | return false; | ||
| 185 | } | ||
| 186 | } | ||
| 187 | |||
| 188 | /*static*/ IR::Inst& RegAlloc::AliasInst(IR::Inst& inst) { | ||
| 189 | IR::Inst* it{&inst}; | ||
| 190 | while (IsAliased(*it)) { | ||
| 191 | const IR::Value arg{it->Arg(0)}; | ||
| 192 | if (arg.IsImmediate()) { | ||
| 193 | break; | ||
| 194 | } | ||
| 195 | it = arg.InstRecursive(); | ||
| 196 | } | ||
| 197 | return *it; | ||
| 198 | } | ||
| 199 | } // namespace Shader::Backend::GLSL | 181 | } // namespace Shader::Backend::GLSL |