diff options
| author | 2021-05-17 19:24:09 -0300 | |
|---|---|---|
| committer | 2021-07-22 21:51:31 -0400 | |
| commit | fb3ba62b3a47ad645b007d5031ed9f8aaa7cb5c0 (patch) | |
| tree | a646ef0f5b2fde47b18f00231157282323c46bf0 /src/shader_recompiler/backend/glasm/reg_alloc.cpp | |
| parent | glasm: Remove unintentional comma on vector insert (diff) | |
| download | yuzu-fb3ba62b3a47ad645b007d5031ed9f8aaa7cb5c0.tar.gz yuzu-fb3ba62b3a47ad645b007d5031ed9f8aaa7cb5c0.tar.xz yuzu-fb3ba62b3a47ad645b007d5031ed9f8aaa7cb5c0.zip | |
glasm: Fix aliased bitcasts ref counting
Diffstat (limited to 'src/shader_recompiler/backend/glasm/reg_alloc.cpp')
| -rw-r--r-- | src/shader_recompiler/backend/glasm/reg_alloc.cpp | 39 |
1 files changed, 32 insertions, 7 deletions
diff --git a/src/shader_recompiler/backend/glasm/reg_alloc.cpp b/src/shader_recompiler/backend/glasm/reg_alloc.cpp index 0e38f467f..707b22247 100644 --- a/src/shader_recompiler/backend/glasm/reg_alloc.cpp +++ b/src/shader_recompiler/backend/glasm/reg_alloc.cpp | |||
| @@ -30,9 +30,10 @@ Value RegAlloc::Consume(const IR::Value& value) { | |||
| 30 | } | 30 | } |
| 31 | 31 | ||
| 32 | void RegAlloc::Unref(IR::Inst& inst) { | 32 | void RegAlloc::Unref(IR::Inst& inst) { |
| 33 | inst.DestructiveRemoveUsage(); | 33 | IR::Inst& value_inst{AliasInst(inst)}; |
| 34 | if (!inst.HasUses()) { | 34 | value_inst.DestructiveRemoveUsage(); |
| 35 | Free(inst.Definition<Id>()); | 35 | if (!value_inst.HasUses()) { |
| 36 | Free(value_inst.Definition<Id>()); | ||
| 36 | } | 37 | } |
| 37 | } | 38 | } |
| 38 | 39 | ||
| @@ -99,10 +100,7 @@ Value RegAlloc::PeekInst(IR::Inst& inst) { | |||
| 99 | } | 100 | } |
| 100 | 101 | ||
| 101 | Value RegAlloc::ConsumeInst(IR::Inst& inst) { | 102 | Value RegAlloc::ConsumeInst(IR::Inst& inst) { |
| 102 | inst.DestructiveRemoveUsage(); | 103 | Unref(inst); |
| 103 | if (!inst.HasUses()) { | ||
| 104 | Free(inst.Definition<Id>()); | ||
| 105 | } | ||
| 106 | return PeekInst(inst); | 104 | return PeekInst(inst); |
| 107 | } | 105 | } |
| 108 | 106 | ||
| @@ -138,4 +136,31 @@ void RegAlloc::Free(Id id) { | |||
| 138 | } | 136 | } |
| 139 | } | 137 | } |
| 140 | 138 | ||
| 139 | /*static*/ bool RegAlloc::IsAliased(const IR::Inst& inst) { | ||
| 140 | switch (inst.GetOpcode()) { | ||
| 141 | case IR::Opcode::Identity: | ||
| 142 | case IR::Opcode::BitCastU16F16: | ||
| 143 | case IR::Opcode::BitCastU32F32: | ||
| 144 | case IR::Opcode::BitCastU64F64: | ||
| 145 | case IR::Opcode::BitCastF16U16: | ||
| 146 | case IR::Opcode::BitCastF32U32: | ||
| 147 | case IR::Opcode::BitCastF64U64: | ||
| 148 | return true; | ||
| 149 | default: | ||
| 150 | return false; | ||
| 151 | } | ||
| 152 | } | ||
| 153 | |||
| 154 | /*static*/ IR::Inst& RegAlloc::AliasInst(IR::Inst& inst) { | ||
| 155 | IR::Inst* it{&inst}; | ||
| 156 | while (IsAliased(*it)) { | ||
| 157 | const IR::Value arg{it->Arg(0)}; | ||
| 158 | if (arg.IsImmediate()) { | ||
| 159 | break; | ||
| 160 | } | ||
| 161 | it = arg.InstRecursive(); | ||
| 162 | } | ||
| 163 | return *it; | ||
| 164 | } | ||
| 165 | |||
| 141 | } // namespace Shader::Backend::GLASM | 166 | } // namespace Shader::Backend::GLASM |