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| author | 2021-06-25 13:09:45 -0400 | |
|---|---|---|
| committer | 2021-07-22 21:51:39 -0400 | |
| commit | 8289eb108fefa9bfbb445c9f6b3f423a5d0eb771 (patch) | |
| tree | e1c72cddcaffd74a9acff03d223576e6d82fbcce /src/shader_recompiler/backend/glasm/emit_glasm_integer.cpp | |
| parent | vk_graphics_pipeline: Implement smooth lines (diff) | |
| download | yuzu-8289eb108fefa9bfbb445c9f6b3f423a5d0eb771.tar.gz yuzu-8289eb108fefa9bfbb445c9f6b3f423a5d0eb771.tar.xz yuzu-8289eb108fefa9bfbb445c9f6b3f423a5d0eb771.zip | |
opengl: Implement LOP.CC
Used by MH:Rise
Diffstat (limited to 'src/shader_recompiler/backend/glasm/emit_glasm_integer.cpp')
| -rw-r--r-- | src/shader_recompiler/backend/glasm/emit_glasm_integer.cpp | 30 |
1 files changed, 27 insertions, 3 deletions
diff --git a/src/shader_recompiler/backend/glasm/emit_glasm_integer.cpp b/src/shader_recompiler/backend/glasm/emit_glasm_integer.cpp index 587bbfe06..f55c26b76 100644 --- a/src/shader_recompiler/backend/glasm/emit_glasm_integer.cpp +++ b/src/shader_recompiler/backend/glasm/emit_glasm_integer.cpp | |||
| @@ -7,6 +7,30 @@ | |||
| 7 | #include "shader_recompiler/frontend/ir/value.h" | 7 | #include "shader_recompiler/frontend/ir/value.h" |
| 8 | 8 | ||
| 9 | namespace Shader::Backend::GLASM { | 9 | namespace Shader::Backend::GLASM { |
| 10 | namespace { | ||
| 11 | void BitwiseLogicalOp(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b, | ||
| 12 | std::string_view lop) { | ||
| 13 | const auto zero = inst.GetAssociatedPseudoOperation(IR::Opcode::GetZeroFromOp); | ||
| 14 | const auto sign = inst.GetAssociatedPseudoOperation(IR::Opcode::GetSignFromOp); | ||
| 15 | if (zero) { | ||
| 16 | zero->Invalidate(); | ||
| 17 | } | ||
| 18 | if (sign) { | ||
| 19 | sign->Invalidate(); | ||
| 20 | } | ||
| 21 | if (zero || sign) { | ||
| 22 | ctx.reg_alloc.InvalidateConditionCodes(); | ||
| 23 | } | ||
| 24 | const auto ret{ctx.reg_alloc.Define(inst)}; | ||
| 25 | ctx.Add("{}.S {}.x,{},{};", lop, ret, a, b); | ||
| 26 | if (zero) { | ||
| 27 | ctx.Add("SEQ.S {},{},0;", *zero, ret); | ||
| 28 | } | ||
| 29 | if (sign) { | ||
| 30 | ctx.Add("SLT.S {},{},0;", *sign, ret); | ||
| 31 | } | ||
| 32 | } | ||
| 33 | } // Anonymous namespace | ||
| 10 | 34 | ||
| 11 | void EmitIAdd32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b) { | 35 | void EmitIAdd32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b) { |
| 12 | const std::array flags{ | 36 | const std::array flags{ |
| @@ -110,15 +134,15 @@ void EmitShiftRightArithmetic64(EmitContext& ctx, IR::Inst& inst, ScalarRegister | |||
| 110 | } | 134 | } |
| 111 | 135 | ||
| 112 | void EmitBitwiseAnd32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b) { | 136 | void EmitBitwiseAnd32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b) { |
| 113 | ctx.Add("AND.S {}.x,{},{};", inst, a, b); | 137 | BitwiseLogicalOp(ctx, inst, a, b, "AND"); |
| 114 | } | 138 | } |
| 115 | 139 | ||
| 116 | void EmitBitwiseOr32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b) { | 140 | void EmitBitwiseOr32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b) { |
| 117 | ctx.Add("OR.S {}.x,{},{};", inst, a, b); | 141 | BitwiseLogicalOp(ctx, inst, a, b, "OR"); |
| 118 | } | 142 | } |
| 119 | 143 | ||
| 120 | void EmitBitwiseXor32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b) { | 144 | void EmitBitwiseXor32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b) { |
| 121 | ctx.Add("XOR.S {}.x,{},{};", inst, a, b); | 145 | BitwiseLogicalOp(ctx, inst, a, b, "XOR"); |
| 122 | } | 146 | } |
| 123 | 147 | ||
| 124 | void EmitBitFieldInsert(EmitContext& ctx, IR::Inst& inst, ScalarS32 base, ScalarS32 insert, | 148 | void EmitBitFieldInsert(EmitContext& ctx, IR::Inst& inst, ScalarS32 base, ScalarS32 insert, |