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authorGravatar ReinUsesLisp2021-05-19 17:09:29 -0300
committerGravatar ameerj2021-07-22 21:51:32 -0400
commit291f220be37d5fed36906b4fce977a5e4e23f481 (patch)
tree57921282aa52ffd16dc8b009bd5a3a2abc6d12b5 /src/shader_recompiler/backend/glasm/emit_glasm_instructions.h
parentglasm: Implement barriers (diff)
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glasm: Implement 64-bit shifts
Diffstat (limited to 'src/shader_recompiler/backend/glasm/emit_glasm_instructions.h')
-rw-r--r--src/shader_recompiler/backend/glasm/emit_glasm_instructions.h8
1 files changed, 5 insertions, 3 deletions
diff --git a/src/shader_recompiler/backend/glasm/emit_glasm_instructions.h b/src/shader_recompiler/backend/glasm/emit_glasm_instructions.h
index 119b166af..94e545ad4 100644
--- a/src/shader_recompiler/backend/glasm/emit_glasm_instructions.h
+++ b/src/shader_recompiler/backend/glasm/emit_glasm_instructions.h
@@ -308,11 +308,13 @@ void EmitINeg64(EmitContext& ctx, IR::Inst& inst, Register value);
308void EmitIAbs32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value); 308void EmitIAbs32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value);
309void EmitIAbs64(EmitContext& ctx, IR::Inst& inst, Register value); 309void EmitIAbs64(EmitContext& ctx, IR::Inst& inst, Register value);
310void EmitShiftLeftLogical32(EmitContext& ctx, IR::Inst& inst, ScalarU32 base, ScalarU32 shift); 310void EmitShiftLeftLogical32(EmitContext& ctx, IR::Inst& inst, ScalarU32 base, ScalarU32 shift);
311void EmitShiftLeftLogical64(EmitContext& ctx, Register base, Register shift); 311void EmitShiftLeftLogical64(EmitContext& ctx, IR::Inst& inst, ScalarRegister base, ScalarU32 shift);
312void EmitShiftRightLogical32(EmitContext& ctx, IR::Inst& inst, ScalarU32 base, ScalarU32 shift); 312void EmitShiftRightLogical32(EmitContext& ctx, IR::Inst& inst, ScalarU32 base, ScalarU32 shift);
313void EmitShiftRightLogical64(EmitContext& ctx, Register base, Register shift); 313void EmitShiftRightLogical64(EmitContext& ctx, IR::Inst& inst, ScalarRegister base,
314 ScalarU32 shift);
314void EmitShiftRightArithmetic32(EmitContext& ctx, IR::Inst& inst, ScalarS32 base, ScalarS32 shift); 315void EmitShiftRightArithmetic32(EmitContext& ctx, IR::Inst& inst, ScalarS32 base, ScalarS32 shift);
315void EmitShiftRightArithmetic64(EmitContext& ctx, Register base, Register shift); 316void EmitShiftRightArithmetic64(EmitContext& ctx, IR::Inst& inst, ScalarRegister base,
317 ScalarS32 shift);
316void EmitBitwiseAnd32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b); 318void EmitBitwiseAnd32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b);
317void EmitBitwiseOr32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b); 319void EmitBitwiseOr32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b);
318void EmitBitwiseXor32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b); 320void EmitBitwiseXor32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b);