diff options
| author | 2021-05-19 17:09:29 -0300 | |
|---|---|---|
| committer | 2021-07-22 21:51:32 -0400 | |
| commit | 291f220be37d5fed36906b4fce977a5e4e23f481 (patch) | |
| tree | 57921282aa52ffd16dc8b009bd5a3a2abc6d12b5 /src/shader_recompiler/backend/glasm/emit_glasm_instructions.h | |
| parent | glasm: Implement barriers (diff) | |
| download | yuzu-291f220be37d5fed36906b4fce977a5e4e23f481.tar.gz yuzu-291f220be37d5fed36906b4fce977a5e4e23f481.tar.xz yuzu-291f220be37d5fed36906b4fce977a5e4e23f481.zip | |
glasm: Implement 64-bit shifts
Diffstat (limited to 'src/shader_recompiler/backend/glasm/emit_glasm_instructions.h')
| -rw-r--r-- | src/shader_recompiler/backend/glasm/emit_glasm_instructions.h | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/shader_recompiler/backend/glasm/emit_glasm_instructions.h b/src/shader_recompiler/backend/glasm/emit_glasm_instructions.h index 119b166af..94e545ad4 100644 --- a/src/shader_recompiler/backend/glasm/emit_glasm_instructions.h +++ b/src/shader_recompiler/backend/glasm/emit_glasm_instructions.h | |||
| @@ -308,11 +308,13 @@ void EmitINeg64(EmitContext& ctx, IR::Inst& inst, Register value); | |||
| 308 | void EmitIAbs32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value); | 308 | void EmitIAbs32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value); |
| 309 | void EmitIAbs64(EmitContext& ctx, IR::Inst& inst, Register value); | 309 | void EmitIAbs64(EmitContext& ctx, IR::Inst& inst, Register value); |
| 310 | void EmitShiftLeftLogical32(EmitContext& ctx, IR::Inst& inst, ScalarU32 base, ScalarU32 shift); | 310 | void EmitShiftLeftLogical32(EmitContext& ctx, IR::Inst& inst, ScalarU32 base, ScalarU32 shift); |
| 311 | void EmitShiftLeftLogical64(EmitContext& ctx, Register base, Register shift); | 311 | void EmitShiftLeftLogical64(EmitContext& ctx, IR::Inst& inst, ScalarRegister base, ScalarU32 shift); |
| 312 | void EmitShiftRightLogical32(EmitContext& ctx, IR::Inst& inst, ScalarU32 base, ScalarU32 shift); | 312 | void EmitShiftRightLogical32(EmitContext& ctx, IR::Inst& inst, ScalarU32 base, ScalarU32 shift); |
| 313 | void EmitShiftRightLogical64(EmitContext& ctx, Register base, Register shift); | 313 | void EmitShiftRightLogical64(EmitContext& ctx, IR::Inst& inst, ScalarRegister base, |
| 314 | ScalarU32 shift); | ||
| 314 | void EmitShiftRightArithmetic32(EmitContext& ctx, IR::Inst& inst, ScalarS32 base, ScalarS32 shift); | 315 | void EmitShiftRightArithmetic32(EmitContext& ctx, IR::Inst& inst, ScalarS32 base, ScalarS32 shift); |
| 315 | void EmitShiftRightArithmetic64(EmitContext& ctx, Register base, Register shift); | 316 | void EmitShiftRightArithmetic64(EmitContext& ctx, IR::Inst& inst, ScalarRegister base, |
| 317 | ScalarS32 shift); | ||
| 316 | void EmitBitwiseAnd32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b); | 318 | void EmitBitwiseAnd32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b); |
| 317 | void EmitBitwiseOr32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b); | 319 | void EmitBitwiseOr32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b); |
| 318 | void EmitBitwiseXor32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b); | 320 | void EmitBitwiseXor32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b); |