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| author | 2021-05-21 21:42:48 -0300 | |
|---|---|---|
| committer | 2021-07-22 21:51:33 -0400 | |
| commit | c8414e686f30b3bec7f179ee7ab800f223f8ece0 (patch) | |
| tree | 73e86260d181d7022eacdc7821b6d41b3b47e13b /src/shader_recompiler/backend/glasm/emit_glasm_image.cpp | |
| parent | glasm: Reorder unreachable image atomic insts (diff) | |
| download | yuzu-c8414e686f30b3bec7f179ee7ab800f223f8ece0.tar.gz yuzu-c8414e686f30b3bec7f179ee7ab800f223f8ece0.tar.xz yuzu-c8414e686f30b3bec7f179ee7ab800f223f8ece0.zip | |
glasm: Implement image atomics
Diffstat (limited to 'src/shader_recompiler/backend/glasm/emit_glasm_image.cpp')
| -rw-r--r-- | src/shader_recompiler/backend/glasm/emit_glasm_image.cpp | 153 |
1 files changed, 153 insertions, 0 deletions
diff --git a/src/shader_recompiler/backend/glasm/emit_glasm_image.cpp b/src/shader_recompiler/backend/glasm/emit_glasm_image.cpp index 385ca51ac..a7def0897 100644 --- a/src/shader_recompiler/backend/glasm/emit_glasm_image.cpp +++ b/src/shader_recompiler/backend/glasm/emit_glasm_image.cpp | |||
| @@ -205,6 +205,16 @@ std::string_view FormatStorage(ImageFormat format) { | |||
| 205 | } | 205 | } |
| 206 | throw InvalidArgument("Invalid image format {}", format); | 206 | throw InvalidArgument("Invalid image format {}", format); |
| 207 | } | 207 | } |
| 208 | |||
| 209 | template <typename T> | ||
| 210 | void ImageAtomic(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord, T value, | ||
| 211 | std::string_view op) { | ||
| 212 | const auto info{inst.Flags<IR::TextureInstInfo>()}; | ||
| 213 | const std::string_view type{TextureType(info)}; | ||
| 214 | const std::string image{Image(ctx, info, index)}; | ||
| 215 | const Register ret{ctx.reg_alloc.Define(inst)}; | ||
| 216 | ctx.Add("ATOMIM.{} {},{},{},{},{};", op, ret, value, coord, image, type); | ||
| 217 | } | ||
| 208 | } // Anonymous namespace | 218 | } // Anonymous namespace |
| 209 | 219 | ||
| 210 | void EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, | 220 | void EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, |
| @@ -590,6 +600,61 @@ void EmitImageWrite(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Re | |||
| 590 | ctx.Add("STOREIM.{} {},{},{},{};", format, image, color, coord, type); | 600 | ctx.Add("STOREIM.{} {},{},{},{};", format, image, color, coord, type); |
| 591 | } | 601 | } |
| 592 | 602 | ||
| 603 | void EmitImageAtomicIAdd32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord, | ||
| 604 | ScalarU32 value) { | ||
| 605 | ImageAtomic(ctx, inst, index, coord, value, "ADD.U32"); | ||
| 606 | } | ||
| 607 | |||
| 608 | void EmitImageAtomicSMin32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord, | ||
| 609 | ScalarS32 value) { | ||
| 610 | ImageAtomic(ctx, inst, index, coord, value, "MIN.S32"); | ||
| 611 | } | ||
| 612 | |||
| 613 | void EmitImageAtomicUMin32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord, | ||
| 614 | ScalarU32 value) { | ||
| 615 | ImageAtomic(ctx, inst, index, coord, value, "MIN.U32"); | ||
| 616 | } | ||
| 617 | |||
| 618 | void EmitImageAtomicSMax32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord, | ||
| 619 | ScalarS32 value) { | ||
| 620 | ImageAtomic(ctx, inst, index, coord, value, "MAX.S32"); | ||
| 621 | } | ||
| 622 | |||
| 623 | void EmitImageAtomicUMax32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord, | ||
| 624 | ScalarU32 value) { | ||
| 625 | ImageAtomic(ctx, inst, index, coord, value, "MAX.U32"); | ||
| 626 | } | ||
| 627 | |||
| 628 | void EmitImageAtomicInc32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord, | ||
| 629 | ScalarU32 value) { | ||
| 630 | ImageAtomic(ctx, inst, index, coord, value, "IWRAP.U32"); | ||
| 631 | } | ||
| 632 | |||
| 633 | void EmitImageAtomicDec32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord, | ||
| 634 | ScalarU32 value) { | ||
| 635 | ImageAtomic(ctx, inst, index, coord, value, "DWRAP.U32"); | ||
| 636 | } | ||
| 637 | |||
| 638 | void EmitImageAtomicAnd32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord, | ||
| 639 | ScalarU32 value) { | ||
| 640 | ImageAtomic(ctx, inst, index, coord, value, "AND.U32"); | ||
| 641 | } | ||
| 642 | |||
| 643 | void EmitImageAtomicOr32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord, | ||
| 644 | ScalarU32 value) { | ||
| 645 | ImageAtomic(ctx, inst, index, coord, value, "OR.U32"); | ||
| 646 | } | ||
| 647 | |||
| 648 | void EmitImageAtomicXor32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord, | ||
| 649 | ScalarU32 value) { | ||
| 650 | ImageAtomic(ctx, inst, index, coord, value, "XOR.U32"); | ||
| 651 | } | ||
| 652 | |||
| 653 | void EmitImageAtomicExchange32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, | ||
| 654 | Register coord, ScalarU32 value) { | ||
| 655 | ImageAtomic(ctx, inst, index, coord, value, "EXCH.U32"); | ||
| 656 | } | ||
| 657 | |||
| 593 | void EmitBindlessImageSampleImplicitLod(EmitContext&) { | 658 | void EmitBindlessImageSampleImplicitLod(EmitContext&) { |
| 594 | throw LogicError("Unreachable instruction"); | 659 | throw LogicError("Unreachable instruction"); |
| 595 | } | 660 | } |
| @@ -686,4 +751,92 @@ void EmitBoundImageWrite(EmitContext&) { | |||
| 686 | throw LogicError("Unreachable instruction"); | 751 | throw LogicError("Unreachable instruction"); |
| 687 | } | 752 | } |
| 688 | 753 | ||
| 754 | void EmitBindlessImageAtomicIAdd32(EmitContext&) { | ||
| 755 | throw LogicError("Unreachable instruction"); | ||
| 756 | } | ||
| 757 | |||
| 758 | void EmitBindlessImageAtomicSMin32(EmitContext&) { | ||
| 759 | throw LogicError("Unreachable instruction"); | ||
| 760 | } | ||
| 761 | |||
| 762 | void EmitBindlessImageAtomicUMin32(EmitContext&) { | ||
| 763 | throw LogicError("Unreachable instruction"); | ||
| 764 | } | ||
| 765 | |||
| 766 | void EmitBindlessImageAtomicSMax32(EmitContext&) { | ||
| 767 | throw LogicError("Unreachable instruction"); | ||
| 768 | } | ||
| 769 | |||
| 770 | void EmitBindlessImageAtomicUMax32(EmitContext&) { | ||
| 771 | throw LogicError("Unreachable instruction"); | ||
| 772 | } | ||
| 773 | |||
| 774 | void EmitBindlessImageAtomicInc32(EmitContext&) { | ||
| 775 | throw LogicError("Unreachable instruction"); | ||
| 776 | } | ||
| 777 | |||
| 778 | void EmitBindlessImageAtomicDec32(EmitContext&) { | ||
| 779 | throw LogicError("Unreachable instruction"); | ||
| 780 | } | ||
| 781 | |||
| 782 | void EmitBindlessImageAtomicAnd32(EmitContext&) { | ||
| 783 | throw LogicError("Unreachable instruction"); | ||
| 784 | } | ||
| 785 | |||
| 786 | void EmitBindlessImageAtomicOr32(EmitContext&) { | ||
| 787 | throw LogicError("Unreachable instruction"); | ||
| 788 | } | ||
| 789 | |||
| 790 | void EmitBindlessImageAtomicXor32(EmitContext&) { | ||
| 791 | throw LogicError("Unreachable instruction"); | ||
| 792 | } | ||
| 793 | |||
| 794 | void EmitBindlessImageAtomicExchange32(EmitContext&) { | ||
| 795 | throw LogicError("Unreachable instruction"); | ||
| 796 | } | ||
| 797 | |||
| 798 | void EmitBoundImageAtomicIAdd32(EmitContext&) { | ||
| 799 | throw LogicError("Unreachable instruction"); | ||
| 800 | } | ||
| 801 | |||
| 802 | void EmitBoundImageAtomicSMin32(EmitContext&) { | ||
| 803 | throw LogicError("Unreachable instruction"); | ||
| 804 | } | ||
| 805 | |||
| 806 | void EmitBoundImageAtomicUMin32(EmitContext&) { | ||
| 807 | throw LogicError("Unreachable instruction"); | ||
| 808 | } | ||
| 809 | |||
| 810 | void EmitBoundImageAtomicSMax32(EmitContext&) { | ||
| 811 | throw LogicError("Unreachable instruction"); | ||
| 812 | } | ||
| 813 | |||
| 814 | void EmitBoundImageAtomicUMax32(EmitContext&) { | ||
| 815 | throw LogicError("Unreachable instruction"); | ||
| 816 | } | ||
| 817 | |||
| 818 | void EmitBoundImageAtomicInc32(EmitContext&) { | ||
| 819 | throw LogicError("Unreachable instruction"); | ||
| 820 | } | ||
| 821 | |||
| 822 | void EmitBoundImageAtomicDec32(EmitContext&) { | ||
| 823 | throw LogicError("Unreachable instruction"); | ||
| 824 | } | ||
| 825 | |||
| 826 | void EmitBoundImageAtomicAnd32(EmitContext&) { | ||
| 827 | throw LogicError("Unreachable instruction"); | ||
| 828 | } | ||
| 829 | |||
| 830 | void EmitBoundImageAtomicOr32(EmitContext&) { | ||
| 831 | throw LogicError("Unreachable instruction"); | ||
| 832 | } | ||
| 833 | |||
| 834 | void EmitBoundImageAtomicXor32(EmitContext&) { | ||
| 835 | throw LogicError("Unreachable instruction"); | ||
| 836 | } | ||
| 837 | |||
| 838 | void EmitBoundImageAtomicExchange32(EmitContext&) { | ||
| 839 | throw LogicError("Unreachable instruction"); | ||
| 840 | } | ||
| 841 | |||
| 689 | } // namespace Shader::Backend::GLASM | 842 | } // namespace Shader::Backend::GLASM |