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| author |  Lioncash | 2015-01-12 14:12:05 -0500 |
|---|---|---|
| committer | Lioncash | 2015-01-12 14:15:24 -0500 |
| commit | f7770b83d49f3ac791f095ade399705a4d04fe63 (patch) | |
| tree | 55448ac982348dae114371d67ad9fb899370b1e1 /src/core | |
| parent | Merge pull request #475 from lioncash/cleanup (diff) | |
| download | yuzu-f7770b83d49f3ac791f095ade399705a4d04fe63.tar.gz yuzu-f7770b83d49f3ac791f095ade399705a4d04fe63.tar.xz yuzu-f7770b83d49f3ac791f095ade399705a4d04fe63.zip | |
dyncom: Fix 32-bit ASR shifts for immediates
Diffstat (limited to 'src/core')
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index c6a9baae3..b5e0993ed 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp | |||
| @@ -176,13 +176,11 @@ unsigned int DPO(ArithmeticShiftRightByImmediate)(arm_processor *cpu, unsigned i | |||
| 176 | unsigned int shifter_operand; | 176 | unsigned int shifter_operand; |
| 177 | int shift_imm = BITS(sht_oper, 7, 11); | 177 | int shift_imm = BITS(sht_oper, 7, 11); |
| 178 | if (shift_imm == 0) { | 178 | if (shift_imm == 0) { |
| 179 | if (BIT(rm, 31)) { | 179 | if (BIT(rm, 31) == 0) |
| 180 | shifter_operand = 0; | 180 | shifter_operand = 0; |
| 181 | cpu->shifter_carry_out = BIT(rm, 31); | 181 | else |
| 182 | } else { | ||
| 183 | shifter_operand = 0xFFFFFFFF; | 182 | shifter_operand = 0xFFFFFFFF; |
| 184 | cpu->shifter_carry_out = BIT(rm, 31); | 183 | cpu->shifter_carry_out = BIT(rm, 31); |
| 185 | } | ||
| 186 | } else { | 184 | } else { |
| 187 | shifter_operand = static_cast<int>(rm) >> shift_imm; | 185 | shifter_operand = static_cast<int>(rm) >> shift_imm; |
| 188 | cpu->shifter_carry_out = BIT(rm, shift_imm - 1); | 186 | cpu->shifter_carry_out = BIT(rm, shift_imm - 1); |