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authorGravatar bunnei2016-03-22 08:38:48 -0400
committerGravatar bunnei2016-03-22 08:38:48 -0400
commite16899783d6ad6a81f330164af0f81102485c12b (patch)
treea50b52e1a1f2f5787e54dba46cd9c9130f8c14f6 /src/core
parentMerge pull request #1559 from lioncash/vec (diff)
parentarmstate: Correct FIQ register banking (diff)
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Merge pull request #1563 from lioncash/lolfiq
armstate: Correct FIQ register banking
Diffstat (limited to 'src/core')
-rw-r--r--src/core/arm/skyeye_common/armstate.cpp7
1 files changed, 3 insertions, 4 deletions
diff --git a/src/core/arm/skyeye_common/armstate.cpp b/src/core/arm/skyeye_common/armstate.cpp
index 2d814345a..5550c112e 100644
--- a/src/core/arm/skyeye_common/armstate.cpp
+++ b/src/core/arm/skyeye_common/armstate.cpp
@@ -2,6 +2,7 @@
2// Licensed under GPLv2 or any later version 2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included. 3// Refer to the license.txt file included.
4 4
5#include <algorithm>
5#include "common/swap.h" 6#include "common/swap.h"
6#include "common/logging/log.h" 7#include "common/logging/log.h"
7#include "core/memory.h" 8#include "core/memory.h"
@@ -48,8 +49,7 @@ void ARMul_State::ChangePrivilegeMode(u32 new_mode)
48 Spsr[UNDEFBANK] = Spsr_copy; 49 Spsr[UNDEFBANK] = Spsr_copy;
49 break; 50 break;
50 case FIQ32MODE: 51 case FIQ32MODE:
51 Reg_firq[0] = Reg[13]; 52 std::copy(Reg.begin() + 8, Reg.end() - 1, Reg_firq.begin());
52 Reg_firq[1] = Reg[14];
53 Spsr[FIQBANK] = Spsr_copy; 53 Spsr[FIQBANK] = Spsr_copy;
54 break; 54 break;
55 } 55 }
@@ -85,8 +85,7 @@ void ARMul_State::ChangePrivilegeMode(u32 new_mode)
85 Bank = UNDEFBANK; 85 Bank = UNDEFBANK;
86 break; 86 break;
87 case FIQ32MODE: 87 case FIQ32MODE:
88 Reg[13] = Reg_firq[0]; 88 std::copy(Reg_firq.begin(), Reg_firq.end(), Reg.begin() + 8);
89 Reg[14] = Reg_firq[1];
90 Spsr_copy = Spsr[FIQBANK]; 89 Spsr_copy = Spsr[FIQBANK];
91 Bank = FIQBANK; 90 Bank = FIQBANK;
92 break; 91 break;