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| author | 2015-07-13 21:39:58 +0200 | |
|---|---|---|
| committer | 2015-07-13 21:39:58 +0200 | |
| commit | 884b681ccaf3cb4057ca0ed0102e446736bb535f (patch) | |
| tree | 9359e9b88f0147879c672638d8c02960d2179d3a /src/core | |
| parent | Merge pull request #859 from Apology11/master (diff) | |
| parent | CiTrace: Clean up initialization method. (diff) | |
| download | yuzu-884b681ccaf3cb4057ca0ed0102e446736bb535f.tar.gz yuzu-884b681ccaf3cb4057ca0ed0102e446736bb535f.tar.xz yuzu-884b681ccaf3cb4057ca0ed0102e446736bb535f.zip | |
Merge pull request #702 from neobrain/citrace
Add CiTrace recording support.
Diffstat (limited to 'src/core')
| -rw-r--r-- | src/core/CMakeLists.txt | 3 | ||||
| -rw-r--r-- | src/core/hle/service/gsp_gpu.cpp | 2 | ||||
| -rw-r--r-- | src/core/hw/gpu.cpp | 78 | ||||
| -rw-r--r-- | src/core/hw/hw.cpp | 30 | ||||
| -rw-r--r-- | src/core/hw/lcd.cpp | 10 | ||||
| -rw-r--r-- | src/core/tracer/citrace.h | 101 | ||||
| -rw-r--r-- | src/core/tracer/recorder.cpp | 187 | ||||
| -rw-r--r-- | src/core/tracer/recorder.h | 90 |
8 files changed, 473 insertions, 28 deletions
diff --git a/src/core/CMakeLists.txt b/src/core/CMakeLists.txt index 9b004440c..8267ee586 100644 --- a/src/core/CMakeLists.txt +++ b/src/core/CMakeLists.txt | |||
| @@ -115,6 +115,7 @@ set(SRCS | |||
| 115 | loader/elf.cpp | 115 | loader/elf.cpp |
| 116 | loader/loader.cpp | 116 | loader/loader.cpp |
| 117 | loader/ncch.cpp | 117 | loader/ncch.cpp |
| 118 | tracer/recorder.cpp | ||
| 118 | mem_map.cpp | 119 | mem_map.cpp |
| 119 | memory.cpp | 120 | memory.cpp |
| 120 | settings.cpp | 121 | settings.cpp |
| @@ -243,6 +244,8 @@ set(HEADERS | |||
| 243 | loader/elf.h | 244 | loader/elf.h |
| 244 | loader/loader.h | 245 | loader/loader.h |
| 245 | loader/ncch.h | 246 | loader/ncch.h |
| 247 | tracer/recorder.h | ||
| 248 | tracer/citrace.h | ||
| 246 | mem_map.h | 249 | mem_map.h |
| 247 | memory.h | 250 | memory.h |
| 248 | memory_setup.h | 251 | memory_setup.h |
diff --git a/src/core/hle/service/gsp_gpu.cpp b/src/core/hle/service/gsp_gpu.cpp index f175085e8..3910d0227 100644 --- a/src/core/hle/service/gsp_gpu.cpp +++ b/src/core/hle/service/gsp_gpu.cpp | |||
| @@ -349,7 +349,7 @@ void SignalInterrupt(InterruptId interrupt_id) { | |||
| 349 | /// Executes the next GSP command | 349 | /// Executes the next GSP command |
| 350 | static void ExecuteCommand(const Command& command, u32 thread_id) { | 350 | static void ExecuteCommand(const Command& command, u32 thread_id) { |
| 351 | // Utility function to convert register ID to address | 351 | // Utility function to convert register ID to address |
| 352 | auto WriteGPURegister = [](u32 id, u32 data) { | 352 | static auto WriteGPURegister = [](u32 id, u32 data) { |
| 353 | GPU::Write<u32>(0x1EF00000 + 4 * id, data); | 353 | GPU::Write<u32>(0x1EF00000 + 4 * id, data); |
| 354 | }; | 354 | }; |
| 355 | 355 | ||
diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp index a1789f9c7..a3a7d128f 100644 --- a/src/core/hw/gpu.cpp +++ b/src/core/hw/gpu.cpp | |||
| @@ -21,12 +21,17 @@ | |||
| 21 | #include "core/hw/hw.h" | 21 | #include "core/hw/hw.h" |
| 22 | #include "core/hw/gpu.h" | 22 | #include "core/hw/gpu.h" |
| 23 | 23 | ||
| 24 | #include "core/tracer/recorder.h" | ||
| 25 | |||
| 24 | #include "video_core/command_processor.h" | 26 | #include "video_core/command_processor.h" |
| 25 | #include "video_core/hwrasterizer_base.h" | 27 | #include "video_core/hwrasterizer_base.h" |
| 26 | #include "video_core/renderer_base.h" | 28 | #include "video_core/renderer_base.h" |
| 27 | #include "video_core/utils.h" | 29 | #include "video_core/utils.h" |
| 28 | #include "video_core/video_core.h" | 30 | #include "video_core/video_core.h" |
| 29 | 31 | ||
| 32 | #include "video_core/debug_utils/debug_utils.h" | ||
| 33 | |||
| 34 | |||
| 30 | namespace GPU { | 35 | namespace GPU { |
| 31 | 36 | ||
| 32 | Regs g_regs; | 37 | Regs g_regs; |
| @@ -101,39 +106,43 @@ inline void Write(u32 addr, const T data) { | |||
| 101 | const bool is_second_filler = (index != GPU_REG_INDEX(memory_fill_config[0].trigger)); | 106 | const bool is_second_filler = (index != GPU_REG_INDEX(memory_fill_config[0].trigger)); |
| 102 | auto& config = g_regs.memory_fill_config[is_second_filler]; | 107 | auto& config = g_regs.memory_fill_config[is_second_filler]; |
| 103 | 108 | ||
| 104 | if (config.address_start && config.trigger) { | 109 | if (config.trigger) { |
| 105 | u8* start = Memory::GetPhysicalPointer(config.GetStartAddress()); | 110 | if (config.address_start) { // Some games pass invalid values here |
| 106 | u8* end = Memory::GetPhysicalPointer(config.GetEndAddress()); | 111 | u8* start = Memory::GetPhysicalPointer(config.GetStartAddress()); |
| 107 | 112 | u8* end = Memory::GetPhysicalPointer(config.GetEndAddress()); | |
| 108 | if (config.fill_24bit) { | 113 | |
| 109 | // fill with 24-bit values | 114 | if (config.fill_24bit) { |
| 110 | for (u8* ptr = start; ptr < end; ptr += 3) { | 115 | // fill with 24-bit values |
| 111 | ptr[0] = config.value_24bit_r; | 116 | for (u8* ptr = start; ptr < end; ptr += 3) { |
| 112 | ptr[1] = config.value_24bit_g; | 117 | ptr[0] = config.value_24bit_r; |
| 113 | ptr[2] = config.value_24bit_b; | 118 | ptr[1] = config.value_24bit_g; |
| 119 | ptr[2] = config.value_24bit_b; | ||
| 120 | } | ||
| 121 | } else if (config.fill_32bit) { | ||
| 122 | // fill with 32-bit values | ||
| 123 | for (u32* ptr = (u32*)start; ptr < (u32*)end; ++ptr) | ||
| 124 | *ptr = config.value_32bit; | ||
| 125 | } else { | ||
| 126 | // fill with 16-bit values | ||
| 127 | for (u16* ptr = (u16*)start; ptr < (u16*)end; ++ptr) | ||
| 128 | *ptr = config.value_16bit; | ||
| 114 | } | 129 | } |
| 115 | } else if (config.fill_32bit) { | ||
| 116 | // fill with 32-bit values | ||
| 117 | for (u32* ptr = (u32*)start; ptr < (u32*)end; ++ptr) | ||
| 118 | *ptr = config.value_32bit; | ||
| 119 | } else { | ||
| 120 | // fill with 16-bit values | ||
| 121 | for (u16* ptr = (u16*)start; ptr < (u16*)end; ++ptr) | ||
| 122 | *ptr = config.value_16bit; | ||
| 123 | } | ||
| 124 | 130 | ||
| 125 | LOG_TRACE(HW_GPU, "MemoryFill from 0x%08x to 0x%08x", config.GetStartAddress(), config.GetEndAddress()); | 131 | LOG_TRACE(HW_GPU, "MemoryFill from 0x%08x to 0x%08x", config.GetStartAddress(), config.GetEndAddress()); |
| 126 | 132 | ||
| 127 | config.trigger = 0; | 133 | if (!is_second_filler) { |
| 128 | config.finished = 1; | 134 | GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PSC0); |
| 135 | } else { | ||
| 136 | GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PSC1); | ||
| 137 | } | ||
| 129 | 138 | ||
| 130 | if (!is_second_filler) { | 139 | VideoCore::g_renderer->hw_rasterizer->NotifyFlush(config.GetStartAddress(), config.GetEndAddress() - config.GetStartAddress()); |
| 131 | GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PSC0); | ||
| 132 | } else { | ||
| 133 | GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PSC1); | ||
| 134 | } | 140 | } |
| 135 | 141 | ||
| 136 | VideoCore::g_renderer->hw_rasterizer->NotifyFlush(config.GetStartAddress(), config.GetEndAddress() - config.GetStartAddress()); | 142 | // Reset "trigger" flag and set the "finish" flag |
| 143 | // NOTE: This was confirmed to happen on hardware even if "address_start" is zero. | ||
| 144 | config.trigger = 0; | ||
| 145 | config.finished = 1; | ||
| 137 | } | 146 | } |
| 138 | break; | 147 | break; |
| 139 | } | 148 | } |
| @@ -270,6 +279,7 @@ inline void Write(u32 addr, const T data) { | |||
| 270 | config.GetPhysicalOutputAddress(), output_width, output_height, | 279 | config.GetPhysicalOutputAddress(), output_width, output_height, |
| 271 | config.output_format.Value(), config.flags); | 280 | config.output_format.Value(), config.flags); |
| 272 | 281 | ||
| 282 | g_regs.display_transfer_config.trigger = 0; | ||
| 273 | GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PPF); | 283 | GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PPF); |
| 274 | 284 | ||
| 275 | VideoCore::g_renderer->hw_rasterizer->NotifyFlush(config.GetPhysicalOutputAddress(), output_size); | 285 | VideoCore::g_renderer->hw_rasterizer->NotifyFlush(config.GetPhysicalOutputAddress(), output_size); |
| @@ -284,7 +294,14 @@ inline void Write(u32 addr, const T data) { | |||
| 284 | if (config.trigger & 1) | 294 | if (config.trigger & 1) |
| 285 | { | 295 | { |
| 286 | u32* buffer = (u32*)Memory::GetPhysicalPointer(config.GetPhysicalAddress()); | 296 | u32* buffer = (u32*)Memory::GetPhysicalPointer(config.GetPhysicalAddress()); |
| 297 | |||
| 298 | if (Pica::g_debug_context && Pica::g_debug_context->recorder) { | ||
| 299 | Pica::g_debug_context->recorder->MemoryAccessed((u8*)buffer, config.size * sizeof(u32), config.GetPhysicalAddress()); | ||
| 300 | } | ||
| 301 | |||
| 287 | Pica::CommandProcessor::ProcessCommandList(buffer, config.size); | 302 | Pica::CommandProcessor::ProcessCommandList(buffer, config.size); |
| 303 | |||
| 304 | g_regs.command_processor_config.trigger = 0; | ||
| 288 | } | 305 | } |
| 289 | break; | 306 | break; |
| 290 | } | 307 | } |
| @@ -292,6 +309,13 @@ inline void Write(u32 addr, const T data) { | |||
| 292 | default: | 309 | default: |
| 293 | break; | 310 | break; |
| 294 | } | 311 | } |
| 312 | |||
| 313 | // Notify tracer about the register write | ||
| 314 | // This is happening *after* handling the write to make sure we properly catch all memory reads. | ||
| 315 | if (Pica::g_debug_context && Pica::g_debug_context->recorder) { | ||
| 316 | // addr + GPU VBase - IO VBase + IO PBase | ||
| 317 | Pica::g_debug_context->recorder->RegisterWritten<T>(addr + 0x1EF00000 - 0x1EC00000 + 0x10100000, data); | ||
| 318 | } | ||
| 295 | } | 319 | } |
| 296 | 320 | ||
| 297 | // Explicitly instantiate template functions because we aren't defining this in the header: | 321 | // Explicitly instantiate template functions because we aren't defining this in the header: |
diff --git a/src/core/hw/hw.cpp b/src/core/hw/hw.cpp index c7006a498..b5fdbf9c1 100644 --- a/src/core/hw/hw.cpp +++ b/src/core/hw/hw.cpp | |||
| @@ -15,6 +15,21 @@ template <typename T> | |||
| 15 | inline void Read(T &var, const u32 addr) { | 15 | inline void Read(T &var, const u32 addr) { |
| 16 | switch (addr & 0xFFFFF000) { | 16 | switch (addr & 0xFFFFF000) { |
| 17 | case VADDR_GPU: | 17 | case VADDR_GPU: |
| 18 | case VADDR_GPU + 0x1000: | ||
| 19 | case VADDR_GPU + 0x2000: | ||
| 20 | case VADDR_GPU + 0x3000: | ||
| 21 | case VADDR_GPU + 0x4000: | ||
| 22 | case VADDR_GPU + 0x5000: | ||
| 23 | case VADDR_GPU + 0x6000: | ||
| 24 | case VADDR_GPU + 0x7000: | ||
| 25 | case VADDR_GPU + 0x8000: | ||
| 26 | case VADDR_GPU + 0x9000: | ||
| 27 | case VADDR_GPU + 0xA000: | ||
| 28 | case VADDR_GPU + 0xB000: | ||
| 29 | case VADDR_GPU + 0xC000: | ||
| 30 | case VADDR_GPU + 0xD000: | ||
| 31 | case VADDR_GPU + 0xE000: | ||
| 32 | case VADDR_GPU + 0xF000: | ||
| 18 | GPU::Read(var, addr); | 33 | GPU::Read(var, addr); |
| 19 | break; | 34 | break; |
| 20 | case VADDR_LCD: | 35 | case VADDR_LCD: |
| @@ -29,6 +44,21 @@ template <typename T> | |||
| 29 | inline void Write(u32 addr, const T data) { | 44 | inline void Write(u32 addr, const T data) { |
| 30 | switch (addr & 0xFFFFF000) { | 45 | switch (addr & 0xFFFFF000) { |
| 31 | case VADDR_GPU: | 46 | case VADDR_GPU: |
| 47 | case VADDR_GPU + 0x1000: | ||
| 48 | case VADDR_GPU + 0x2000: | ||
| 49 | case VADDR_GPU + 0x3000: | ||
| 50 | case VADDR_GPU + 0x4000: | ||
| 51 | case VADDR_GPU + 0x5000: | ||
| 52 | case VADDR_GPU + 0x6000: | ||
| 53 | case VADDR_GPU + 0x7000: | ||
| 54 | case VADDR_GPU + 0x8000: | ||
| 55 | case VADDR_GPU + 0x9000: | ||
| 56 | case VADDR_GPU + 0xA000: | ||
| 57 | case VADDR_GPU + 0xB000: | ||
| 58 | case VADDR_GPU + 0xC000: | ||
| 59 | case VADDR_GPU + 0xD000: | ||
| 60 | case VADDR_GPU + 0xE000: | ||
| 61 | case VADDR_GPU + 0xF000: | ||
| 32 | GPU::Write(addr, data); | 62 | GPU::Write(addr, data); |
| 33 | break; | 63 | break; |
| 34 | case VADDR_LCD: | 64 | case VADDR_LCD: |
diff --git a/src/core/hw/lcd.cpp b/src/core/hw/lcd.cpp index cdb757a18..6f93709e3 100644 --- a/src/core/hw/lcd.cpp +++ b/src/core/hw/lcd.cpp | |||
| @@ -10,6 +10,9 @@ | |||
| 10 | #include "core/hw/hw.h" | 10 | #include "core/hw/hw.h" |
| 11 | #include "core/hw/lcd.h" | 11 | #include "core/hw/lcd.h" |
| 12 | 12 | ||
| 13 | #include "core/tracer/recorder.h" | ||
| 14 | #include "video_core/debug_utils/debug_utils.h" | ||
| 15 | |||
| 13 | namespace LCD { | 16 | namespace LCD { |
| 14 | 17 | ||
| 15 | Regs g_regs; | 18 | Regs g_regs; |
| @@ -40,6 +43,13 @@ inline void Write(u32 addr, const T data) { | |||
| 40 | } | 43 | } |
| 41 | 44 | ||
| 42 | g_regs[index] = static_cast<u32>(data); | 45 | g_regs[index] = static_cast<u32>(data); |
| 46 | |||
| 47 | // Notify tracer about the register write | ||
| 48 | // This is happening *after* handling the write to make sure we properly catch all memory reads. | ||
| 49 | if (Pica::g_debug_context && Pica::g_debug_context->recorder) { | ||
| 50 | // addr + GPU VBase - IO VBase + IO PBase | ||
| 51 | Pica::g_debug_context->recorder->RegisterWritten<T>(addr + HW::VADDR_LCD - 0x1EC00000 + 0x10100000, data); | ||
| 52 | } | ||
| 43 | } | 53 | } |
| 44 | 54 | ||
| 45 | // Explicitly instantiate template functions because we aren't defining this in the header: | 55 | // Explicitly instantiate template functions because we aren't defining this in the header: |
diff --git a/src/core/tracer/citrace.h b/src/core/tracer/citrace.h new file mode 100644 index 000000000..5deb6ce9e --- /dev/null +++ b/src/core/tracer/citrace.h | |||
| @@ -0,0 +1,101 @@ | |||
| 1 | // Copyright 2015 Citra Emulator Project | ||
| 2 | // Licensed under GPLv2 or any later version | ||
| 3 | // Refer to the license.txt file included. | ||
| 4 | |||
| 5 | #pragma once | ||
| 6 | |||
| 7 | #include <cstdint> | ||
| 8 | |||
| 9 | namespace CiTrace { | ||
| 10 | |||
| 11 | // NOTE: Things are stored in little-endian | ||
| 12 | |||
| 13 | #pragma pack(1) | ||
| 14 | |||
| 15 | struct CTHeader { | ||
| 16 | static const char* ExpectedMagicWord() { | ||
| 17 | return "CiTr"; | ||
| 18 | } | ||
| 19 | |||
| 20 | static uint32_t ExpectedVersion() { | ||
| 21 | return 1; | ||
| 22 | } | ||
| 23 | |||
| 24 | char magic[4]; | ||
| 25 | uint32_t version; | ||
| 26 | uint32_t header_size; | ||
| 27 | |||
| 28 | struct { | ||
| 29 | // NOTE: Register range sizes are technically hardware-constants, but the actual limits | ||
| 30 | // aren't known. Hence we store the presumed limits along the offsets. | ||
| 31 | // Sizes are given in uint32_t units. | ||
| 32 | uint32_t gpu_registers; | ||
| 33 | uint32_t gpu_registers_size; | ||
| 34 | uint32_t lcd_registers; | ||
| 35 | uint32_t lcd_registers_size; | ||
| 36 | uint32_t pica_registers; | ||
| 37 | uint32_t pica_registers_size; | ||
| 38 | uint32_t default_attributes; | ||
| 39 | uint32_t default_attributes_size; | ||
| 40 | uint32_t vs_program_binary; | ||
| 41 | uint32_t vs_program_binary_size; | ||
| 42 | uint32_t vs_swizzle_data; | ||
| 43 | uint32_t vs_swizzle_data_size; | ||
| 44 | uint32_t vs_float_uniforms; | ||
| 45 | uint32_t vs_float_uniforms_size; | ||
| 46 | uint32_t gs_program_binary; | ||
| 47 | uint32_t gs_program_binary_size; | ||
| 48 | uint32_t gs_swizzle_data; | ||
| 49 | uint32_t gs_swizzle_data_size; | ||
| 50 | uint32_t gs_float_uniforms; | ||
| 51 | uint32_t gs_float_uniforms_size; | ||
| 52 | |||
| 53 | // Other things we might want to store here: | ||
| 54 | // - Initial framebuffer data, maybe even a full copy of FCRAM/VRAM | ||
| 55 | // - Lookup tables for fragment lighting | ||
| 56 | // - Lookup tables for procedural textures | ||
| 57 | } initial_state_offsets; | ||
| 58 | |||
| 59 | uint32_t stream_offset; | ||
| 60 | uint32_t stream_size; | ||
| 61 | }; | ||
| 62 | |||
| 63 | enum CTStreamElementType : uint32_t { | ||
| 64 | FrameMarker = 0xE1, | ||
| 65 | MemoryLoad = 0xE2, | ||
| 66 | RegisterWrite = 0xE3, | ||
| 67 | }; | ||
| 68 | |||
| 69 | struct CTMemoryLoad { | ||
| 70 | uint32_t file_offset; | ||
| 71 | uint32_t size; | ||
| 72 | uint32_t physical_address; | ||
| 73 | uint32_t pad; | ||
| 74 | }; | ||
| 75 | |||
| 76 | struct CTRegisterWrite { | ||
| 77 | uint32_t physical_address; | ||
| 78 | |||
| 79 | enum : uint32_t { | ||
| 80 | SIZE_8 = 0xD1, | ||
| 81 | SIZE_16 = 0xD2, | ||
| 82 | SIZE_32 = 0xD3, | ||
| 83 | SIZE_64 = 0xD4 | ||
| 84 | } size; | ||
| 85 | |||
| 86 | // TODO: Make it clearer which bits of this member are used for sizes other than 32 bits | ||
| 87 | uint64_t value; | ||
| 88 | }; | ||
| 89 | |||
| 90 | struct CTStreamElement { | ||
| 91 | CTStreamElementType type; | ||
| 92 | |||
| 93 | union { | ||
| 94 | CTMemoryLoad memory_load; | ||
| 95 | CTRegisterWrite register_write; | ||
| 96 | }; | ||
| 97 | }; | ||
| 98 | |||
| 99 | #pragma pack() | ||
| 100 | |||
| 101 | } | ||
diff --git a/src/core/tracer/recorder.cpp b/src/core/tracer/recorder.cpp new file mode 100644 index 000000000..656706c0c --- /dev/null +++ b/src/core/tracer/recorder.cpp | |||
| @@ -0,0 +1,187 @@ | |||
| 1 | // Copyright 2015 Citra Emulator Project | ||
| 2 | // Licensed under GPLv2 or any later version | ||
| 3 | // Refer to the license.txt file included. | ||
| 4 | |||
| 5 | #include <cstring> | ||
| 6 | |||
| 7 | #include "common/assert.h" | ||
| 8 | #include "common/file_util.h" | ||
| 9 | #include "common/logging/log.h" | ||
| 10 | |||
| 11 | #include "recorder.h" | ||
| 12 | |||
| 13 | namespace CiTrace { | ||
| 14 | |||
| 15 | Recorder::Recorder(const InitialState& initial_state) : initial_state(initial_state) { | ||
| 16 | |||
| 17 | } | ||
| 18 | |||
| 19 | void Recorder::Finish(const std::string& filename) { | ||
| 20 | // Setup CiTrace header | ||
| 21 | CTHeader header; | ||
| 22 | std::memcpy(header.magic, CTHeader::ExpectedMagicWord(), 4); | ||
| 23 | header.version = CTHeader::ExpectedVersion(); | ||
| 24 | header.header_size = sizeof(CTHeader); | ||
| 25 | |||
| 26 | // Calculate file offsets | ||
| 27 | auto& initial = header.initial_state_offsets; | ||
| 28 | |||
| 29 | initial.gpu_registers_size = initial_state.gpu_registers.size(); | ||
| 30 | initial.lcd_registers_size = initial_state.lcd_registers.size(); | ||
| 31 | initial.pica_registers_size = initial_state.pica_registers.size(); | ||
| 32 | initial.default_attributes_size = initial_state.default_attributes.size(); | ||
| 33 | initial.vs_program_binary_size = initial_state.vs_program_binary.size(); | ||
| 34 | initial.vs_swizzle_data_size = initial_state.vs_swizzle_data.size(); | ||
| 35 | initial.vs_float_uniforms_size = initial_state.vs_float_uniforms.size(); | ||
| 36 | initial.gs_program_binary_size = initial_state.gs_program_binary.size(); | ||
| 37 | initial.gs_swizzle_data_size = initial_state.gs_swizzle_data.size(); | ||
| 38 | initial.gs_float_uniforms_size = initial_state.gs_float_uniforms.size(); | ||
| 39 | header.stream_size = stream.size(); | ||
| 40 | |||
| 41 | initial.gpu_registers = sizeof(header); | ||
| 42 | initial.lcd_registers = initial.gpu_registers + initial.gpu_registers_size * sizeof(u32); | ||
| 43 | initial.pica_registers = initial.lcd_registers + initial.lcd_registers_size * sizeof(u32);; | ||
| 44 | initial.default_attributes = initial.pica_registers + initial.pica_registers_size * sizeof(u32); | ||
| 45 | initial.vs_program_binary = initial.default_attributes + initial.default_attributes_size * sizeof(u32); | ||
| 46 | initial.vs_swizzle_data = initial.vs_program_binary + initial.vs_program_binary_size * sizeof(u32); | ||
| 47 | initial.vs_float_uniforms = initial.vs_swizzle_data + initial.vs_swizzle_data_size * sizeof(u32); | ||
| 48 | initial.gs_program_binary = initial.vs_float_uniforms + initial.vs_float_uniforms_size * sizeof(u32); | ||
| 49 | initial.gs_swizzle_data = initial.gs_program_binary + initial.gs_program_binary_size * sizeof(u32); | ||
| 50 | initial.gs_float_uniforms = initial.gs_swizzle_data + initial.gs_swizzle_data_size * sizeof(u32); | ||
| 51 | header.stream_offset = initial.gs_float_uniforms + initial.gs_float_uniforms_size * sizeof(u32); | ||
| 52 | |||
| 53 | // Iterate through stream elements, update relevant stream element data | ||
| 54 | for (auto& stream_element : stream) { | ||
| 55 | switch (stream_element.data.type) { | ||
| 56 | case MemoryLoad: | ||
| 57 | { | ||
| 58 | auto& file_offset = memory_regions[stream_element.hash]; | ||
| 59 | if (!stream_element.uses_existing_data) { | ||
| 60 | file_offset = header.stream_offset; | ||
| 61 | } | ||
| 62 | stream_element.data.memory_load.file_offset = file_offset; | ||
| 63 | break; | ||
| 64 | } | ||
| 65 | |||
| 66 | default: | ||
| 67 | // Other commands don't use any extra data | ||
| 68 | DEBUG_ASSERT(stream_element.extra_data.size() == 0); | ||
| 69 | break; | ||
| 70 | } | ||
| 71 | header.stream_offset += stream_element.extra_data.size(); | ||
| 72 | } | ||
| 73 | |||
| 74 | try { | ||
| 75 | // Open file and write header | ||
| 76 | FileUtil::IOFile file(filename, "wb"); | ||
| 77 | size_t written = file.WriteObject(header); | ||
| 78 | if (written != 1 || file.Tell() != initial.gpu_registers) | ||
| 79 | throw "Failed to write header"; | ||
| 80 | |||
| 81 | // Write initial state | ||
| 82 | written = file.WriteArray(initial_state.gpu_registers.data(), initial_state.gpu_registers.size()); | ||
| 83 | if (written != initial_state.gpu_registers.size() || file.Tell() != initial.lcd_registers) | ||
| 84 | throw "Failed to write GPU registers"; | ||
| 85 | |||
| 86 | written = file.WriteArray(initial_state.lcd_registers.data(), initial_state.lcd_registers.size()); | ||
| 87 | if (written != initial_state.lcd_registers.size() || file.Tell() != initial.pica_registers) | ||
| 88 | throw "Failed to write LCD registers"; | ||
| 89 | |||
| 90 | written = file.WriteArray(initial_state.pica_registers.data(), initial_state.pica_registers.size()); | ||
| 91 | if (written != initial_state.pica_registers.size() || file.Tell() != initial.default_attributes) | ||
| 92 | throw "Failed to write Pica registers"; | ||
| 93 | |||
| 94 | written = file.WriteArray(initial_state.default_attributes.data(), initial_state.default_attributes.size()); | ||
| 95 | if (written != initial_state.default_attributes.size() || file.Tell() != initial.vs_program_binary) | ||
| 96 | throw "Failed to write default vertex attributes"; | ||
| 97 | |||
| 98 | written = file.WriteArray(initial_state.vs_program_binary.data(), initial_state.vs_program_binary.size()); | ||
| 99 | if (written != initial_state.vs_program_binary.size() || file.Tell() != initial.vs_swizzle_data) | ||
| 100 | throw "Failed to write vertex shader program binary"; | ||
| 101 | |||
| 102 | written = file.WriteArray(initial_state.vs_swizzle_data.data(), initial_state.vs_swizzle_data.size()); | ||
| 103 | if (written != initial_state.vs_swizzle_data.size() || file.Tell() != initial.vs_float_uniforms) | ||
| 104 | throw "Failed to write vertex shader swizzle data"; | ||
| 105 | |||
| 106 | written = file.WriteArray(initial_state.vs_float_uniforms.data(), initial_state.vs_float_uniforms.size()); | ||
| 107 | if (written != initial_state.vs_float_uniforms.size() || file.Tell() != initial.gs_program_binary) | ||
| 108 | throw "Failed to write vertex shader float uniforms"; | ||
| 109 | |||
| 110 | written = file.WriteArray(initial_state.gs_program_binary.data(), initial_state.gs_program_binary.size()); | ||
| 111 | if (written != initial_state.gs_program_binary.size() || file.Tell() != initial.gs_swizzle_data) | ||
| 112 | throw "Failed to write geomtry shader program binary"; | ||
| 113 | |||
| 114 | written = file.WriteArray(initial_state.gs_swizzle_data.data(), initial_state.gs_swizzle_data.size()); | ||
| 115 | if (written != initial_state.gs_swizzle_data.size() || file.Tell() != initial.gs_float_uniforms) | ||
| 116 | throw "Failed to write geometry shader swizzle data"; | ||
| 117 | |||
| 118 | written = file.WriteArray(initial_state.gs_float_uniforms.data(), initial_state.gs_float_uniforms.size()); | ||
| 119 | if (written != initial_state.gs_float_uniforms.size() || file.Tell() != initial.gs_float_uniforms + sizeof(u32) * initial.gs_float_uniforms_size) | ||
| 120 | throw "Failed to write geometry shader float uniforms"; | ||
| 121 | |||
| 122 | // Iterate through stream elements, write "extra data" | ||
| 123 | for (const auto& stream_element : stream) { | ||
| 124 | if (stream_element.extra_data.size() == 0) | ||
| 125 | continue; | ||
| 126 | |||
| 127 | written = file.WriteBytes(stream_element.extra_data.data(), stream_element.extra_data.size()); | ||
| 128 | if (written != stream_element.extra_data.size()) | ||
| 129 | throw "Failed to write extra data"; | ||
| 130 | } | ||
| 131 | |||
| 132 | if (file.Tell() != header.stream_offset) | ||
| 133 | throw "Unexpected end of extra data"; | ||
| 134 | |||
| 135 | // Write actual stream elements | ||
| 136 | for (const auto& stream_element : stream) { | ||
| 137 | if (1 != file.WriteObject(stream_element.data)) | ||
| 138 | throw "Failed to write stream element"; | ||
| 139 | } | ||
| 140 | } catch(const char* str) { | ||
| 141 | LOG_ERROR(HW_GPU, "Writing CiTrace file failed: %s", str); | ||
| 142 | } | ||
| 143 | } | ||
| 144 | |||
| 145 | void Recorder::FrameFinished() { | ||
| 146 | stream.push_back( { FrameMarker } ); | ||
| 147 | } | ||
| 148 | |||
| 149 | void Recorder::MemoryAccessed(const u8* data, u32 size, u32 physical_address) { | ||
| 150 | StreamElement element = { MemoryLoad }; | ||
| 151 | element.data.memory_load.size = size; | ||
| 152 | element.data.memory_load.physical_address = physical_address; | ||
| 153 | |||
| 154 | // Compute hash over given memory region to check if the contents are already stored internally | ||
| 155 | boost::crc_32_type result; | ||
| 156 | result.process_bytes(data, size); | ||
| 157 | element.hash = result.checksum(); | ||
| 158 | |||
| 159 | element.uses_existing_data = (memory_regions.find(element.hash) != memory_regions.end()); | ||
| 160 | if (!element.uses_existing_data) { | ||
| 161 | element.extra_data.resize(size); | ||
| 162 | memcpy(element.extra_data.data(), data, size); | ||
| 163 | memory_regions.insert({element.hash, 0}); // file offset will be initialized in Finish() | ||
| 164 | } | ||
| 165 | |||
| 166 | stream.push_back(element); | ||
| 167 | } | ||
| 168 | |||
| 169 | template<typename T> | ||
| 170 | void Recorder::RegisterWritten(u32 physical_address, T value) { | ||
| 171 | StreamElement element = { RegisterWrite }; | ||
| 172 | element.data.register_write.size = (sizeof(T) == 1) ? CTRegisterWrite::SIZE_8 | ||
| 173 | : (sizeof(T) == 2) ? CTRegisterWrite::SIZE_16 | ||
| 174 | : (sizeof(T) == 4) ? CTRegisterWrite::SIZE_32 | ||
| 175 | : CTRegisterWrite::SIZE_64; | ||
| 176 | element.data.register_write.physical_address = physical_address; | ||
| 177 | element.data.register_write.value = value; | ||
| 178 | |||
| 179 | stream.push_back(element); | ||
| 180 | } | ||
| 181 | |||
| 182 | template void Recorder::RegisterWritten(u32,u8); | ||
| 183 | template void Recorder::RegisterWritten(u32,u16); | ||
| 184 | template void Recorder::RegisterWritten(u32,u32); | ||
| 185 | template void Recorder::RegisterWritten(u32,u64); | ||
| 186 | |||
| 187 | } | ||
diff --git a/src/core/tracer/recorder.h b/src/core/tracer/recorder.h new file mode 100644 index 000000000..6e4b70015 --- /dev/null +++ b/src/core/tracer/recorder.h | |||
| @@ -0,0 +1,90 @@ | |||
| 1 | // Copyright 2015 Citra Emulator Project | ||
| 2 | // Licensed under GPLv2 or any later version | ||
| 3 | // Refer to the license.txt file included. | ||
| 4 | |||
| 5 | #pragma once | ||
| 6 | |||
| 7 | #include <unordered_map> | ||
| 8 | #include <vector> | ||
| 9 | |||
| 10 | #include <boost/crc.hpp> | ||
| 11 | |||
| 12 | #include "common/common_types.h" | ||
| 13 | |||
| 14 | #include "citrace.h" | ||
| 15 | |||
| 16 | namespace CiTrace { | ||
| 17 | |||
| 18 | class Recorder { | ||
| 19 | public: | ||
| 20 | struct InitialState { | ||
| 21 | std::vector<u32> gpu_registers; | ||
| 22 | std::vector<u32> lcd_registers; | ||
| 23 | std::vector<u32> pica_registers; | ||
| 24 | std::vector<u32> default_attributes; | ||
| 25 | std::vector<u32> vs_program_binary; | ||
| 26 | std::vector<u32> vs_swizzle_data; | ||
| 27 | std::vector<u32> vs_float_uniforms; | ||
| 28 | std::vector<u32> gs_program_binary; | ||
| 29 | std::vector<u32> gs_swizzle_data; | ||
| 30 | std::vector<u32> gs_float_uniforms; | ||
| 31 | }; | ||
| 32 | |||
| 33 | /** | ||
| 34 | * Recorder constructor | ||
| 35 | * @param default_attributes Pointer to an array of 32-bit-aligned 24-bit floating point values. | ||
| 36 | * @param vs_float_uniforms Pointer to an array of 32-bit-aligned 24-bit floating point values. | ||
| 37 | */ | ||
| 38 | Recorder(const InitialState& initial_state); | ||
| 39 | |||
| 40 | /// Finish recording of this Citrace and save it using the given filename. | ||
| 41 | void Finish(const std::string& filename); | ||
| 42 | |||
| 43 | /// Mark end of a frame | ||
| 44 | void FrameFinished(); | ||
| 45 | |||
| 46 | /** | ||
| 47 | * Store a copy of the given memory range in the recording. | ||
| 48 | * @note Use this whenever the GPU is about to access a particular memory region. | ||
| 49 | * @note The implementation will make sure to minimize redundant memory updates. | ||
| 50 | */ | ||
| 51 | void MemoryAccessed(const u8* data, u32 size, u32 physical_address); | ||
| 52 | |||
| 53 | /** | ||
| 54 | * Record a register write. | ||
| 55 | * @note Use this whenever a GPU-related MMIO register has been written to. | ||
| 56 | */ | ||
| 57 | template<typename T> | ||
| 58 | void RegisterWritten(u32 physical_address, T value); | ||
| 59 | |||
| 60 | private: | ||
| 61 | // Initial state of recording start | ||
| 62 | InitialState initial_state; | ||
| 63 | |||
| 64 | // Command stream | ||
| 65 | struct StreamElement { | ||
| 66 | CTStreamElement data; | ||
| 67 | |||
| 68 | /** | ||
| 69 | * Extra data to store along "core" data. | ||
| 70 | * This is e.g. used for data used in MemoryUpdates. | ||
| 71 | */ | ||
| 72 | std::vector<u8> extra_data; | ||
| 73 | |||
| 74 | /// Optional CRC hash (e.g. for hashing memory regions) | ||
| 75 | boost::crc_32_type::value_type hash; | ||
| 76 | |||
| 77 | /// If true, refer to data already written to the output file instead of extra_data | ||
| 78 | bool uses_existing_data; | ||
| 79 | }; | ||
| 80 | |||
| 81 | std::vector<StreamElement> stream; | ||
| 82 | |||
| 83 | /** | ||
| 84 | * Internal cache which maps hashes of memory contents to file offsets at which those memory | ||
| 85 | * contents are stored. | ||
| 86 | */ | ||
| 87 | std::unordered_map<boost::crc_32_type::value_type /*hash*/, u32 /*file_offset*/> memory_regions; | ||
| 88 | }; | ||
| 89 | |||
| 90 | } // namespace | ||