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authorGravatar bunnei2014-04-01 18:18:52 -0400
committerGravatar bunnei2014-04-01 18:48:06 -0400
commit4860480c365710a0a788d3853558726c1ee28c82 (patch)
treee86ca5ed5e7ed44eca1b49c1af85346ed6ad1077 /src/core
parent-converted tabs to spaces (diff)
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Diffstat (limited to 'src/core')
-rw-r--r--src/core/src/arm/arm_regformat.h188
-rw-r--r--src/core/src/arm/armcpu.h72
-rw-r--r--src/core/src/arm/armdefs.h550
-rw-r--r--src/core/src/arm/armemu.cpp10884
-rw-r--r--src/core/src/arm/mmu/arm1176jzf_s_mmu.cpp1620
-rw-r--r--src/core/src/arm/mmu/arm1176jzf_s_mmu.h10
-rw-r--r--src/core/src/arm/mmu/cache.h116
-rw-r--r--src/core/src/arm/mmu/rb.h34
-rw-r--r--src/core/src/arm/mmu/tlb.h74
-rw-r--r--src/core/src/arm/mmu/wb.h44
10 files changed, 6796 insertions, 6796 deletions
diff --git a/src/core/src/arm/arm_regformat.h b/src/core/src/arm/arm_regformat.h
index c7d6a87e0..0ca62780b 100644
--- a/src/core/src/arm/arm_regformat.h
+++ b/src/core/src/arm/arm_regformat.h
@@ -2,101 +2,101 @@
2#define __ARM_REGFORMAT_H__ 2#define __ARM_REGFORMAT_H__
3 3
4enum arm_regno{ 4enum arm_regno{
5 R0 = 0, 5 R0 = 0,
6 R1, 6 R1,
7 R2, 7 R2,
8 R3, 8 R3,
9 R4, 9 R4,
10 R5, 10 R5,
11 R6, 11 R6,
12 R7, 12 R7,
13 R8, 13 R8,
14 R9, 14 R9,
15 R10, 15 R10,
16 R11, 16 R11,
17 R12, 17 R12,
18 R13, 18 R13,
19 LR, 19 LR,
20 R15, //PC, 20 R15, //PC,
21 CPSR_REG, 21 CPSR_REG,
22 SPSR_REG, 22 SPSR_REG,
23#if 1 23#if 1
24 PHYS_PC, 24 PHYS_PC,
25 R13_USR, 25 R13_USR,
26 R14_USR, 26 R14_USR,
27 R13_SVC, 27 R13_SVC,
28 R14_SVC, 28 R14_SVC,
29 R13_ABORT, 29 R13_ABORT,
30 R14_ABORT, 30 R14_ABORT,
31 R13_UNDEF, 31 R13_UNDEF,
32 R14_UNDEF, 32 R14_UNDEF,
33 R13_IRQ, 33 R13_IRQ,
34 R14_IRQ, 34 R14_IRQ,
35 R8_FIRQ, 35 R8_FIRQ,
36 R9_FIRQ, 36 R9_FIRQ,
37 R10_FIRQ, 37 R10_FIRQ,
38 R11_FIRQ, 38 R11_FIRQ,
39 R12_FIRQ, 39 R12_FIRQ,
40 R13_FIRQ, 40 R13_FIRQ,
41 R14_FIRQ, 41 R14_FIRQ,
42 SPSR_INVALID1, 42 SPSR_INVALID1,
43 SPSR_INVALID2, 43 SPSR_INVALID2,
44 SPSR_SVC, 44 SPSR_SVC,
45 SPSR_ABORT, 45 SPSR_ABORT,
46 SPSR_UNDEF, 46 SPSR_UNDEF,
47 SPSR_IRQ, 47 SPSR_IRQ,
48 SPSR_FIRQ, 48 SPSR_FIRQ,
49 MODE_REG, /* That is the cpsr[4 : 0], just for calculation easily */ 49 MODE_REG, /* That is the cpsr[4 : 0], just for calculation easily */
50 BANK_REG, 50 BANK_REG,
51 EXCLUSIVE_TAG, 51 EXCLUSIVE_TAG,
52 EXCLUSIVE_STATE, 52 EXCLUSIVE_STATE,
53 EXCLUSIVE_RESULT, 53 EXCLUSIVE_RESULT,
54 CP15_BASE, 54 CP15_BASE,
55 CP15_C0 = CP15_BASE, 55 CP15_C0 = CP15_BASE,
56 CP15_C0_C0 = CP15_C0, 56 CP15_C0_C0 = CP15_C0,
57 CP15_MAIN_ID = CP15_C0_C0, 57 CP15_MAIN_ID = CP15_C0_C0,
58 CP15_CACHE_TYPE, 58 CP15_CACHE_TYPE,
59 CP15_TCM_STATUS, 59 CP15_TCM_STATUS,
60 CP15_TLB_TYPE, 60 CP15_TLB_TYPE,
61 CP15_C0_C1, 61 CP15_C0_C1,
62 CP15_PROCESSOR_FEATURE_0 = CP15_C0_C1, 62 CP15_PROCESSOR_FEATURE_0 = CP15_C0_C1,
63 CP15_PROCESSOR_FEATURE_1, 63 CP15_PROCESSOR_FEATURE_1,
64 CP15_DEBUG_FEATURE_0, 64 CP15_DEBUG_FEATURE_0,
65 CP15_AUXILIARY_FEATURE_0, 65 CP15_AUXILIARY_FEATURE_0,
66 CP15_C1_C0, 66 CP15_C1_C0,
67 CP15_CONTROL = CP15_C1_C0, 67 CP15_CONTROL = CP15_C1_C0,
68 CP15_AUXILIARY_CONTROL, 68 CP15_AUXILIARY_CONTROL,
69 CP15_COPROCESSOR_ACCESS_CONTROL, 69 CP15_COPROCESSOR_ACCESS_CONTROL,
70 CP15_C2, 70 CP15_C2,
71 CP15_C2_C0 = CP15_C2, 71 CP15_C2_C0 = CP15_C2,
72 CP15_TRANSLATION_BASE = CP15_C2_C0, 72 CP15_TRANSLATION_BASE = CP15_C2_C0,
73 CP15_TRANSLATION_BASE_TABLE_0 = CP15_TRANSLATION_BASE, 73 CP15_TRANSLATION_BASE_TABLE_0 = CP15_TRANSLATION_BASE,
74 CP15_TRANSLATION_BASE_TABLE_1, 74 CP15_TRANSLATION_BASE_TABLE_1,
75 CP15_TRANSLATION_BASE_CONTROL, 75 CP15_TRANSLATION_BASE_CONTROL,
76 CP15_DOMAIN_ACCESS_CONTROL, 76 CP15_DOMAIN_ACCESS_CONTROL,
77 CP15_RESERVED, 77 CP15_RESERVED,
78 /* Fault status */ 78 /* Fault status */
79 CP15_FAULT_STATUS, 79 CP15_FAULT_STATUS,
80 CP15_INSTR_FAULT_STATUS, 80 CP15_INSTR_FAULT_STATUS,
81 CP15_COMBINED_DATA_FSR = CP15_FAULT_STATUS, 81 CP15_COMBINED_DATA_FSR = CP15_FAULT_STATUS,
82 CP15_INST_FSR, 82 CP15_INST_FSR,
83 /* Fault Address register */ 83 /* Fault Address register */
84 CP15_FAULT_ADDRESS, 84 CP15_FAULT_ADDRESS,
85 CP15_COMBINED_DATA_FAR = CP15_FAULT_ADDRESS, 85 CP15_COMBINED_DATA_FAR = CP15_FAULT_ADDRESS,
86 CP15_WFAR, 86 CP15_WFAR,
87 CP15_IFAR, 87 CP15_IFAR,
88 CP15_PID, 88 CP15_PID,
89 CP15_CONTEXT_ID, 89 CP15_CONTEXT_ID,
90 CP15_THREAD_URO, 90 CP15_THREAD_URO,
91 CP15_TLB_FAULT_ADDR, /* defined by SkyEye */ 91 CP15_TLB_FAULT_ADDR, /* defined by SkyEye */
92 CP15_TLB_FAULT_STATUS, /* defined by SkyEye */ 92 CP15_TLB_FAULT_STATUS, /* defined by SkyEye */
93 /* VFP registers */ 93 /* VFP registers */
94 VFP_BASE, 94 VFP_BASE,
95 VFP_FPSID = VFP_BASE, 95 VFP_FPSID = VFP_BASE,
96 VFP_FPSCR, 96 VFP_FPSCR,
97 VFP_FPEXC, 97 VFP_FPEXC,
98#endif 98#endif
99 MAX_REG_NUM, 99 MAX_REG_NUM,
100}; 100};
101 101
102#define VFP_OFFSET(x) (x - VFP_BASE) 102#define VFP_OFFSET(x) (x - VFP_BASE)
diff --git a/src/core/src/arm/armcpu.h b/src/core/src/arm/armcpu.h
index ee4a860dd..d7e336b94 100644
--- a/src/core/src/arm/armcpu.h
+++ b/src/core/src/arm/armcpu.h
@@ -1,21 +1,21 @@
1/* 1/*
2 * arm 2 * arm
3 * armcpu.h 3 * armcpu.h
4 * 4 *
5 * Copyright (C) 2003, 2004 Sebastian Biallas (sb@biallas.net) 5 * Copyright (C) 2003, 2004 Sebastian Biallas (sb@biallas.net)
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 * 10 *
11 * This program is distributed in the hope that it will be useful, 11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 * 15 *
16 * You should have received a copy of the GNU General Public License 16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software 17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */ 19 */
20 20
21#ifndef __ARM_CPU_H__ 21#ifndef __ARM_CPU_H__
@@ -32,19 +32,19 @@
32 32
33 33
34typedef struct ARM_CPU_State_s { 34typedef struct ARM_CPU_State_s {
35 ARMul_State * core; 35 ARMul_State * core;
36 uint32_t core_num; 36 uint32_t core_num;
37 /* The core id that boot from 37 /* The core id that boot from
38 */ 38 */
39 uint32_t boot_core_id; 39 uint32_t boot_core_id;
40}ARM_CPU_State; 40}ARM_CPU_State;
41 41
42//static ARM_CPU_State* get_current_cpu(){ 42//static ARM_CPU_State* get_current_cpu(){
43// machine_config_t* mach = get_current_mach(); 43// machine_config_t* mach = get_current_mach();
44// /* Casting a conf_obj_t to ARM_CPU_State type */ 44// /* Casting a conf_obj_t to ARM_CPU_State type */
45// ARM_CPU_State* cpu = (ARM_CPU_State*)mach->cpu_data->obj; 45// ARM_CPU_State* cpu = (ARM_CPU_State*)mach->cpu_data->obj;
46// 46//
47// return cpu; 47// return cpu;
48//} 48//}
49 49
50/** 50/**
@@ -53,8 +53,8 @@ typedef struct ARM_CPU_State_s {
53* @return 53* @return
54*/ 54*/
55//static ARMul_State* get_boot_core(){ 55//static ARMul_State* get_boot_core(){
56// ARM_CPU_State* cpu = get_current_cpu(); 56// ARM_CPU_State* cpu = get_current_cpu();
57// return &cpu->core[cpu->boot_core_id]; 57// return &cpu->core[cpu->boot_core_id];
58//} 58//}
59/** 59/**
60* @brief Get the instance of running core 60* @brief Get the instance of running core
@@ -62,19 +62,19 @@ typedef struct ARM_CPU_State_s {
62* @return the core instance 62* @return the core instance
63*/ 63*/
64//static ARMul_State* get_current_core(){ 64//static ARMul_State* get_current_core(){
65// /* Casting a conf_obj_t to ARM_CPU_State type */ 65// /* Casting a conf_obj_t to ARM_CPU_State type */
66// int id = Common::CurrentThreadId(); 66// int id = Common::CurrentThreadId();
67// /* If thread is not in running mode, we should give the boot core */ 67// /* If thread is not in running mode, we should give the boot core */
68// if(get_thread_state(id) != Running_state){ 68// if(get_thread_state(id) != Running_state){
69// return get_boot_core(); 69// return get_boot_core();
70// } 70// }
71// /* Judge if we are running in paralell or sequenial */ 71// /* Judge if we are running in paralell or sequenial */
72// if(thread_exist(id)){ 72// if(thread_exist(id)){
73// conf_object_t* conf_obj = get_current_exec_priv(id); 73// conf_object_t* conf_obj = get_current_exec_priv(id);
74// return (ARMul_State*)get_cast_conf_obj(conf_obj, "arm_core_t"); 74// return (ARMul_State*)get_cast_conf_obj(conf_obj, "arm_core_t");
75// } 75// }
76// 76//
77// return NULL; 77// return NULL;
78//} 78//}
79 79
80#define CURRENT_CORE get_current_core() 80#define CURRENT_CORE get_current_core()
diff --git a/src/core/src/arm/armdefs.h b/src/core/src/arm/armdefs.h
index 69cf790e4..0136a52d2 100644
--- a/src/core/src/arm/armdefs.h
+++ b/src/core/src/arm/armdefs.h
@@ -89,7 +89,7 @@
89#endif 89#endif
90 90
91//#define DBCT_TEST_SPEED 91//#define DBCT_TEST_SPEED
92#define DBCT_TEST_SPEED_SEC 10 92#define DBCT_TEST_SPEED_SEC 10
93//AJ2D-------------------------------------------------------------------------- 93//AJ2D--------------------------------------------------------------------------
94 94
95//teawater add compile switch for DBCT GDB RSP function 2005.10.21-------------- 95//teawater add compile switch for DBCT GDB RSP function 2005.10.21--------------
@@ -99,9 +99,9 @@
99//#include <skyeye_defs.h> 99//#include <skyeye_defs.h>
100//#include <skyeye_types.h> 100//#include <skyeye_types.h>
101 101
102#define ARM_BYTE_TYPE 0 102#define ARM_BYTE_TYPE 0
103#define ARM_HALFWORD_TYPE 1 103#define ARM_HALFWORD_TYPE 1
104#define ARM_WORD_TYPE 2 104#define ARM_WORD_TYPE 2
105 105
106//the define of cachetype 106//the define of cachetype
107#define NONCACHE 0 107#define NONCACHE 0
@@ -112,10 +112,10 @@
112typedef char *VoidStar; 112typedef char *VoidStar;
113#endif 113#endif
114 114
115typedef unsigned long long ARMdword; /* must be 64 bits wide */ 115typedef unsigned long long ARMdword; /* must be 64 bits wide */
116typedef unsigned int ARMword; /* must be 32 bits wide */ 116typedef unsigned int ARMword; /* must be 32 bits wide */
117typedef unsigned char ARMbyte; /* must be 8 bits wide */ 117typedef unsigned char ARMbyte; /* must be 8 bits wide */
118typedef unsigned short ARMhword; /* must be 16 bits wide */ 118typedef unsigned short ARMhword; /* must be 16 bits wide */
119typedef struct ARMul_State ARMul_State; 119typedef struct ARMul_State ARMul_State;
120typedef struct ARMul_io ARMul_io; 120typedef struct ARMul_io ARMul_io;
121typedef struct ARMul_Energy ARMul_Energy; 121typedef struct ARMul_Energy ARMul_Energy;
@@ -152,59 +152,59 @@ typedef unsigned long long uint64_t;
152typedef unsigned ARMul_CPInits (ARMul_State * state); 152typedef unsigned ARMul_CPInits (ARMul_State * state);
153typedef unsigned ARMul_CPExits (ARMul_State * state); 153typedef unsigned ARMul_CPExits (ARMul_State * state);
154typedef unsigned ARMul_LDCs (ARMul_State * state, unsigned type, 154typedef unsigned ARMul_LDCs (ARMul_State * state, unsigned type,
155 ARMword instr, ARMword value); 155 ARMword instr, ARMword value);
156typedef unsigned ARMul_STCs (ARMul_State * state, unsigned type, 156typedef unsigned ARMul_STCs (ARMul_State * state, unsigned type,
157 ARMword instr, ARMword * value); 157 ARMword instr, ARMword * value);
158typedef unsigned ARMul_MRCs (ARMul_State * state, unsigned type, 158typedef unsigned ARMul_MRCs (ARMul_State * state, unsigned type,
159 ARMword instr, ARMword * value); 159 ARMword instr, ARMword * value);
160typedef unsigned ARMul_MCRs (ARMul_State * state, unsigned type, 160typedef unsigned ARMul_MCRs (ARMul_State * state, unsigned type,
161 ARMword instr, ARMword value); 161 ARMword instr, ARMword value);
162typedef unsigned ARMul_MRRCs (ARMul_State * state, unsigned type, 162typedef unsigned ARMul_MRRCs (ARMul_State * state, unsigned type,
163 ARMword instr, ARMword * value1, ARMword * value2); 163 ARMword instr, ARMword * value1, ARMword * value2);
164typedef unsigned ARMul_MCRRs (ARMul_State * state, unsigned type, 164typedef unsigned ARMul_MCRRs (ARMul_State * state, unsigned type,
165 ARMword instr, ARMword value1, ARMword value2); 165 ARMword instr, ARMword value1, ARMword value2);
166typedef unsigned ARMul_CDPs (ARMul_State * state, unsigned type, 166typedef unsigned ARMul_CDPs (ARMul_State * state, unsigned type,
167 ARMword instr); 167 ARMword instr);
168typedef unsigned ARMul_CPReads (ARMul_State * state, unsigned reg, 168typedef unsigned ARMul_CPReads (ARMul_State * state, unsigned reg,
169 ARMword * value); 169 ARMword * value);
170typedef unsigned ARMul_CPWrites (ARMul_State * state, unsigned reg, 170typedef unsigned ARMul_CPWrites (ARMul_State * state, unsigned reg,
171 ARMword value); 171 ARMword value);
172 172
173 173
174//added by ksh,2004-3-5 174//added by ksh,2004-3-5
175struct ARMul_io 175struct ARMul_io
176{ 176{
177 ARMword *instr; //to display the current interrupt state 177 ARMword *instr; //to display the current interrupt state
178 ARMword *net_flag; //to judge if network is enabled 178 ARMword *net_flag; //to judge if network is enabled
179 ARMword *net_int; //netcard interrupt 179 ARMword *net_int; //netcard interrupt
180 180
181 //ywc,2004-04-01 181 //ywc,2004-04-01
182 ARMword *ts_int; 182 ARMword *ts_int;
183 ARMword *ts_is_enable; 183 ARMword *ts_is_enable;
184 ARMword *ts_addr_begin; 184 ARMword *ts_addr_begin;
185 ARMword *ts_addr_end; 185 ARMword *ts_addr_end;
186 ARMword *ts_buffer; 186 ARMword *ts_buffer;
187}; 187};
188 188
189/* added by ksh,2004-11-26,some energy profiling */ 189/* added by ksh,2004-11-26,some energy profiling */
190struct ARMul_Energy 190struct ARMul_Energy
191{ 191{
192 int energy_prof; /* <tktan> BUG200103282109 : for energy profiling */ 192 int energy_prof; /* <tktan> BUG200103282109 : for energy profiling */
193 int enable_func_energy; /* <tktan> BUG200105181702 */ 193 int enable_func_energy; /* <tktan> BUG200105181702 */
194 char *func_energy; 194 char *func_energy;
195 int func_display; /* <tktan> BUG200103311509 : for function call display */ 195 int func_display; /* <tktan> BUG200103311509 : for function call display */
196 int func_disp_start; /* <tktan> BUG200104191428 : to start func profiling */ 196 int func_disp_start; /* <tktan> BUG200104191428 : to start func profiling */
197 char *start_func; /* <tktan> BUG200104191428 */ 197 char *start_func; /* <tktan> BUG200104191428 */
198 198
199 FILE *outfile; /* <tktan> BUG200105201531 : direct console to file */ 199 FILE *outfile; /* <tktan> BUG200105201531 : direct console to file */
200 long long tcycle, pcycle; 200 long long tcycle, pcycle;
201 float t_energy; 201 float t_energy;
202 void *cur_task; /* <tktan> BUG200103291737 */ 202 void *cur_task; /* <tktan> BUG200103291737 */
203 long long t_mem_cycle, t_idle_cycle, t_uart_cycle; 203 long long t_mem_cycle, t_idle_cycle, t_uart_cycle;
204 long long p_mem_cycle, p_idle_cycle, p_uart_cycle; 204 long long p_mem_cycle, p_idle_cycle, p_uart_cycle;
205 long long p_io_update_tcycle; 205 long long p_io_update_tcycle;
206 /*record CCCR,to get current core frequency */ 206 /*record CCCR,to get current core frequency */
207 ARMword cccr; 207 ARMword cccr;
208}; 208};
209#if 0 209#if 0
210#define MAX_BANK 8 210#define MAX_BANK 8
@@ -212,119 +212,119 @@ struct ARMul_Energy
212 212
213typedef struct mem_bank 213typedef struct mem_bank
214{ 214{
215 ARMword (*read_byte) (ARMul_State * state, ARMword addr); 215 ARMword (*read_byte) (ARMul_State * state, ARMword addr);
216 void (*write_byte) (ARMul_State * state, ARMword addr, ARMword data); 216 void (*write_byte) (ARMul_State * state, ARMword addr, ARMword data);
217 ARMword (*read_halfword) (ARMul_State * state, ARMword addr); 217 ARMword (*read_halfword) (ARMul_State * state, ARMword addr);
218 void (*write_halfword) (ARMul_State * state, ARMword addr, 218 void (*write_halfword) (ARMul_State * state, ARMword addr,
219 ARMword data); 219 ARMword data);
220 ARMword (*read_word) (ARMul_State * state, ARMword addr); 220 ARMword (*read_word) (ARMul_State * state, ARMword addr);
221 void (*write_word) (ARMul_State * state, ARMword addr, ARMword data); 221 void (*write_word) (ARMul_State * state, ARMword addr, ARMword data);
222 unsigned int addr, len; 222 unsigned int addr, len;
223 char filename[MAX_STR]; 223 char filename[MAX_STR];
224 unsigned type; //chy 2003-09-21: maybe io,ram,rom 224 unsigned type; //chy 2003-09-21: maybe io,ram,rom
225} mem_bank_t; 225} mem_bank_t;
226typedef struct 226typedef struct
227{ 227{
228 int bank_num; 228 int bank_num;
229 int current_num; /*current num of bank */ 229 int current_num; /*current num of bank */
230 mem_bank_t mem_banks[MAX_BANK]; 230 mem_bank_t mem_banks[MAX_BANK];
231} mem_config_t; 231} mem_config_t;
232#endif 232#endif
233#define VFP_REG_NUM 64 233#define VFP_REG_NUM 64
234struct ARMul_State 234struct ARMul_State
235{ 235{
236 ARMword Emulate; /* to start and stop emulation */ 236 ARMword Emulate; /* to start and stop emulation */
237 unsigned EndCondition; /* reason for stopping */ 237 unsigned EndCondition; /* reason for stopping */
238 unsigned ErrorCode; /* type of illegal instruction */ 238 unsigned ErrorCode; /* type of illegal instruction */
239 239
240 /* Order of the following register should not be modified */ 240 /* Order of the following register should not be modified */
241 ARMword Reg[16]; /* the current register file */ 241 ARMword Reg[16]; /* the current register file */
242 ARMword Cpsr; /* the current psr */ 242 ARMword Cpsr; /* the current psr */
243 ARMword Spsr_copy; 243 ARMword Spsr_copy;
244 ARMword phys_pc; 244 ARMword phys_pc;
245 ARMword Reg_usr[2]; 245 ARMword Reg_usr[2];
246 ARMword Reg_svc[2]; /* R13_SVC R14_SVC */ 246 ARMword Reg_svc[2]; /* R13_SVC R14_SVC */
247 ARMword Reg_abort[2]; /* R13_ABORT R14_ABORT */ 247 ARMword Reg_abort[2]; /* R13_ABORT R14_ABORT */
248 ARMword Reg_undef[2]; /* R13 UNDEF R14 UNDEF */ 248 ARMword Reg_undef[2]; /* R13 UNDEF R14 UNDEF */
249 ARMword Reg_irq[2]; /* R13_IRQ R14_IRQ */ 249 ARMword Reg_irq[2]; /* R13_IRQ R14_IRQ */
250 ARMword Reg_firq[7]; /* R8---R14 FIRQ */ 250 ARMword Reg_firq[7]; /* R8---R14 FIRQ */
251 ARMword Spsr[7]; /* the exception psr's */ 251 ARMword Spsr[7]; /* the exception psr's */
252 ARMword Mode; /* the current mode */ 252 ARMword Mode; /* the current mode */
253 ARMword Bank; /* the current register bank */ 253 ARMword Bank; /* the current register bank */
254 ARMword exclusive_tag; 254 ARMword exclusive_tag;
255 ARMword exclusive_state; 255 ARMword exclusive_state;
256 ARMword exclusive_result; 256 ARMword exclusive_result;
257 ARMword CP15[VFP_BASE - CP15_BASE]; 257 ARMword CP15[VFP_BASE - CP15_BASE];
258 ARMword VFP[3]; /* FPSID, FPSCR, and FPEXC */ 258 ARMword VFP[3]; /* FPSID, FPSCR, and FPEXC */
259 /* VFPv2 and VFPv3-D16 has 16 doubleword registers (D0-D16 or S0-S31). 259 /* VFPv2 and VFPv3-D16 has 16 doubleword registers (D0-D16 or S0-S31).
260 VFPv3-D32/ASIMD may have up to 32 doubleword registers (D0-D31), 260 VFPv3-D32/ASIMD may have up to 32 doubleword registers (D0-D31),
261 and only 32 singleword registers are accessible (S0-S31). */ 261 and only 32 singleword registers are accessible (S0-S31). */
262 ARMword ExtReg[VFP_REG_NUM]; 262 ARMword ExtReg[VFP_REG_NUM];
263 /* ---- End of the ordered registers ---- */ 263 /* ---- End of the ordered registers ---- */
264 264
265 ARMword RegBank[7][16]; /* all the registers */ 265 ARMword RegBank[7][16]; /* all the registers */
266 //chy:2003-08-19, used in arm xscale 266 //chy:2003-08-19, used in arm xscale
267 /* 40 bit accumulator. We always keep this 64 bits wide, 267 /* 40 bit accumulator. We always keep this 64 bits wide,
268 and move only 40 bits out of it in an MRA insn. */ 268 and move only 40 bits out of it in an MRA insn. */
269 ARMdword Accumulator; 269 ARMdword Accumulator;
270 270
271 ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; /* dummy flags for speed */ 271 ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; /* dummy flags for speed */
272 unsigned long long int icounter, debug_icounter, kernel_icounter; 272 unsigned long long int icounter, debug_icounter, kernel_icounter;
273 unsigned int shifter_carry_out; 273 unsigned int shifter_carry_out;
274 //ARMword translate_pc; 274 //ARMword translate_pc;
275 275
276 /* add armv6 flags dyf:2010-08-09 */ 276 /* add armv6 flags dyf:2010-08-09 */
277 ARMword GEFlag, EFlag, AFlag, QFlags; 277 ARMword GEFlag, EFlag, AFlag, QFlags;
278 //chy:2003-08-19, used in arm v5e|xscale 278 //chy:2003-08-19, used in arm v5e|xscale
279 ARMword SFlag; 279 ARMword SFlag;
280#ifdef MODET 280#ifdef MODET
281 ARMword TFlag; /* Thumb state */ 281 ARMword TFlag; /* Thumb state */
282#endif 282#endif
283 ARMword instr, pc, temp; /* saved register state */ 283 ARMword instr, pc, temp; /* saved register state */
284 ARMword loaded, decoded; /* saved pipeline state */ 284 ARMword loaded, decoded; /* saved pipeline state */
285 //chy 2006-04-12 for ICE breakpoint 285 //chy 2006-04-12 for ICE breakpoint
286 ARMword loaded_addr, decoded_addr; /* saved pipeline state addr*/ 286 ARMword loaded_addr, decoded_addr; /* saved pipeline state addr*/
287 unsigned int NumScycles, NumNcycles, NumIcycles, NumCcycles, NumFcycles; /* emulated cycles used */ 287 unsigned int NumScycles, NumNcycles, NumIcycles, NumCcycles, NumFcycles; /* emulated cycles used */
288 unsigned long long NumInstrs; /* the number of instructions executed */ 288 unsigned long long NumInstrs; /* the number of instructions executed */
289 unsigned NextInstr; 289 unsigned NextInstr;
290 unsigned VectorCatch; /* caught exception mask */ 290 unsigned VectorCatch; /* caught exception mask */
291 unsigned CallDebug; /* set to call the debugger */ 291 unsigned CallDebug; /* set to call the debugger */
292 unsigned CanWatch; /* set by memory interface if its willing to suffer the 292 unsigned CanWatch; /* set by memory interface if its willing to suffer the
293 overhead of checking for watchpoints on each memory 293 overhead of checking for watchpoints on each memory
294 access */ 294 access */
295 unsigned int StopHandle; 295 unsigned int StopHandle;
296 296
297 char *CommandLine; /* Command Line from ARMsd */ 297 char *CommandLine; /* Command Line from ARMsd */
298 298
299 ARMul_CPInits *CPInit[16]; /* coprocessor initialisers */ 299 ARMul_CPInits *CPInit[16]; /* coprocessor initialisers */
300 ARMul_CPExits *CPExit[16]; /* coprocessor finalisers */ 300 ARMul_CPExits *CPExit[16]; /* coprocessor finalisers */
301 ARMul_LDCs *LDC[16]; /* LDC instruction */ 301 ARMul_LDCs *LDC[16]; /* LDC instruction */
302 ARMul_STCs *STC[16]; /* STC instruction */ 302 ARMul_STCs *STC[16]; /* STC instruction */
303 ARMul_MRCs *MRC[16]; /* MRC instruction */ 303 ARMul_MRCs *MRC[16]; /* MRC instruction */
304 ARMul_MCRs *MCR[16]; /* MCR instruction */ 304 ARMul_MCRs *MCR[16]; /* MCR instruction */
305 ARMul_MRRCs *MRRC[16]; /* MRRC instruction */ 305 ARMul_MRRCs *MRRC[16]; /* MRRC instruction */
306 ARMul_MCRRs *MCRR[16]; /* MCRR instruction */ 306 ARMul_MCRRs *MCRR[16]; /* MCRR instruction */
307 ARMul_CDPs *CDP[16]; /* CDP instruction */ 307 ARMul_CDPs *CDP[16]; /* CDP instruction */
308 ARMul_CPReads *CPRead[16]; /* Read CP register */ 308 ARMul_CPReads *CPRead[16]; /* Read CP register */
309 ARMul_CPWrites *CPWrite[16]; /* Write CP register */ 309 ARMul_CPWrites *CPWrite[16]; /* Write CP register */
310 unsigned char *CPData[16]; /* Coprocessor data */ 310 unsigned char *CPData[16]; /* Coprocessor data */
311 unsigned char const *CPRegWords[16]; /* map of coprocessor register sizes */ 311 unsigned char const *CPRegWords[16]; /* map of coprocessor register sizes */
312 312
313 unsigned EventSet; /* the number of events in the queue */ 313 unsigned EventSet; /* the number of events in the queue */
314 unsigned int Now; /* time to the nearest cycle */ 314 unsigned int Now; /* time to the nearest cycle */
315 struct EventNode **EventPtr; /* the event list */ 315 struct EventNode **EventPtr; /* the event list */
316 316
317 unsigned Debug; /* show instructions as they are executed */ 317 unsigned Debug; /* show instructions as they are executed */
318 unsigned NresetSig; /* reset the processor */ 318 unsigned NresetSig; /* reset the processor */
319 unsigned NfiqSig; 319 unsigned NfiqSig;
320 unsigned NirqSig; 320 unsigned NirqSig;
321 321
322 unsigned abortSig; 322 unsigned abortSig;
323 unsigned NtransSig; 323 unsigned NtransSig;
324 unsigned bigendSig; 324 unsigned bigendSig;
325 unsigned prog32Sig; 325 unsigned prog32Sig;
326 unsigned data32Sig; 326 unsigned data32Sig;
327 unsigned syscallSig; 327 unsigned syscallSig;
328 328
329/* 2004-05-09 chy 329/* 2004-05-09 chy
330---------------------------------------------------------- 330----------------------------------------------------------
@@ -357,115 +357,115 @@ on later processors, this bit reads as 1 and ignores writes.
357So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model) 357So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
358 if lateabtSig=0, then it means Base Restored Abort Model 358 if lateabtSig=0, then it means Base Restored Abort Model
359*/ 359*/
360 unsigned lateabtSig; 360 unsigned lateabtSig;
361 361
362 ARMword Vector; /* synthesize aborts in cycle modes */ 362 ARMword Vector; /* synthesize aborts in cycle modes */
363 ARMword Aborted; /* sticky flag for aborts */ 363 ARMword Aborted; /* sticky flag for aborts */
364 ARMword Reseted; /* sticky flag for Reset */ 364 ARMword Reseted; /* sticky flag for Reset */
365 ARMword Inted, LastInted; /* sticky flags for interrupts */ 365 ARMword Inted, LastInted; /* sticky flags for interrupts */
366 ARMword Base; /* extra hand for base writeback */ 366 ARMword Base; /* extra hand for base writeback */
367 ARMword AbortAddr; /* to keep track of Prefetch aborts */ 367 ARMword AbortAddr; /* to keep track of Prefetch aborts */
368 368
369 const struct Dbg_HostosInterface *hostif; 369 const struct Dbg_HostosInterface *hostif;
370 370
371 int verbose; /* non-zero means print various messages like the banner */ 371 int verbose; /* non-zero means print various messages like the banner */
372 372
373 mmu_state_t mmu; 373 mmu_state_t mmu;
374 int mmu_inited; 374 int mmu_inited;
375 //mem_state_t mem; 375 //mem_state_t mem;
376 /*remove io_state to skyeye_mach_*.c files */ 376 /*remove io_state to skyeye_mach_*.c files */
377 //io_state_t io; 377 //io_state_t io;
378 /* point to a interrupt pending register. now for skyeye-ne2k.c 378 /* point to a interrupt pending register. now for skyeye-ne2k.c
379 * later should move somewhere. e.g machine_config_t*/ 379 * later should move somewhere. e.g machine_config_t*/
380 380
381 381
382 //chy: 2003-08-11, for different arm core type 382 //chy: 2003-08-11, for different arm core type
383 unsigned is_v4; /* Are we emulating a v4 architecture (or higher) ? */ 383 unsigned is_v4; /* Are we emulating a v4 architecture (or higher) ? */
384 unsigned is_v5; /* Are we emulating a v5 architecture ? */ 384 unsigned is_v5; /* Are we emulating a v5 architecture ? */
385 unsigned is_v5e; /* Are we emulating a v5e architecture ? */ 385 unsigned is_v5e; /* Are we emulating a v5e architecture ? */
386 unsigned is_v6; /* Are we emulating a v6 architecture ? */ 386 unsigned is_v6; /* Are we emulating a v6 architecture ? */
387 unsigned is_v7; /* Are we emulating a v7 architecture ? */ 387 unsigned is_v7; /* Are we emulating a v7 architecture ? */
388 unsigned is_XScale; /* Are we emulating an XScale architecture ? */ 388 unsigned is_XScale; /* Are we emulating an XScale architecture ? */
389 unsigned is_iWMMXt; /* Are we emulating an iWMMXt co-processor ? */ 389 unsigned is_iWMMXt; /* Are we emulating an iWMMXt co-processor ? */
390 unsigned is_ep9312; /* Are we emulating a Cirrus Maverick co-processor ? */ 390 unsigned is_ep9312; /* Are we emulating a Cirrus Maverick co-processor ? */
391 //chy 2005-09-19 391 //chy 2005-09-19
392 unsigned is_pxa27x; /* Are we emulating a Intel PXA27x co-processor ? */ 392 unsigned is_pxa27x; /* Are we emulating a Intel PXA27x co-processor ? */
393 //chy: seems only used in xscale's CP14 393 //chy: seems only used in xscale's CP14
394 unsigned int LastTime; /* Value of last call to ARMul_Time() */ 394 unsigned int LastTime; /* Value of last call to ARMul_Time() */
395 ARMword CP14R0_CCD; /* used to count 64 clock cycles with CP14 R0 bit 3 set */ 395 ARMword CP14R0_CCD; /* used to count 64 clock cycles with CP14 R0 bit 3 set */
396 396
397 397
398//added by ksh:for handle different machs io 2004-3-5 398//added by ksh:for handle different machs io 2004-3-5
399 ARMul_io mach_io; 399 ARMul_io mach_io;
400 400
401/*added by ksh,2004-11-26,some energy profiling*/ 401/*added by ksh,2004-11-26,some energy profiling*/
402 ARMul_Energy energy; 402 ARMul_Energy energy;
403 403
404//teawater add for next_dis 2004.10.27----------------------- 404//teawater add for next_dis 2004.10.27-----------------------
405 int disassemble; 405 int disassemble;
406//AJ2D------------------------------------------ 406//AJ2D------------------------------------------
407 407
408//teawater add for arm2x86 2005.02.15------------------------------------------- 408//teawater add for arm2x86 2005.02.15-------------------------------------------
409 u32 trap; 409 u32 trap;
410 u32 tea_break_addr; 410 u32 tea_break_addr;
411 u32 tea_break_ok; 411 u32 tea_break_ok;
412 int tea_pc; 412 int tea_pc;
413//AJ2D-------------------------------------------------------------------------- 413//AJ2D--------------------------------------------------------------------------
414//teawater add for arm2x86 2005.07.03------------------------------------------- 414//teawater add for arm2x86 2005.07.03-------------------------------------------
415 415
416 /* 416 /*
417 * 2007-01-24 removed the term-io functions by Anthony Lee, 417 * 2007-01-24 removed the term-io functions by Anthony Lee,
418 * moved to "device/uart/skyeye_uart_stdio.c". 418 * moved to "device/uart/skyeye_uart_stdio.c".
419 */ 419 */
420 420
421//AJ2D-------------------------------------------------------------------------- 421//AJ2D--------------------------------------------------------------------------
422//teawater add for arm2x86 2005.07.05------------------------------------------- 422//teawater add for arm2x86 2005.07.05-------------------------------------------
423 //arm_arm A2-18 423 //arm_arm A2-18
424 int abort_model; //0 Base Restored Abort Model, 1 the Early Abort Model, 2 Base Updated Abort Model 424 int abort_model; //0 Base Restored Abort Model, 1 the Early Abort Model, 2 Base Updated Abort Model
425//AJ2D-------------------------------------------------------------------------- 425//AJ2D--------------------------------------------------------------------------
426//teawater change for return if running tb dirty 2005.07.09--------------------- 426//teawater change for return if running tb dirty 2005.07.09---------------------
427 void *tb_now; 427 void *tb_now;
428//AJ2D-------------------------------------------------------------------------- 428//AJ2D--------------------------------------------------------------------------
429 429
430//teawater add for record reg value to ./reg.txt 2005.07.10--------------------- 430//teawater add for record reg value to ./reg.txt 2005.07.10---------------------
431 FILE *tea_reg_fd; 431 FILE *tea_reg_fd;
432//AJ2D-------------------------------------------------------------------------- 432//AJ2D--------------------------------------------------------------------------
433 433
434/*added by ksh in 2005-10-1*/ 434/*added by ksh in 2005-10-1*/
435 cpu_config_t *cpu; 435 cpu_config_t *cpu;
436 //mem_config_t *mem_bank; 436 //mem_config_t *mem_bank;
437 437
438/* added LPC remap function */ 438/* added LPC remap function */
439 int vector_remap_flag; 439 int vector_remap_flag;
440 u32 vector_remap_addr; 440 u32 vector_remap_addr;
441 u32 vector_remap_size; 441 u32 vector_remap_size;
442 442
443 u32 step; 443 u32 step;
444 u32 cycle; 444 u32 cycle;
445 int stop_simulator; 445 int stop_simulator;
446 conf_object_t *dyncom_cpu; 446 conf_object_t *dyncom_cpu;
447//teawater add DBCT_TEST_SPEED 2005.10.04--------------------------------------- 447//teawater add DBCT_TEST_SPEED 2005.10.04---------------------------------------
448#ifdef DBCT_TEST_SPEED 448#ifdef DBCT_TEST_SPEED
449 uint64_t instr_count; 449 uint64_t instr_count;
450#endif //DBCT_TEST_SPEED 450#endif //DBCT_TEST_SPEED
451// FILE * state_log; 451// FILE * state_log;
452//diff log 452//diff log
453//#if DIFF_STATE 453//#if DIFF_STATE
454 FILE * state_log; 454 FILE * state_log;
455//#endif 455//#endif
456 /* monitored memory for exclusice access */ 456 /* monitored memory for exclusice access */
457 ARMword exclusive_tag_array[128]; 457 ARMword exclusive_tag_array[128];
458 /* 1 means exclusive access and 0 means open access */ 458 /* 1 means exclusive access and 0 means open access */
459 ARMword exclusive_access_state; 459 ARMword exclusive_access_state;
460 460
461 memory_space_intf space; 461 memory_space_intf space;
462 u32 CurrInstr; 462 u32 CurrInstr;
463 u32 last_pc; /* the last pc executed */ 463 u32 last_pc; /* the last pc executed */
464 u32 last_instr; /* the last inst executed */ 464 u32 last_instr; /* the last inst executed */
465 u32 WriteAddr[17]; 465 u32 WriteAddr[17];
466 u32 WriteData[17]; 466 u32 WriteData[17];
467 u32 WritePc[17]; 467 u32 WritePc[17];
468 u32 CurrWrite; 468 u32 CurrWrite;
469}; 469};
470#define DIFF_WRITE 0 470#define DIFF_WRITE 0
471 471
@@ -510,7 +510,7 @@ typedef ARMul_State arm_core_t;
510#define ARM61 ARM2 510#define ARM61 ARM2
511#define ARM3 ARM2 511#define ARM3 ARM2
512 512
513#ifdef ARM60 /* previous definition in armopts.h */ 513#ifdef ARM60 /* previous definition in armopts.h */
514#undef ARM60 514#undef ARM60
515#endif 515#endif
516 516
@@ -526,9 +526,9 @@ typedef ARMul_State arm_core_t;
526* Macros to extract instruction fields * 526* Macros to extract instruction fields *
527\***************************************************************************/ 527\***************************************************************************/
528 528
529#define BIT(n) ( (ARMword)(instr>>(n))&1) /* bit n of instruction */ 529#define BIT(n) ( (ARMword)(instr>>(n))&1) /* bit n of instruction */
530#define BITS(m,n) ( (ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) ) /* bits m to n of instr */ 530#define BITS(m,n) ( (ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) ) /* bits m to n of instr */
531#define TOPBITS(n) (instr >> (n)) /* bits 31 to n of instr */ 531#define TOPBITS(n) (instr >> (n)) /* bits 31 to n of instr */
532 532
533/***************************************************************************\ 533/***************************************************************************\
534* The hardware vector addresses * 534* The hardware vector addresses *
@@ -542,7 +542,7 @@ typedef ARMul_State arm_core_t;
542#define ARMAddrExceptnV 20L 542#define ARMAddrExceptnV 20L
543#define ARMIRQV 24L 543#define ARMIRQV 24L
544#define ARMFIQV 28L 544#define ARMFIQV 28L
545#define ARMErrorV 32L /* This is an offset, not an address ! */ 545#define ARMErrorV 32L /* This is an offset, not an address ! */
546 546
547#define ARMul_ResetV ARMResetV 547#define ARMul_ResetV ARMResetV
548#define ARMul_UndefinedInstrV ARMUndefinedInstrV 548#define ARMul_UndefinedInstrV ARMUndefinedInstrV
@@ -598,7 +598,7 @@ extern "C" {
598extern void ARMul_EmulateInit (void); 598extern void ARMul_EmulateInit (void);
599extern void ARMul_Reset (ARMul_State * state); 599extern void ARMul_Reset (ARMul_State * state);
600#ifdef __cplusplus 600#ifdef __cplusplus
601 } 601 }
602#endif 602#endif
603extern ARMul_State *ARMul_NewState (ARMul_State * state); 603extern ARMul_State *ARMul_NewState (ARMul_State * state);
604extern ARMword ARMul_DoProg (ARMul_State * state); 604extern ARMword ARMul_DoProg (ARMul_State * state);
@@ -608,7 +608,7 @@ extern ARMword ARMul_DoInstr (ARMul_State * state);
608\***************************************************************************/ 608\***************************************************************************/
609 609
610extern void ARMul_ScheduleEvent (ARMul_State * state, unsigned int delay, 610extern void ARMul_ScheduleEvent (ARMul_State * state, unsigned int delay,
611 unsigned (*func) ()); 611 unsigned (*func) ());
612extern void ARMul_EnvokeEvent (ARMul_State * state); 612extern void ARMul_EnvokeEvent (ARMul_State * state);
613extern unsigned int ARMul_Time (ARMul_State * state); 613extern unsigned int ARMul_Time (ARMul_State * state);
614 614
@@ -617,9 +617,9 @@ extern unsigned int ARMul_Time (ARMul_State * state);
617\***************************************************************************/ 617\***************************************************************************/
618 618
619extern ARMword ARMul_GetReg (ARMul_State * state, unsigned mode, 619extern ARMword ARMul_GetReg (ARMul_State * state, unsigned mode,
620 unsigned reg); 620 unsigned reg);
621extern void ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg, 621extern void ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg,
622 ARMword value); 622 ARMword value);
623extern ARMword ARMul_GetPC (ARMul_State * state); 623extern ARMword ARMul_GetPC (ARMul_State * state);
624extern ARMword ARMul_GetNextPC (ARMul_State * state); 624extern ARMword ARMul_GetNextPC (ARMul_State * state);
625extern void ARMul_SetPC (ARMul_State * state, ARMword value); 625extern void ARMul_SetPC (ARMul_State * state, ARMword value);
@@ -637,11 +637,11 @@ extern void ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value);
637 637
638extern void ARMul_Abort (ARMul_State * state, ARMword address); 638extern void ARMul_Abort (ARMul_State * state, ARMword address);
639#ifdef MODET 639#ifdef MODET
640#define ARMul_ABORTWORD (state->TFlag ? 0xefffdfff : 0xefffffff) /* SWI -1 */ 640#define ARMul_ABORTWORD (state->TFlag ? 0xefffdfff : 0xefffffff) /* SWI -1 */
641#define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \ 641#define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \
642 state->AbortAddr = (address & (state->TFlag ? ~1L : ~3L)) 642 state->AbortAddr = (address & (state->TFlag ? ~1L : ~3L))
643#else 643#else
644#define ARMul_ABORTWORD 0xefffffff /* SWI -1 */ 644#define ARMul_ABORTWORD 0xefffffff /* SWI -1 */
645#define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \ 645#define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \
646 state->AbortAddr = (address & ~3L) 646 state->AbortAddr = (address & ~3L)
647#endif 647#endif
@@ -654,20 +654,20 @@ extern void ARMul_Abort (ARMul_State * state, ARMword address);
654\***************************************************************************/ 654\***************************************************************************/
655 655
656extern unsigned ARMul_MemoryInit (ARMul_State * state, 656extern unsigned ARMul_MemoryInit (ARMul_State * state,
657 unsigned int initmemsize); 657 unsigned int initmemsize);
658extern void ARMul_MemoryExit (ARMul_State * state); 658extern void ARMul_MemoryExit (ARMul_State * state);
659 659
660extern ARMword ARMul_LoadInstrS (ARMul_State * state, ARMword address, 660extern ARMword ARMul_LoadInstrS (ARMul_State * state, ARMword address,
661 ARMword isize); 661 ARMword isize);
662extern ARMword ARMul_LoadInstrN (ARMul_State * state, ARMword address, 662extern ARMword ARMul_LoadInstrN (ARMul_State * state, ARMword address,
663 ARMword isize); 663 ARMword isize);
664#ifdef __cplusplus 664#ifdef __cplusplus
665extern "C" { 665extern "C" {
666#endif 666#endif
667extern ARMword ARMul_ReLoadInstr (ARMul_State * state, ARMword address, 667extern ARMword ARMul_ReLoadInstr (ARMul_State * state, ARMword address,
668 ARMword isize); 668 ARMword isize);
669#ifdef __cplusplus 669#ifdef __cplusplus
670 } 670 }
671#endif 671#endif
672extern ARMword ARMul_LoadWordS (ARMul_State * state, ARMword address); 672extern ARMword ARMul_LoadWordS (ARMul_State * state, ARMword address);
673extern ARMword ARMul_LoadWordN (ARMul_State * state, ARMword address); 673extern ARMword ARMul_LoadWordN (ARMul_State * state, ARMword address);
@@ -675,34 +675,34 @@ extern ARMword ARMul_LoadHalfWord (ARMul_State * state, ARMword address);
675extern ARMword ARMul_LoadByte (ARMul_State * state, ARMword address); 675extern ARMword ARMul_LoadByte (ARMul_State * state, ARMword address);
676 676
677extern void ARMul_StoreWordS (ARMul_State * state, ARMword address, 677extern void ARMul_StoreWordS (ARMul_State * state, ARMword address,
678 ARMword data); 678 ARMword data);
679extern void ARMul_StoreWordN (ARMul_State * state, ARMword address, 679extern void ARMul_StoreWordN (ARMul_State * state, ARMword address,
680 ARMword data); 680 ARMword data);
681extern void ARMul_StoreHalfWord (ARMul_State * state, ARMword address, 681extern void ARMul_StoreHalfWord (ARMul_State * state, ARMword address,
682 ARMword data); 682 ARMword data);
683extern void ARMul_StoreByte (ARMul_State * state, ARMword address, 683extern void ARMul_StoreByte (ARMul_State * state, ARMword address,
684 ARMword data); 684 ARMword data);
685 685
686extern ARMword ARMul_SwapWord (ARMul_State * state, ARMword address, 686extern ARMword ARMul_SwapWord (ARMul_State * state, ARMword address,
687 ARMword data); 687 ARMword data);
688extern ARMword ARMul_SwapByte (ARMul_State * state, ARMword address, 688extern ARMword ARMul_SwapByte (ARMul_State * state, ARMword address,
689 ARMword data); 689 ARMword data);
690 690
691extern void ARMul_Icycles (ARMul_State * state, unsigned number, 691extern void ARMul_Icycles (ARMul_State * state, unsigned number,
692 ARMword address); 692 ARMword address);
693extern void ARMul_Ccycles (ARMul_State * state, unsigned number, 693extern void ARMul_Ccycles (ARMul_State * state, unsigned number,
694 ARMword address); 694 ARMword address);
695 695
696extern ARMword ARMul_ReadWord (ARMul_State * state, ARMword address); 696extern ARMword ARMul_ReadWord (ARMul_State * state, ARMword address);
697extern ARMword ARMul_ReadByte (ARMul_State * state, ARMword address); 697extern ARMword ARMul_ReadByte (ARMul_State * state, ARMword address);
698extern void ARMul_WriteWord (ARMul_State * state, ARMword address, 698extern void ARMul_WriteWord (ARMul_State * state, ARMword address,
699 ARMword data); 699 ARMword data);
700extern void ARMul_WriteByte (ARMul_State * state, ARMword address, 700extern void ARMul_WriteByte (ARMul_State * state, ARMword address,
701 ARMword data); 701 ARMword data);
702 702
703extern ARMword ARMul_MemAccess (ARMul_State * state, ARMword, ARMword, 703extern ARMword ARMul_MemAccess (ARMul_State * state, ARMword, ARMword,
704 ARMword, ARMword, ARMword, ARMword, ARMword, 704 ARMword, ARMword, ARMword, ARMword, ARMword,
705 ARMword, ARMword, ARMword); 705 ARMword, ARMword, ARMword);
706 706
707/***************************************************************************\ 707/***************************************************************************\
708* Definitons of things in the co-processor interface * 708* Definitons of things in the co-processor interface *
@@ -746,12 +746,12 @@ extern ARMword ARMul_MemAccess (ARMul_State * state, ARMword, ARMword,
746extern unsigned ARMul_CoProInit (ARMul_State * state); 746extern unsigned ARMul_CoProInit (ARMul_State * state);
747extern void ARMul_CoProExit (ARMul_State * state); 747extern void ARMul_CoProExit (ARMul_State * state);
748extern void ARMul_CoProAttach (ARMul_State * state, unsigned number, 748extern void ARMul_CoProAttach (ARMul_State * state, unsigned number,
749 ARMul_CPInits * init, ARMul_CPExits * exit, 749 ARMul_CPInits * init, ARMul_CPExits * exit,
750 ARMul_LDCs * ldc, ARMul_STCs * stc, 750 ARMul_LDCs * ldc, ARMul_STCs * stc,
751 ARMul_MRCs * mrc, ARMul_MCRs * mcr, 751 ARMul_MRCs * mrc, ARMul_MCRs * mcr,
752 ARMul_MRRCs * mrrc, ARMul_MCRRs * mcrr, 752 ARMul_MRRCs * mrrc, ARMul_MCRRs * mcrr,
753 ARMul_CDPs * cdp, 753 ARMul_CDPs * cdp,
754 ARMul_CPReads * read, ARMul_CPWrites * write); 754 ARMul_CPReads * read, ARMul_CPWrites * write);
755extern void ARMul_CoProDetach (ARMul_State * state, unsigned number); 755extern void ARMul_CoProDetach (ARMul_State * state, unsigned number);
756 756
757/***************************************************************************\ 757/***************************************************************************\
@@ -775,7 +775,7 @@ extern ARMword ARMul_OSLastErrorP (ARMul_State * state);
775 775
776extern ARMword ARMul_Debug (ARMul_State * state, ARMword pc, ARMword instr); 776extern ARMword ARMul_Debug (ARMul_State * state, ARMword pc, ARMword instr);
777extern unsigned ARMul_OSException (ARMul_State * state, ARMword vector, 777extern unsigned ARMul_OSException (ARMul_State * state, ARMword vector,
778 ARMword pc); 778 ARMword pc);
779extern int rdi_log; 779extern int rdi_log;
780 780
781/***************************************************************************\ 781/***************************************************************************\
@@ -783,9 +783,9 @@ extern int rdi_log;
783\***************************************************************************/ 783\***************************************************************************/
784 784
785#ifdef macintosh 785#ifdef macintosh
786pascal void SpinCursor (short increment); /* copied from CursorCtl.h */ 786pascal void SpinCursor (short increment); /* copied from CursorCtl.h */
787# define HOURGLASS SpinCursor( 1 ) 787# define HOURGLASS SpinCursor( 1 )
788# define HOURGLASS_RATE 1023 /* 2^n - 1 */ 788# define HOURGLASS_RATE 1023 /* 2^n - 1 */
789#endif 789#endif
790 790
791//teawater add for arm2x86 2005.02.14------------------------------------------- 791//teawater add for arm2x86 2005.02.14-------------------------------------------
@@ -821,38 +821,38 @@ pascal void SpinCursor (short increment); /* copied from CursorCtl.h */
821#define NV 15 821#define NV 15
822 822
823#ifndef NFLAG 823#ifndef NFLAG
824#define NFLAG state->NFlag 824#define NFLAG state->NFlag
825#endif //NFLAG 825#endif //NFLAG
826 826
827#ifndef ZFLAG 827#ifndef ZFLAG
828#define ZFLAG state->ZFlag 828#define ZFLAG state->ZFlag
829#endif //ZFLAG 829#endif //ZFLAG
830 830
831#ifndef CFLAG 831#ifndef CFLAG
832#define CFLAG state->CFlag 832#define CFLAG state->CFlag
833#endif //CFLAG 833#endif //CFLAG
834 834
835#ifndef VFLAG 835#ifndef VFLAG
836#define VFLAG state->VFlag 836#define VFLAG state->VFlag
837#endif //VFLAG 837#endif //VFLAG
838 838
839#ifndef IFLAG 839#ifndef IFLAG
840#define IFLAG (state->IFFlags >> 1) 840#define IFLAG (state->IFFlags >> 1)
841#endif //IFLAG 841#endif //IFLAG
842 842
843#ifndef FFLAG 843#ifndef FFLAG
844#define FFLAG (state->IFFlags & 1) 844#define FFLAG (state->IFFlags & 1)
845#endif //FFLAG 845#endif //FFLAG
846 846
847#ifndef IFFLAGS 847#ifndef IFFLAGS
848#define IFFLAGS state->IFFlags 848#define IFFLAGS state->IFFlags
849#endif //VFLAG 849#endif //VFLAG
850 850
851#define FLAG_MASK 0xf0000000 851#define FLAG_MASK 0xf0000000
852#define NBIT_SHIFT 31 852#define NBIT_SHIFT 31
853#define ZBIT_SHIFT 30 853#define ZBIT_SHIFT 30
854#define CBIT_SHIFT 29 854#define CBIT_SHIFT 29
855#define VBIT_SHIFT 28 855#define VBIT_SHIFT 28
856#ifdef DBCT 856#ifdef DBCT
857//teawater change for local tb branch directly jump 2005.10.18------------------ 857//teawater change for local tb branch directly jump 2005.10.18------------------
858#include "dbct/list.h" 858#include "dbct/list.h"
@@ -875,10 +875,10 @@ pascal void SpinCursor (short increment); /* copied from CursorCtl.h */
875 state->Reg[4],state->Reg[5],state->Reg[6],state->Reg[7], \ 875 state->Reg[4],state->Reg[5],state->Reg[6],state->Reg[7], \
876 state->Reg[8],state->Reg[9],state->Reg[10],state->Reg[11], \ 876 state->Reg[8],state->Reg[9],state->Reg[10],state->Reg[11], \
877 state->Reg[12],state->Reg[13],state->Reg[14],state->Reg[15], \ 877 state->Reg[12],state->Reg[13],state->Reg[14],state->Reg[15], \
878 state->Cpsr, state->Spsr[0], state->Spsr[1], state->Spsr[2],\ 878 state->Cpsr, state->Spsr[0], state->Spsr[1], state->Spsr[2],\
879 state->Spsr[3],state->Spsr[4], state->Spsr[5], state->Spsr[6],\ 879 state->Spsr[3],state->Spsr[4], state->Spsr[5], state->Spsr[6],\
880 state->Mode,state->Bank,state->ErrorCode,state->instr,state->pc,\ 880 state->Mode,state->Bank,state->ErrorCode,state->instr,state->pc,\
881 state->temp,state->loaded,state->decoded);} 881 state->temp,state->loaded,state->decoded);}
882 882
883#define SKYEYE_OUTMOREREGS(fd) { fprintf ((fd),"\ 883#define SKYEYE_OUTMOREREGS(fd) { fprintf ((fd),"\
884RUs %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\ 884RUs %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\
@@ -911,13 +911,13 @@ RUn %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x\n",\
911 state->RegBank[5][4],state->RegBank[5][5],state->RegBank[5][6],state->RegBank[5][7], \ 911 state->RegBank[5][4],state->RegBank[5][5],state->RegBank[5][6],state->RegBank[5][7], \
912 state->RegBank[5][8],state->RegBank[5][9],state->RegBank[5][10],state->RegBank[5][11], \ 912 state->RegBank[5][8],state->RegBank[5][9],state->RegBank[5][10],state->RegBank[5][11], \
913 state->RegBank[5][12],state->RegBank[5][13],state->RegBank[5][14],state->RegBank[5][15] \ 913 state->RegBank[5][12],state->RegBank[5][13],state->RegBank[5][14],state->RegBank[5][15] \
914 );} 914 );}
915 915
916 916
917#define SA1110 0x6901b110 917#define SA1110 0x6901b110
918#define SA1100 0x4401a100 918#define SA1100 0x4401a100
919#define PXA250 0x69052100 919#define PXA250 0x69052100
920#define PXA270 0x69054110 920#define PXA270 0x69054110
921//#define PXA250 0x69052903 921//#define PXA250 0x69052903
922// 0x69052903; //PXA250 B1 from intel 278522-001.pdf 922// 0x69052903; //PXA250 B1 from intel 278522-001.pdf
923 923
diff --git a/src/core/src/arm/armemu.cpp b/src/core/src/arm/armemu.cpp
index 362ae0fd1..0b14a6166 100644
--- a/src/core/src/arm/armemu.cpp
+++ b/src/core/src/arm/armemu.cpp
@@ -24,12 +24,12 @@
24void 24void
25XScale_set_fsr_far(ARMul_State * state, ARMword fsr, ARMword _far) 25XScale_set_fsr_far(ARMul_State * state, ARMword fsr, ARMword _far)
26{ 26{
27 _dbg_assert_msg_(ARM11, false, "ImplementMe: XScale_set_fsr_far!"); 27 _dbg_assert_msg_(ARM11, false, "ImplementMe: XScale_set_fsr_far!");
28 //if (!state->is_XScale || (read_cp14_reg(10) & (1UL << 31)) == 0) 28 //if (!state->is_XScale || (read_cp14_reg(10) & (1UL << 31)) == 0)
29 // return; 29 // return;
30 // 30 //
31 //write_cp15_reg(state, 5, 0, 0, fsr); 31 //write_cp15_reg(state, 5, 0, 0, fsr);
32 //write_cp15_reg(state, 6, 0, 0, _far); 32 //write_cp15_reg(state, 6, 0, 0, _far);
33} 33}
34 34
35#define ARMul_Debug(x,y,z) 0 // Disabling this /bunnei 35#define ARMul_Debug(x,y,z) 0 // Disabling this /bunnei
@@ -78,10 +78,10 @@ unsigned xscale_cp15_cp_access_allowed (ARMul_State * state, unsigned reg,
78static int 78static int
79handle_v6_insn (ARMul_State * state, ARMword instr); 79handle_v6_insn (ARMul_State * state, ARMword instr);
80 80
81#define LUNSIGNED (0) /* unsigned operation */ 81#define LUNSIGNED (0) /* unsigned operation */
82#define LSIGNED (1) /* signed operation */ 82#define LSIGNED (1) /* signed operation */
83#define LDEFAULT (0) /* default : do nothing */ 83#define LDEFAULT (0) /* default : do nothing */
84#define LSCC (1) /* set condition codes on result */ 84#define LSCC (1) /* set condition codes on result */
85 85
86#ifdef NEED_UI_LOOP_HOOK 86#ifdef NEED_UI_LOOP_HOOK
87/* How often to run the ui_loop update, when in use. */ 87/* How often to run the ui_loop update, when in use. */
@@ -131,175 +131,175 @@ extern int (*ui_loop_hook) (int);
131/* Load post decrement writeback. */ 131/* Load post decrement writeback. */
132#define LHPOSTDOWN() \ 132#define LHPOSTDOWN() \
133{ \ 133{ \
134 int done = 1; \ 134 int done = 1; \
135 lhs = LHS; \ 135 lhs = LHS; \
136 temp = lhs - GetLS7RHS (state, instr); \ 136 temp = lhs - GetLS7RHS (state, instr); \
137 \ 137 \
138 switch (BITS (5, 6)) \ 138 switch (BITS (5, 6)) \
139 { \ 139 { \
140 case 1: /* H */ \ 140 case 1: /* H */ \
141 if (LoadHalfWord (state, instr, lhs, LUNSIGNED)) \ 141 if (LoadHalfWord (state, instr, lhs, LUNSIGNED)) \
142 LSBase = temp; \ 142 LSBase = temp; \
143 break; \ 143 break; \
144 case 2: /* SB */ \ 144 case 2: /* SB */ \
145 if (LoadByte (state, instr, lhs, LSIGNED)) \ 145 if (LoadByte (state, instr, lhs, LSIGNED)) \
146 LSBase = temp; \ 146 LSBase = temp; \
147 break; \ 147 break; \
148 case 3: /* SH */ \ 148 case 3: /* SH */ \
149 if (LoadHalfWord (state, instr, lhs, LSIGNED)) \ 149 if (LoadHalfWord (state, instr, lhs, LSIGNED)) \
150 LSBase = temp; \ 150 LSBase = temp; \
151 break; \ 151 break; \
152 case 0: /* SWP handled elsewhere. */ \ 152 case 0: /* SWP handled elsewhere. */ \
153 default: \ 153 default: \
154 done = 0; \ 154 done = 0; \
155 break; \ 155 break; \
156 } \ 156 } \
157 if (done) \ 157 if (done) \
158 break; \ 158 break; \
159} 159}
160 160
161/* Load post increment writeback. */ 161/* Load post increment writeback. */
162#define LHPOSTUP() \ 162#define LHPOSTUP() \
163{ \ 163{ \
164 int done = 1; \ 164 int done = 1; \
165 lhs = LHS; \ 165 lhs = LHS; \
166 temp = lhs + GetLS7RHS (state, instr); \ 166 temp = lhs + GetLS7RHS (state, instr); \
167 \ 167 \
168 switch (BITS (5, 6)) \ 168 switch (BITS (5, 6)) \
169 { \ 169 { \
170 case 1: /* H */ \ 170 case 1: /* H */ \
171 if (LoadHalfWord (state, instr, lhs, LUNSIGNED)) \ 171 if (LoadHalfWord (state, instr, lhs, LUNSIGNED)) \
172 LSBase = temp; \ 172 LSBase = temp; \
173 break; \ 173 break; \
174 case 2: /* SB */ \ 174 case 2: /* SB */ \
175 if (LoadByte (state, instr, lhs, LSIGNED)) \ 175 if (LoadByte (state, instr, lhs, LSIGNED)) \
176 LSBase = temp; \ 176 LSBase = temp; \
177 break; \ 177 break; \
178 case 3: /* SH */ \ 178 case 3: /* SH */ \
179 if (LoadHalfWord (state, instr, lhs, LSIGNED)) \ 179 if (LoadHalfWord (state, instr, lhs, LSIGNED)) \
180 LSBase = temp; \ 180 LSBase = temp; \
181 break; \ 181 break; \
182 case 0: /* SWP handled elsewhere. */ \ 182 case 0: /* SWP handled elsewhere. */ \
183 default: \ 183 default: \
184 done = 0; \ 184 done = 0; \
185 break; \ 185 break; \
186 } \ 186 } \
187 if (done) \ 187 if (done) \
188 break; \ 188 break; \
189} 189}
190 190
191/* Load pre decrement. */ 191/* Load pre decrement. */
192#define LHPREDOWN() \ 192#define LHPREDOWN() \
193{ \ 193{ \
194 int done = 1; \ 194 int done = 1; \
195 \ 195 \
196 temp = LHS - GetLS7RHS (state, instr); \ 196 temp = LHS - GetLS7RHS (state, instr); \
197 switch (BITS (5, 6)) \ 197 switch (BITS (5, 6)) \
198 { \ 198 { \
199 case 1: /* H */ \ 199 case 1: /* H */ \
200 (void) LoadHalfWord (state, instr, temp, LUNSIGNED); \ 200 (void) LoadHalfWord (state, instr, temp, LUNSIGNED); \
201 break; \ 201 break; \
202 case 2: /* SB */ \ 202 case 2: /* SB */ \
203 (void) LoadByte (state, instr, temp, LSIGNED); \ 203 (void) LoadByte (state, instr, temp, LSIGNED); \
204 break; \ 204 break; \
205 case 3: /* SH */ \ 205 case 3: /* SH */ \
206 (void) LoadHalfWord (state, instr, temp, LSIGNED); \ 206 (void) LoadHalfWord (state, instr, temp, LSIGNED); \
207 break; \ 207 break; \
208 case 0: \ 208 case 0: \
209 /* SWP handled elsewhere. */ \ 209 /* SWP handled elsewhere. */ \
210 default: \ 210 default: \
211 done = 0; \ 211 done = 0; \
212 break; \ 212 break; \
213 } \ 213 } \
214 if (done) \ 214 if (done) \
215 break; \ 215 break; \
216} 216}
217 217
218/* Load pre decrement writeback. */ 218/* Load pre decrement writeback. */
219#define LHPREDOWNWB() \ 219#define LHPREDOWNWB() \
220{ \ 220{ \
221 int done = 1; \ 221 int done = 1; \
222 \ 222 \
223 temp = LHS - GetLS7RHS (state, instr); \ 223 temp = LHS - GetLS7RHS (state, instr); \
224 switch (BITS (5, 6)) \ 224 switch (BITS (5, 6)) \
225 { \ 225 { \
226 case 1: /* H */ \ 226 case 1: /* H */ \
227 if (LoadHalfWord (state, instr, temp, LUNSIGNED)) \ 227 if (LoadHalfWord (state, instr, temp, LUNSIGNED)) \
228 LSBase = temp; \ 228 LSBase = temp; \
229 break; \ 229 break; \
230 case 2: /* SB */ \ 230 case 2: /* SB */ \
231 if (LoadByte (state, instr, temp, LSIGNED)) \ 231 if (LoadByte (state, instr, temp, LSIGNED)) \
232 LSBase = temp; \ 232 LSBase = temp; \
233 break; \ 233 break; \
234 case 3: /* SH */ \ 234 case 3: /* SH */ \
235 if (LoadHalfWord (state, instr, temp, LSIGNED)) \ 235 if (LoadHalfWord (state, instr, temp, LSIGNED)) \
236 LSBase = temp; \ 236 LSBase = temp; \
237 break; \ 237 break; \
238 case 0: \ 238 case 0: \
239 /* SWP handled elsewhere. */ \ 239 /* SWP handled elsewhere. */ \
240 default: \ 240 default: \
241 done = 0; \ 241 done = 0; \
242 break; \ 242 break; \
243 } \ 243 } \
244 if (done) \ 244 if (done) \
245 break; \ 245 break; \
246} 246}
247 247
248/* Load pre increment. */ 248/* Load pre increment. */
249#define LHPREUP() \ 249#define LHPREUP() \
250{ \ 250{ \
251 int done = 1; \ 251 int done = 1; \
252 \ 252 \
253 temp = LHS + GetLS7RHS (state, instr); \ 253 temp = LHS + GetLS7RHS (state, instr); \
254 switch (BITS (5, 6)) \ 254 switch (BITS (5, 6)) \
255 { \ 255 { \
256 case 1: /* H */ \ 256 case 1: /* H */ \
257 (void) LoadHalfWord (state, instr, temp, LUNSIGNED); \ 257 (void) LoadHalfWord (state, instr, temp, LUNSIGNED); \
258 break; \ 258 break; \
259 case 2: /* SB */ \ 259 case 2: /* SB */ \
260 (void) LoadByte (state, instr, temp, LSIGNED); \ 260 (void) LoadByte (state, instr, temp, LSIGNED); \
261 break; \ 261 break; \
262 case 3: /* SH */ \ 262 case 3: /* SH */ \
263 (void) LoadHalfWord (state, instr, temp, LSIGNED); \ 263 (void) LoadHalfWord (state, instr, temp, LSIGNED); \
264 break; \ 264 break; \
265 case 0: \ 265 case 0: \
266 /* SWP handled elsewhere. */ \ 266 /* SWP handled elsewhere. */ \
267 default: \ 267 default: \
268 done = 0; \ 268 done = 0; \
269 break; \ 269 break; \
270 } \ 270 } \
271 if (done) \ 271 if (done) \
272 break; \ 272 break; \
273} 273}
274 274
275/* Load pre increment writeback. */ 275/* Load pre increment writeback. */
276#define LHPREUPWB() \ 276#define LHPREUPWB() \
277{ \ 277{ \
278 int done = 1; \ 278 int done = 1; \
279 \ 279 \
280 temp = LHS + GetLS7RHS (state, instr); \ 280 temp = LHS + GetLS7RHS (state, instr); \
281 switch (BITS (5, 6)) \ 281 switch (BITS (5, 6)) \
282 { \ 282 { \
283 case 1: /* H */ \ 283 case 1: /* H */ \
284 if (LoadHalfWord (state, instr, temp, LUNSIGNED)) \ 284 if (LoadHalfWord (state, instr, temp, LUNSIGNED)) \
285 LSBase = temp; \ 285 LSBase = temp; \
286 break; \ 286 break; \
287 case 2: /* SB */ \ 287 case 2: /* SB */ \
288 if (LoadByte (state, instr, temp, LSIGNED)) \ 288 if (LoadByte (state, instr, temp, LSIGNED)) \
289 LSBase = temp; \ 289 LSBase = temp; \
290 break; \ 290 break; \
291 case 3: /* SH */ \ 291 case 3: /* SH */ \
292 if (LoadHalfWord (state, instr, temp, LSIGNED)) \ 292 if (LoadHalfWord (state, instr, temp, LSIGNED)) \
293 LSBase = temp; \ 293 LSBase = temp; \
294 break; \ 294 break; \
295 case 0: \ 295 case 0: \
296 /* SWP handled elsewhere. */ \ 296 /* SWP handled elsewhere. */ \
297 default: \ 297 default: \
298 done = 0; \ 298 done = 0; \
299 break; \ 299 break; \
300 } \ 300 } \
301 if (done) \ 301 if (done) \
302 break; \ 302 break; \
303} 303}
304 304
305/*ywc 2005-03-31*/ 305/*ywc 2005-03-31*/
@@ -330,17 +330,17 @@ int ARMul_ICE_debug(ARMul_State *state,ARMword instr,ARMword addr)
330 if (debugmode) { 330 if (debugmode) {
331 if (instr == ARMul_ABORTWORD) return 0; 331 if (instr == ARMul_ABORTWORD) return 0;
332 for (i = 0; i < skyeye_ice.num_bps; i++) { 332 for (i = 0; i < skyeye_ice.num_bps; i++) {
333 if (skyeye_ice.bps[i] == addr) { 333 if (skyeye_ice.bps[i] == addr) {
334 //for test 334 //for test
335 //printf("SKYEYE: ICE_debug bps [%d]== 0x%x\n", i,addr); 335 //printf("SKYEYE: ICE_debug bps [%d]== 0x%x\n", i,addr);
336 state->EndCondition = 0; 336 state->EndCondition = 0;
337 state->Emulate = STOP; 337 state->Emulate = STOP;
338 return 1; 338 return 1;
339 } 339 }
340 } 340 }
341 if (skyeye_ice.tps_status==TRACE_STARTED) 341 if (skyeye_ice.tps_status==TRACE_STARTED)
342 { 342 {
343 for (i = 0; i < skyeye_ice.num_tps; i++) 343 for (i = 0; i < skyeye_ice.num_tps; i++)
344 { 344 {
345 if (((skyeye_ice.tps[i].tp_address==addr)&&(skyeye_ice.tps[i].status==TRACEPOINT_ENABLED))||(skyeye_ice.tps[i].status==TRACEPOINT_STEPPING)) 345 if (((skyeye_ice.tps[i].tp_address==addr)&&(skyeye_ice.tps[i].status==TRACEPOINT_ENABLED))||(skyeye_ice.tps[i].status==TRACEPOINT_STEPPING))
346 { 346 {
@@ -353,22 +353,22 @@ int ARMul_ICE_debug(ARMul_State *state,ARMword instr,ARMword addr)
353 if (skyeye_config.code_cov.prof_on) 353 if (skyeye_config.code_cov.prof_on)
354 cov_prof(EXEC_FLAG, addr); 354 cov_prof(EXEC_FLAG, addr);
355#endif 355#endif
356 /* chech if we need to run some callback functions at this time */ 356 /* chech if we need to run some callback functions at this time */
357 //generic_arch_t* arch_instance = get_arch_instance(""); 357 //generic_arch_t* arch_instance = get_arch_instance("");
358 //exec_callback(Step_callback, arch_instance); 358 //exec_callback(Step_callback, arch_instance);
359 //if (!SIM_is_running()) { 359 //if (!SIM_is_running()) {
360 // if (instr == ARMul_ABORTWORD) return 0; 360 // if (instr == ARMul_ABORTWORD) return 0;
361 // state->EndCondition = 0; 361 // state->EndCondition = 0;
362 // state->Emulate = STOP; 362 // state->Emulate = STOP;
363 // return 1; 363 // return 1;
364 //} 364 //}
365 return 0; 365 return 0;
366} 366}
367 367
368/* 368/*
369void chy_debug() 369void chy_debug()
370{ 370{
371 printf("SkyEye chy_deubeg begin\n"); 371 printf("SkyEye chy_deubeg begin\n");
372} 372}
373*/ 373*/
374ARMword 374ARMword
@@ -378,26 +378,26 @@ ARMword
378ARMul_Emulate26 (ARMul_State * state) 378ARMul_Emulate26 (ARMul_State * state)
379#endif 379#endif
380{ 380{
381 ARMword instr; /* The current instruction. */ 381 ARMword instr; /* The current instruction. */
382 ARMword dest = 0; /* Almost the DestBus. */ 382 ARMword dest = 0; /* Almost the DestBus. */
383 ARMword temp; /* Ubiquitous third hand. */ 383 ARMword temp; /* Ubiquitous third hand. */
384 ARMword pc = 0; /* The address of the current instruction. */ 384 ARMword pc = 0; /* The address of the current instruction. */
385 ARMword lhs; /* Almost the ABus and BBus. */ 385 ARMword lhs; /* Almost the ABus and BBus. */
386 ARMword rhs; 386 ARMword rhs;
387 ARMword decoded = 0; /* Instruction pipeline. */ 387 ARMword decoded = 0; /* Instruction pipeline. */
388 ARMword loaded = 0; 388 ARMword loaded = 0;
389 ARMword decoded_addr=0; 389 ARMword decoded_addr=0;
390 ARMword loaded_addr=0; 390 ARMword loaded_addr=0;
391 ARMword have_bp=0; 391 ARMword have_bp=0;
392 392
393 /* shenoubang */ 393 /* shenoubang */
394 static int instr_sum = 0; 394 static int instr_sum = 0;
395 int reg_index = 0; 395 int reg_index = 0;
396#if DIFF_STATE 396#if DIFF_STATE
397//initialize all mirror register for follow mode 397//initialize all mirror register for follow mode
398 for (reg_index = 0; reg_index < 16; reg_index ++) { 398 for (reg_index = 0; reg_index < 16; reg_index ++) {
399 mirror_register_file[reg_index] = state->Reg[reg_index]; 399 mirror_register_file[reg_index] = state->Reg[reg_index];
400 } 400 }
401 mirror_register_file[CPSR_REG] = state->Cpsr; 401 mirror_register_file[CPSR_REG] = state->Cpsr;
402 mirror_register_file[R13_SVC] = state->RegBank[SVCBANK][13]; 402 mirror_register_file[R13_SVC] = state->RegBank[SVCBANK][13];
403 mirror_register_file[R14_SVC] = state->RegBank[SVCBANK][14]; 403 mirror_register_file[R14_SVC] = state->RegBank[SVCBANK][14];
@@ -420,136 +420,136 @@ ARMul_Emulate26 (ARMul_State * state)
420 mirror_register_file[SPSR_IRQ] = state->Spsr[IRQBANK]; 420 mirror_register_file[SPSR_IRQ] = state->Spsr[IRQBANK];
421 mirror_register_file[SPSR_FIRQ] = state->Spsr[FIQBANK]; 421 mirror_register_file[SPSR_FIRQ] = state->Spsr[FIQBANK];
422#endif 422#endif
423 /* Execute the next instruction. */ 423 /* Execute the next instruction. */
424 if (state->NextInstr < PRIMEPIPE) { 424 if (state->NextInstr < PRIMEPIPE) {
425 decoded = state->decoded; 425 decoded = state->decoded;
426 loaded = state->loaded; 426 loaded = state->loaded;
427 pc = state->pc; 427 pc = state->pc;
428 //chy 2006-04-12, for ICE debug 428 //chy 2006-04-12, for ICE debug
429 decoded_addr=state->decoded_addr; 429 decoded_addr=state->decoded_addr;
430 loaded_addr=state->loaded_addr; 430 loaded_addr=state->loaded_addr;
431 } 431 }
432 432
433 do { 433 do {
434 //print_func_name(state->pc); 434 //print_func_name(state->pc);
435 /* Just keep going. */ 435 /* Just keep going. */
436 isize = INSN_SIZE; 436 isize = INSN_SIZE;
437 437
438 switch (state->NextInstr) { 438 switch (state->NextInstr) {
439 case SEQ: 439 case SEQ:
440 /* Advance the pipeline, and an S cycle. */ 440 /* Advance the pipeline, and an S cycle. */
441 state->Reg[15] += isize; 441 state->Reg[15] += isize;
442 pc += isize; 442 pc += isize;
443 instr = decoded; 443 instr = decoded;
444 //chy 2006-04-12, for ICE debug 444 //chy 2006-04-12, for ICE debug
445 have_bp = ARMul_ICE_debug(state,instr,decoded_addr); 445 have_bp = ARMul_ICE_debug(state,instr,decoded_addr);
446 decoded = loaded; 446 decoded = loaded;
447 decoded_addr=loaded_addr; 447 decoded_addr=loaded_addr;
448 //loaded = ARMul_LoadInstrS (state, pc + (isize * 2), 448 //loaded = ARMul_LoadInstrS (state, pc + (isize * 2),
449 // isize); 449 // isize);
450 loaded_addr=pc + (isize * 2); 450 loaded_addr=pc + (isize * 2);
451 if (have_bp) goto TEST_EMULATE; 451 if (have_bp) goto TEST_EMULATE;
452 break; 452 break;
453 453
454 case NONSEQ: 454 case NONSEQ:
455 /* Advance the pipeline, and an N cycle. */ 455 /* Advance the pipeline, and an N cycle. */
456 state->Reg[15] += isize; 456 state->Reg[15] += isize;
457 pc += isize; 457 pc += isize;
458 instr = decoded; 458 instr = decoded;
459 //chy 2006-04-12, for ICE debug 459 //chy 2006-04-12, for ICE debug
460 have_bp=ARMul_ICE_debug(state,instr,decoded_addr); 460 have_bp=ARMul_ICE_debug(state,instr,decoded_addr);
461 decoded = loaded; 461 decoded = loaded;
462 decoded_addr=loaded_addr; 462 decoded_addr=loaded_addr;
463 //loaded = ARMul_LoadInstrN (state, pc + (isize * 2), 463 //loaded = ARMul_LoadInstrN (state, pc + (isize * 2),
464 // isize); 464 // isize);
465 loaded_addr=pc + (isize * 2); 465 loaded_addr=pc + (isize * 2);
466 NORMALCYCLE; 466 NORMALCYCLE;
467 if (have_bp) goto TEST_EMULATE; 467 if (have_bp) goto TEST_EMULATE;
468 break; 468 break;
469 469
470 case PCINCEDSEQ: 470 case PCINCEDSEQ:
471 /* Program counter advanced, and an S cycle. */ 471 /* Program counter advanced, and an S cycle. */
472 pc += isize; 472 pc += isize;
473 instr = decoded; 473 instr = decoded;
474 //chy 2006-04-12, for ICE debug 474 //chy 2006-04-12, for ICE debug
475 have_bp=ARMul_ICE_debug(state,instr,decoded_addr); 475 have_bp=ARMul_ICE_debug(state,instr,decoded_addr);
476 decoded = loaded; 476 decoded = loaded;
477 decoded_addr=loaded_addr; 477 decoded_addr=loaded_addr;
478 //loaded = ARMul_LoadInstrS (state, pc + (isize * 2), 478 //loaded = ARMul_LoadInstrS (state, pc + (isize * 2),
479 // isize); 479 // isize);
480 loaded_addr=pc + (isize * 2); 480 loaded_addr=pc + (isize * 2);
481 NORMALCYCLE; 481 NORMALCYCLE;
482 if (have_bp) goto TEST_EMULATE; 482 if (have_bp) goto TEST_EMULATE;
483 break; 483 break;
484 484
485 case PCINCEDNONSEQ: 485 case PCINCEDNONSEQ:
486 /* Program counter advanced, and an N cycle. */ 486 /* Program counter advanced, and an N cycle. */
487 pc += isize; 487 pc += isize;
488 instr = decoded; 488 instr = decoded;
489 //chy 2006-04-12, for ICE debug 489 //chy 2006-04-12, for ICE debug
490 have_bp=ARMul_ICE_debug(state,instr,decoded_addr); 490 have_bp=ARMul_ICE_debug(state,instr,decoded_addr);
491 decoded = loaded; 491 decoded = loaded;
492 decoded_addr=loaded_addr; 492 decoded_addr=loaded_addr;
493 //loaded = ARMul_LoadInstrN (state, pc + (isize * 2), 493 //loaded = ARMul_LoadInstrN (state, pc + (isize * 2),
494 // isize); 494 // isize);
495 loaded_addr=pc + (isize * 2); 495 loaded_addr=pc + (isize * 2);
496 NORMALCYCLE; 496 NORMALCYCLE;
497 if (have_bp) goto TEST_EMULATE; 497 if (have_bp) goto TEST_EMULATE;
498 break; 498 break;
499 499
500 case RESUME: 500 case RESUME:
501 /* The program counter has been changed. */ 501 /* The program counter has been changed. */
502 pc = state->Reg[15]; 502 pc = state->Reg[15];
503#ifndef MODE32 503#ifndef MODE32
504 pc = pc & R15PCBITS; 504 pc = pc & R15PCBITS;
505#endif 505#endif
506 state->Reg[15] = pc + (isize * 2); 506 state->Reg[15] = pc + (isize * 2);
507 state->Aborted = 0; 507 state->Aborted = 0;
508 //chy 2004-05-25, fix bug provided by Carl van Schaik<cvansch@cse.unsw.EDU.AU> 508 //chy 2004-05-25, fix bug provided by Carl van Schaik<cvansch@cse.unsw.EDU.AU>
509 state->AbortAddr = 1; 509 state->AbortAddr = 1;
510 510
511 instr = ARMul_LoadInstrN (state, pc, isize); 511 instr = ARMul_LoadInstrN (state, pc, isize);
512 //instr = ARMul_ReLoadInstr (state, pc, isize); 512 //instr = ARMul_ReLoadInstr (state, pc, isize);
513 //chy 2006-04-12, for ICE debug 513 //chy 2006-04-12, for ICE debug
514 have_bp=ARMul_ICE_debug(state,instr,pc); 514 have_bp=ARMul_ICE_debug(state,instr,pc);
515 //decoded = 515 //decoded =
516 // ARMul_ReLoadInstr (state, pc + isize, isize); 516 // ARMul_ReLoadInstr (state, pc + isize, isize);
517 decoded_addr=pc+isize; 517 decoded_addr=pc+isize;
518 //loaded = ARMul_ReLoadInstr (state, pc + isize * 2, 518 //loaded = ARMul_ReLoadInstr (state, pc + isize * 2,
519 // isize); 519 // isize);
520 loaded_addr=pc + isize * 2; 520 loaded_addr=pc + isize * 2;
521 NORMALCYCLE; 521 NORMALCYCLE;
522 if (have_bp) goto TEST_EMULATE; 522 if (have_bp) goto TEST_EMULATE;
523 break; 523 break;
524 524
525 default: 525 default:
526 /* The program counter has been changed. */ 526 /* The program counter has been changed. */
527 pc = state->Reg[15]; 527 pc = state->Reg[15];
528#ifndef MODE32 528#ifndef MODE32
529 pc = pc & R15PCBITS; 529 pc = pc & R15PCBITS;
530#endif 530#endif
531 state->Reg[15] = pc + (isize * 2); 531 state->Reg[15] = pc + (isize * 2);
532 state->Aborted = 0; 532 state->Aborted = 0;
533 //chy 2004-05-25, fix bug provided by Carl van Schaik<cvansch@cse.unsw.EDU.AU> 533 //chy 2004-05-25, fix bug provided by Carl van Schaik<cvansch@cse.unsw.EDU.AU>
534 state->AbortAddr = 1; 534 state->AbortAddr = 1;
535 535
536 instr = ARMul_LoadInstrN (state, pc, isize); 536 instr = ARMul_LoadInstrN (state, pc, isize);
537 //chy 2006-04-12, for ICE debug 537 //chy 2006-04-12, for ICE debug
538 have_bp=ARMul_ICE_debug(state,instr,pc); 538 have_bp=ARMul_ICE_debug(state,instr,pc);
539 #if 0 539 #if 0
540 decoded = 540 decoded =
541 ARMul_LoadInstrS (state, pc + (isize), isize); 541 ARMul_LoadInstrS (state, pc + (isize), isize);
542 #endif 542 #endif
543 decoded_addr=pc+isize; 543 decoded_addr=pc+isize;
544 #if 0 544 #if 0
545 loaded = ARMul_LoadInstrS (state, pc + (isize * 2), 545 loaded = ARMul_LoadInstrS (state, pc + (isize * 2),
546 isize); 546 isize);
547 #endif 547 #endif
548 loaded_addr=pc + isize * 2; 548 loaded_addr=pc + isize * 2;
549 NORMALCYCLE; 549 NORMALCYCLE;
550 if (have_bp) goto TEST_EMULATE; 550 if (have_bp) goto TEST_EMULATE;
551 break; 551 break;
552 } 552 }
553#if 0 553#if 0
554 int idx = 0; 554 int idx = 0;
555 printf("pc:%x\n", pc); 555 printf("pc:%x\n", pc);
@@ -558,31 +558,31 @@ ARMul_Emulate26 (ARMul_State * state)
558 } 558 }
559 printf("\n"); 559 printf("\n");
560#endif 560#endif
561 instr = ARMul_LoadInstrN (state, pc, isize); 561 instr = ARMul_LoadInstrN (state, pc, isize);
562 state->last_instr = state->CurrInstr; 562 state->last_instr = state->CurrInstr;
563 state->CurrInstr = instr; 563 state->CurrInstr = instr;
564#if 0 564#if 0
565 if((state->NumInstrs % 10000000) == 0) 565 if((state->NumInstrs % 10000000) == 0)
566 printf("---|%p|--- %lld\n", pc, state->NumInstrs); 566 printf("---|%p|--- %lld\n", pc, state->NumInstrs);
567 if(state->NumInstrs > (3000000000)){ 567 if(state->NumInstrs > (3000000000)){
568 static int flag = 0; 568 static int flag = 0;
569 if(pc == 0x8032ccc4){ 569 if(pc == 0x8032ccc4){
570 flag = 300; 570 flag = 300;
571 } 571 }
572 if(flag){ 572 if(flag){
573 int idx = 0; 573 int idx = 0;
574 printf("------------------------------------\n"); 574 printf("------------------------------------\n");
575 printf("pc:%x\n", pc); 575 printf("pc:%x\n", pc);
576 for (;idx < 17; idx ++) { 576 for (;idx < 17; idx ++) {
577 printf("R%d:%x\t", idx, state->Reg[idx]); 577 printf("R%d:%x\t", idx, state->Reg[idx]);
578 } 578 }
579 printf("\nN:%d\t Z:%d\t C:%d\t V:%d\n", state->NFlag, state->ZFlag, state->CFlag, state->VFlag); 579 printf("\nN:%d\t Z:%d\t C:%d\t V:%d\n", state->NFlag, state->ZFlag, state->CFlag, state->VFlag);
580 printf("\n"); 580 printf("\n");
581 printf("------------------------------------\n"); 581 printf("------------------------------------\n");
582 flag--; 582 flag--;
583 } 583 }
584 } 584 }
585#endif 585#endif
586#if DIFF_STATE 586#if DIFF_STATE
587 fprintf(state->state_log, "PC:0x%x\n", pc); 587 fprintf(state->state_log, "PC:0x%x\n", pc);
588 if (pc && (pc + 8) != state->Reg[15]) { 588 if (pc && (pc + 8) != state->Reg[15]) {
@@ -683,187 +683,187 @@ ARMul_Emulate26 (ARMul_State * state)
683#endif 683#endif
684 684
685#if 0 685#if 0
686 uint32_t alex = 0; 686 uint32_t alex = 0;
687 static int flagged = 0; 687 static int flagged = 0;
688 if ((flagged == 0) && (pc == 0xb224)) 688 if ((flagged == 0) && (pc == 0xb224))
689 { 689 {
690 flagged++; 690 flagged++;
691 } 691 }
692 if ((flagged == 1) && (pc == 0x1a800)) 692 if ((flagged == 1) && (pc == 0x1a800))
693 { 693 {
694 flagged++; 694 flagged++;
695 } 695 }
696 if (flagged == 3) { 696 if (flagged == 3) {
697 printf("---|%p|--- %x\n", pc, state->NumInstrs); 697 printf("---|%p|--- %x\n", pc, state->NumInstrs);
698 for (alex = 0; alex < 15; alex++) 698 for (alex = 0; alex < 15; alex++)
699 { 699 {
700 printf("R%02d % 8x\n", alex, state->Reg[alex]); 700 printf("R%02d % 8x\n", alex, state->Reg[alex]);
701 } 701 }
702 printf("R%02d % 8x\n", alex, state->Reg[alex] - 8); 702 printf("R%02d % 8x\n", alex, state->Reg[alex] - 8);
703 printf("CPS %x%07x\n", (state->NFlag<<3 | state->ZFlag<<2 | state->CFlag<<1 | state->VFlag), state->Cpsr & 0xfffffff); 703 printf("CPS %x%07x\n", (state->NFlag<<3 | state->ZFlag<<2 | state->CFlag<<1 | state->VFlag), state->Cpsr & 0xfffffff);
704 } else { 704 } else {
705 if (state->NumInstrs < 0x400000) 705 if (state->NumInstrs < 0x400000)
706 { 706 {
707 //exit(-1); 707 //exit(-1);
708 } 708 }
709 } 709 }
710#endif 710#endif
711 711
712 if (state->EventSet) 712 if (state->EventSet)
713 ARMul_EnvokeEvent (state); 713 ARMul_EnvokeEvent (state);
714 714
715#if 0 715#if 0
716 /* do profiling for code coverage */ 716 /* do profiling for code coverage */
717 if (skyeye_config.code_cov.prof_on) 717 if (skyeye_config.code_cov.prof_on)
718 cov_prof(EXEC_FLAG, pc); 718 cov_prof(EXEC_FLAG, pc);
719#endif 719#endif
720//2003-07-11 chy: for test 720//2003-07-11 chy: for test
721#if 0 721#if 0
722 if (skyeye_config.log.logon >= 1) { 722 if (skyeye_config.log.logon >= 1) {
723 if (state->NumInstrs >= skyeye_config.log.start && 723 if (state->NumInstrs >= skyeye_config.log.start &&
724 state->NumInstrs <= skyeye_config.log.end) { 724 state->NumInstrs <= skyeye_config.log.end) {
725 static int mybegin = 0; 725 static int mybegin = 0;
726 static int myinstrnum = 0; 726 static int myinstrnum = 0;
727 if (mybegin == 0) 727 if (mybegin == 0)
728 mybegin = 1; 728 mybegin = 1;
729#if 0 729#if 0
730 if (state->NumInstrs == 3695) { 730 if (state->NumInstrs == 3695) {
731 printf ("***********SKYEYE: numinstr = 3695\n"); 731 printf ("***********SKYEYE: numinstr = 3695\n");
732 } 732 }
733 static int mybeg2 = 0; 733 static int mybeg2 = 0;
734 static int mybeg3 = 0; 734 static int mybeg3 = 0;
735 static int mybeg4 = 0; 735 static int mybeg4 = 0;
736 static int mybeg5 = 0; 736 static int mybeg5 = 0;
737 737
738 if (pc == 0xa0008000) { 738 if (pc == 0xa0008000) {
739 //mybegin=1; 739 //mybegin=1;
740 printf ("************SKYEYE: real vmlinux begin now numinstr is %llu ****************\n", state->NumInstrs); 740 printf ("************SKYEYE: real vmlinux begin now numinstr is %llu ****************\n", state->NumInstrs);
741 } 741 }
742 742
743 //chy 2003-09-02 test fiq 743 //chy 2003-09-02 test fiq
744 if (state->NumInstrs == 67347000) { 744 if (state->NumInstrs == 67347000) {
745 printf ("***********SKYEYE: numinstr = 67347000, begin log\n"); 745 printf ("***********SKYEYE: numinstr = 67347000, begin log\n");
746 mybegin = 1; 746 mybegin = 1;
747 } 747 }
748 if (pc == 0xc00087b4) { //numinstr=67348714 748 if (pc == 0xc00087b4) { //numinstr=67348714
749 mybegin = 1; 749 mybegin = 1;
750 printf ("************SKYEYE: test irq now numinstr is %llu ****************\n", state->NumInstrs); 750 printf ("************SKYEYE: test irq now numinstr is %llu ****************\n", state->NumInstrs);
751 } 751 }
752 if (pc == 0xc00087b8) { //in start_kernel::sti() 752 if (pc == 0xc00087b8) { //in start_kernel::sti()
753 mybeg4 = 1; 753 mybeg4 = 1;
754 printf ("************SKYEYE: startkerenl: sti now numinstr is %llu ********\n", state->NumInstrs); 754 printf ("************SKYEYE: startkerenl: sti now numinstr is %llu ********\n", state->NumInstrs);
755 } 755 }
756 /*if (pc==0xc001e4f4||pc==0xc001e4f8||pc==0xc001e4fc||pc==0xc001e500||pc==0xffff0004) { //MRA instr */ 756 /*if (pc==0xc001e4f4||pc==0xc001e4f8||pc==0xc001e4fc||pc==0xc001e500||pc==0xffff0004) { //MRA instr */
757 if (pc == 0xc001e500) { //MRA instr 757 if (pc == 0xc001e500) { //MRA instr
758 mybeg5 = 1; 758 mybeg5 = 1;
759 printf ("************SKYEYE: MRA instr now numinstr is %llu ********\n", state->NumInstrs); 759 printf ("************SKYEYE: MRA instr now numinstr is %llu ********\n", state->NumInstrs);
760 } 760 }
761 if (pc >= 0xc0000000 && mybeg2 == 0) { 761 if (pc >= 0xc0000000 && mybeg2 == 0) {
762 mybeg2 = 1; 762 mybeg2 = 1;
763 printf ("************SKYEYE: enable mmu&cache, now numinstr is %llu **************\n", state->NumInstrs); 763 printf ("************SKYEYE: enable mmu&cache, now numinstr is %llu **************\n", state->NumInstrs);
764 SKYEYE_OUTREGS (stderr); 764 SKYEYE_OUTREGS (stderr);
765 printf ("************************************************************************\n"); 765 printf ("************************************************************************\n");
766 } 766 }
767 //chy 2003-09-01 test after tlb-flush 767 //chy 2003-09-01 test after tlb-flush
768 if (pc == 0xc00261ac) { 768 if (pc == 0xc00261ac) {
769 //sleep(2); 769 //sleep(2);
770 mybeg3 = 1; 770 mybeg3 = 1;
771 printf ("************SKYEYE: after tlb-flush numinstr is %llu ****************\n", state->NumInstrs); 771 printf ("************SKYEYE: after tlb-flush numinstr is %llu ****************\n", state->NumInstrs);
772 } 772 }
773 if (mybeg3 == 1) { 773 if (mybeg3 == 1) {
774 SKYEYE_OUTREGS (skyeye_logfd); 774 SKYEYE_OUTREGS (skyeye_logfd);
775 SKYEYE_OUTMOREREGS (skyeye_logfd); 775 SKYEYE_OUTMOREREGS (skyeye_logfd);
776 fprintf (skyeye_logfd, "\n"); 776 fprintf (skyeye_logfd, "\n");
777 } 777 }
778#endif 778#endif
779 if (mybegin == 1) { 779 if (mybegin == 1) {
780 //fprintf(skyeye_logfd,"p %x,i %x,d %x,l %x,",pc,instr,decoded,loaded); 780 //fprintf(skyeye_logfd,"p %x,i %x,d %x,l %x,",pc,instr,decoded,loaded);
781 //chy for test 20050729 781 //chy for test 20050729
782 /*if (state->NumInstrs>=3302294) { 782 /*if (state->NumInstrs>=3302294) {
783 if (pc==0x100c9d4 && instr==0xe1b0f00e){ 783 if (pc==0x100c9d4 && instr==0xe1b0f00e){
784 chy_debug(); 784 chy_debug();
785 printf("*********************************************\n"); 785 printf("*********************************************\n");
786 printf("******SKYEYE N %llx :p %x,i %x\n SKYEYE******\n",state->NumInstrs,pc,instr); 786 printf("******SKYEYE N %llx :p %x,i %x\n SKYEYE******\n",state->NumInstrs,pc,instr);
787 printf("*********************************************\n"); 787 printf("*********************************************\n");
788 } 788 }
789 */ 789 */
790 if (skyeye_config.log.logon >= 1) 790 if (skyeye_config.log.logon >= 1)
791 /* 791 /*
792 fprintf (skyeye_logfd, 792 fprintf (skyeye_logfd,
793 "N %llx :p %x,i %x,", 793 "N %llx :p %x,i %x,",
794 state->NumInstrs, pc, 794 state->NumInstrs, pc,
795#ifdef MODET 795#ifdef MODET
796 TFLAG ? instr & 0xffff : instr 796 TFLAG ? instr & 0xffff : instr
797#else 797#else
798 instr 798 instr
799#endif 799#endif
800 ); 800 );
801 */ 801 */
802 fprintf(skyeye_logfd, "pc=0x%x,r3=0x%x\n", pc, state->Reg[3]); 802 fprintf(skyeye_logfd, "pc=0x%x,r3=0x%x\n", pc, state->Reg[3]);
803 if (skyeye_config.log.logon >= 2) 803 if (skyeye_config.log.logon >= 2)
804 SKYEYE_OUTREGS (skyeye_logfd); 804 SKYEYE_OUTREGS (skyeye_logfd);
805 if (skyeye_config.log.logon >= 3) 805 if (skyeye_config.log.logon >= 3)
806 SKYEYE_OUTMOREREGS 806 SKYEYE_OUTMOREREGS
807 (skyeye_logfd); 807 (skyeye_logfd);
808 //fprintf (skyeye_logfd, "\n"); 808 //fprintf (skyeye_logfd, "\n");
809 if (skyeye_config.log.length > 0) { 809 if (skyeye_config.log.length > 0) {
810 myinstrnum++; 810 myinstrnum++;
811 if (myinstrnum >= 811 if (myinstrnum >=
812 skyeye_config.log. 812 skyeye_config.log.
813 length) { 813 length) {
814 myinstrnum = 0; 814 myinstrnum = 0;
815 fflush (skyeye_logfd); 815 fflush (skyeye_logfd);
816 fseek (skyeye_logfd, 816 fseek (skyeye_logfd,
817 0L, SEEK_SET); 817 0L, SEEK_SET);
818 } 818 }
819 } 819 }
820 } 820 }
821 //SKYEYE_OUTREGS(skyeye_logfd); 821 //SKYEYE_OUTREGS(skyeye_logfd);
822 //SKYEYE_OUTMOREREGS(skyeye_logfd); 822 //SKYEYE_OUTMOREREGS(skyeye_logfd);
823 } 823 }
824 } 824 }
825#endif 825#endif
826#if 0 /* Enable this for a helpful bit of debugging when tracing is needed. */ 826#if 0 /* Enable this for a helpful bit of debugging when tracing is needed. */
827 fprintf (stderr, "pc: %x, instr: %x\n", pc & ~1, instr); 827 fprintf (stderr, "pc: %x, instr: %x\n", pc & ~1, instr);
828 if (instr == 0) 828 if (instr == 0)
829 abort (); 829 abort ();
830#endif 830#endif
831#if 0 /* Enable this code to help track down stack alignment bugs. */ 831#if 0 /* Enable this code to help track down stack alignment bugs. */
832 { 832 {
833 static ARMword old_sp = -1; 833 static ARMword old_sp = -1;
834 834
835 if (old_sp != state->Reg[13]) { 835 if (old_sp != state->Reg[13]) {
836 old_sp = state->Reg[13]; 836 old_sp = state->Reg[13];
837 fprintf (stderr, 837 fprintf (stderr,
838 "pc: %08x: SP set to %08x%s\n", 838 "pc: %08x: SP set to %08x%s\n",
839 pc & ~1, old_sp, 839 pc & ~1, old_sp,
840 (old_sp % 8) ? " [UNALIGNED!]" : ""); 840 (old_sp % 8) ? " [UNALIGNED!]" : "");
841 } 841 }
842 } 842 }
843#endif 843#endif
844 /* Any exceptions ? */ 844 /* Any exceptions ? */
845 if (state->NresetSig == LOW) { 845 if (state->NresetSig == LOW) {
846 ARMul_Abort (state, ARMul_ResetV); 846 ARMul_Abort (state, ARMul_ResetV);
847 847
848 /*added energy_prof statement by ksh in 2004-11-26 */ 848 /*added energy_prof statement by ksh in 2004-11-26 */
849 //chy 2005-07-28 for standalone 849 //chy 2005-07-28 for standalone
850 //ARMul_do_energy(state,instr,pc); 850 //ARMul_do_energy(state,instr,pc);
851 break; 851 break;
852 } 852 }
853 else if (!state->NfiqSig && !FFLAG) { 853 else if (!state->NfiqSig && !FFLAG) {
854 ARMul_Abort (state, ARMul_FIQV); 854 ARMul_Abort (state, ARMul_FIQV);
855 /*added energy_prof statement by ksh in 2004-11-26 */ 855 /*added energy_prof statement by ksh in 2004-11-26 */
856 //chy 2005-07-28 for standalone 856 //chy 2005-07-28 for standalone
857 //ARMul_do_energy(state,instr,pc); 857 //ARMul_do_energy(state,instr,pc);
858 break; 858 break;
859 } 859 }
860 else if (!state->NirqSig && !IFLAG) { 860 else if (!state->NirqSig && !IFLAG) {
861 ARMul_Abort (state, ARMul_IRQV); 861 ARMul_Abort (state, ARMul_IRQV);
862 /*added energy_prof statement by ksh in 2004-11-26 */ 862 /*added energy_prof statement by ksh in 2004-11-26 */
863 //chy 2005-07-28 for standalone 863 //chy 2005-07-28 for standalone
864 //ARMul_do_energy(state,instr,pc); 864 //ARMul_do_energy(state,instr,pc);
865 break; 865 break;
866 } 866 }
867 867
868//teawater add for arm2x86 2005.04.26------------------------------------------- 868//teawater add for arm2x86 2005.04.26-------------------------------------------
869#if 0 869#if 0
@@ -876,3737 +876,3737 @@ ARMul_Emulate26 (ARMul_State * state)
876 printf("\n"); 876 printf("\n");
877 } 877 }
878#endif 878#endif
879 if (state->tea_pc) { 879 if (state->tea_pc) {
880 int i; 880 int i;
881 881
882 if (state->tea_reg_fd) { 882 if (state->tea_reg_fd) {
883 fprintf (state->tea_reg_fd, "\n"); 883 fprintf (state->tea_reg_fd, "\n");
884 for (i = 0; i < 15; i++) { 884 for (i = 0; i < 15; i++) {
885 fprintf (state->tea_reg_fd, "%x,", 885 fprintf (state->tea_reg_fd, "%x,",
886 state->Reg[i]); 886 state->Reg[i]);
887 } 887 }
888 fprintf (state->tea_reg_fd, "%x,", pc); 888 fprintf (state->tea_reg_fd, "%x,", pc);
889 state->Cpsr = ARMul_GetCPSR (state); 889 state->Cpsr = ARMul_GetCPSR (state);
890 fprintf (state->tea_reg_fd, "%x\n", 890 fprintf (state->tea_reg_fd, "%x\n",
891 state->Cpsr); 891 state->Cpsr);
892 } 892 }
893 else { 893 else {
894 printf ("\n"); 894 printf ("\n");
895 for (i = 0; i < 15; i++) { 895 for (i = 0; i < 15; i++) {
896 printf ("%x,", state->Reg[i]); 896 printf ("%x,", state->Reg[i]);
897 } 897 }
898 printf ("%x,", pc); 898 printf ("%x,", pc);
899 state->Cpsr = ARMul_GetCPSR (state); 899 state->Cpsr = ARMul_GetCPSR (state);
900 printf ("%x\n", state->Cpsr); 900 printf ("%x\n", state->Cpsr);
901 } 901 }
902 } 902 }
903//AJ2D-------------------------------------------------------------------------- 903//AJ2D--------------------------------------------------------------------------
904 904
905 if (state->CallDebug > 0) { 905 if (state->CallDebug > 0) {
906 instr = ARMul_Debug (state, pc, instr); 906 instr = ARMul_Debug (state, pc, instr);
907 if (state->Emulate < ONCE) { 907 if (state->Emulate < ONCE) {
908 state->NextInstr = RESUME; 908 state->NextInstr = RESUME;
909 break; 909 break;
910 } 910 }
911 if (state->Debug) { 911 if (state->Debug) {
912 fprintf (stderr, 912 fprintf (stderr,
913 "sim: At %08lx Instr %08lx Mode %02lx\n", 913 "sim: At %08lx Instr %08lx Mode %02lx\n",
914 pc, instr, state->Mode); 914 pc, instr, state->Mode);
915 (void) fgetc (stdin); 915 (void) fgetc (stdin);
916 } 916 }
917 } 917 }
918 else if (state->Emulate < ONCE) { 918 else if (state->Emulate < ONCE) {
919 state->NextInstr = RESUME; 919 state->NextInstr = RESUME;
920 break; 920 break;
921 } 921 }
922 //io_do_cycle (state); 922 //io_do_cycle (state);
923 state->NumInstrs++; 923 state->NumInstrs++;
924 #if 0 924 #if 0
925 if (state->NumInstrs % 10000000 == 0) { 925 if (state->NumInstrs % 10000000 == 0) {
926 printf("10 MIPS instr have been executed\n"); 926 printf("10 MIPS instr have been executed\n");
927 } 927 }
928 #endif 928 #endif
929 929
930#ifdef MODET 930#ifdef MODET
931 /* Provide Thumb instruction decoding. If the processor is in Thumb 931 /* Provide Thumb instruction decoding. If the processor is in Thumb
932 mode, then we can simply decode the Thumb instruction, and map it 932 mode, then we can simply decode the Thumb instruction, and map it
933 to the corresponding ARM instruction (by directly loading the 933 to the corresponding ARM instruction (by directly loading the
934 instr variable, and letting the normal ARM simulator 934 instr variable, and letting the normal ARM simulator
935 execute). There are some caveats to ensure that the correct 935 execute). There are some caveats to ensure that the correct
936 pipelined PC value is used when executing Thumb code, and also for 936 pipelined PC value is used when executing Thumb code, and also for
937 dealing with the BL instruction. */ 937 dealing with the BL instruction. */
938 if (TFLAG) { 938 if (TFLAG) {
939 ARMword new; 939 ARMword new;
940 940
941 /* Check if in Thumb mode. */ 941 /* Check if in Thumb mode. */
942 switch (ARMul_ThumbDecode (state, pc, instr, &new)) { 942 switch (ARMul_ThumbDecode (state, pc, instr, &new)) {
943 case t_undefined: 943 case t_undefined:
944 /* This is a Thumb instruction. */ 944 /* This is a Thumb instruction. */
945 ARMul_UndefInstr (state, instr); 945 ARMul_UndefInstr (state, instr);
946 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext; 946 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext;
947 947
948 case t_branch: 948 case t_branch:
949 /* Already processed. */ 949 /* Already processed. */
950 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext; 950 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext;
951 951
952 case t_decoded: 952 case t_decoded:
953 /* ARM instruction available. */ 953 /* ARM instruction available. */
954 //printf("t decode %04lx -> %08lx\n", instr & 0xffff, new); 954 //printf("t decode %04lx -> %08lx\n", instr & 0xffff, new);
955 instr = new; 955 instr = new;
956 /* So continue instruction decoding. */ 956 /* So continue instruction decoding. */
957 break; 957 break;
958 default: 958 default:
959 break; 959 break;
960 } 960 }
961 } 961 }
962#endif 962#endif
963 963
964 /* Check the condition codes. */ 964 /* Check the condition codes. */
965 if ((temp = TOPBITS (28)) == AL) { 965 if ((temp = TOPBITS (28)) == AL) {
966 /* Vile deed in the need for speed. */ 966 /* Vile deed in the need for speed. */
967 goto mainswitch; 967 goto mainswitch;
968 } 968 }
969 969
970 /* Check the condition code. */ 970 /* Check the condition code. */
971 switch ((int) TOPBITS (28)) { 971 switch ((int) TOPBITS (28)) {
972 case AL: 972 case AL:
973 temp = TRUE; 973 temp = TRUE;
974 break; 974 break;
975 case NV: 975 case NV:
976 976
977 /* shenoubang add for armv7 instr dmb 2012-3-11 */ 977 /* shenoubang add for armv7 instr dmb 2012-3-11 */
978 if (state->is_v7) { 978 if (state->is_v7) {
979 if ((instr & 0x0fffff00) == 0x057ff000) { 979 if ((instr & 0x0fffff00) == 0x057ff000) {
980 switch((instr >> 4) & 0xf) { 980 switch((instr >> 4) & 0xf) {
981 case 4: /* dsb */ 981 case 4: /* dsb */
982 case 5: /* dmb */ 982 case 5: /* dmb */
983 case 6: /* isb */ 983 case 6: /* isb */
984 // TODO: do no implemented thes instr 984 // TODO: do no implemented thes instr
985 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext; 985 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext;
986 } 986 }
987 } 987 }
988 } 988 }
989 /* dyf add for armv6 instruct CPS 2010.9.17 */ 989 /* dyf add for armv6 instruct CPS 2010.9.17 */
990 if (state->is_v6) { 990 if (state->is_v6) {
991 /* clrex do nothing here temporary */ 991 /* clrex do nothing here temporary */
992 if (instr == 0xf57ff01f) { 992 if (instr == 0xf57ff01f) {
993 //printf("clrex \n"); 993 //printf("clrex \n");
994 ERROR_LOG(ARM11, "Instr = 0x%x, pc = 0x%x, clrex instr!!\n", instr, pc); 994 ERROR_LOG(ARM11, "Instr = 0x%x, pc = 0x%x, clrex instr!!\n", instr, pc);
995#if 0 995#if 0
996 int i; 996 int i;
997 for(i = 0; i < 128; i++){ 997 for(i = 0; i < 128; i++){
998 state->exclusive_tag_array[i] = 0xffffffff; 998 state->exclusive_tag_array[i] = 0xffffffff;
999 } 999 }
1000#endif 1000#endif
1001 /* shenoubang 2012-3-14 refer the dyncom_interpreter */ 1001 /* shenoubang 2012-3-14 refer the dyncom_interpreter */
1002 state->exclusive_tag_array[0] = 0xFFFFFFFF; 1002 state->exclusive_tag_array[0] = 0xFFFFFFFF;
1003 state->exclusive_access_state = 0; 1003 state->exclusive_access_state = 0;
1004 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext; 1004 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext;
1005 } 1005 }
1006 1006
1007 if (BITS(20, 27) == 0x10) { 1007 if (BITS(20, 27) == 0x10) {
1008 if (BIT(19)) { 1008 if (BIT(19)) {
1009 if (BIT(8)) { 1009 if (BIT(8)) {
1010 if (BIT(18)) 1010 if (BIT(18))
1011 state->Cpsr |= 1<<8; 1011 state->Cpsr |= 1<<8;
1012 else 1012 else
1013 state->Cpsr &= ~(1<<8); 1013 state->Cpsr &= ~(1<<8);
1014 } 1014 }
1015 if (BIT(7)) { 1015 if (BIT(7)) {
1016 if (BIT(18)) 1016 if (BIT(18))
1017 state->Cpsr |= 1<<7; 1017 state->Cpsr |= 1<<7;
1018 else 1018 else
1019 state->Cpsr &= ~(1<<7); 1019 state->Cpsr &= ~(1<<7);
1020 ASSIGNINT (state->Cpsr & INTBITS); 1020 ASSIGNINT (state->Cpsr & INTBITS);
1021 } 1021 }
1022 if (BIT(6)) { 1022 if (BIT(6)) {
1023 if (BIT(18)) 1023 if (BIT(18))
1024 state->Cpsr |= 1<<6; 1024 state->Cpsr |= 1<<6;
1025 else 1025 else
1026 state->Cpsr &= ~(1<<6); 1026 state->Cpsr &= ~(1<<6);
1027 ASSIGNINT (state->Cpsr & INTBITS); 1027 ASSIGNINT (state->Cpsr & INTBITS);
1028 } 1028 }
1029 } 1029 }
1030 if (BIT(17)) { 1030 if (BIT(17)) {
1031 state->Cpsr |= BITS(0, 4); 1031 state->Cpsr |= BITS(0, 4);
1032 printf("skyeye test state->Mode\n"); 1032 printf("skyeye test state->Mode\n");
1033 if (state->Mode != (state->Cpsr & MODEBITS)) { 1033 if (state->Mode != (state->Cpsr & MODEBITS)) {
1034 state->Mode = 1034 state->Mode =
1035 ARMul_SwitchMode (state, state->Mode, 1035 ARMul_SwitchMode (state, state->Mode,
1036 state->Cpsr & MODEBITS); 1036 state->Cpsr & MODEBITS);
1037 1037
1038 state->NtransSig = (state->Mode & 3) ? HIGH : LOW; 1038 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
1039 } 1039 }
1040 } 1040 }
1041 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext; 1041 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext;
1042 } 1042 }
1043 } 1043 }
1044 if (state->is_v5) { 1044 if (state->is_v5) {
1045 if (BITS (25, 27) == 5) { /* BLX(1) */ 1045 if (BITS (25, 27) == 5) { /* BLX(1) */
1046 ARMword dest; 1046 ARMword dest;
1047 1047
1048 state->Reg[14] = pc + 4; 1048 state->Reg[14] = pc + 4;
1049 1049
1050 /* Force entry into Thumb mode. */ 1050 /* Force entry into Thumb mode. */
1051 dest = pc + 8 + 1; 1051 dest = pc + 8 + 1;
1052 if (BIT (23)) 1052 if (BIT (23))
1053 dest += (NEGBRANCH + 1053 dest += (NEGBRANCH +
1054 (BIT (24) << 1)); 1054 (BIT (24) << 1));
1055 else 1055 else
1056 dest += POSBRANCH + 1056 dest += POSBRANCH +
1057 (BIT (24) << 1); 1057 (BIT (24) << 1);
1058 1058
1059 WriteR15Branch (state, dest); 1059 WriteR15Branch (state, dest);
1060 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext; 1060 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext;
1061 } 1061 }
1062 else if ((instr & 0xFC70F000) == 0xF450F000) { 1062 else if ((instr & 0xFC70F000) == 0xF450F000) {
1063 /* The PLD instruction. Ignored. */ 1063 /* The PLD instruction. Ignored. */
1064 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext; 1064 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext;
1065 } 1065 }
1066 else if (((instr & 0xfe500f00) == 0xfc100100) 1066 else if (((instr & 0xfe500f00) == 0xfc100100)
1067 || ((instr & 0xfe500f00) == 1067 || ((instr & 0xfe500f00) ==
1068 0xfc000100)) { 1068 0xfc000100)) {
1069 /* wldrw and wstrw are unconditional. */ 1069 /* wldrw and wstrw are unconditional. */
1070 goto mainswitch; 1070 goto mainswitch;
1071 } 1071 }
1072 else { 1072 else {
1073 /* UNDEFINED in v5, UNPREDICTABLE in v3, v4, non executed in v1, v2. */ 1073 /* UNDEFINED in v5, UNPREDICTABLE in v3, v4, non executed in v1, v2. */
1074 ARMul_UndefInstr (state, instr); 1074 ARMul_UndefInstr (state, instr);
1075 } 1075 }
1076 } 1076 }
1077 temp = FALSE; 1077 temp = FALSE;
1078 break; 1078 break;
1079 case EQ: 1079 case EQ:
1080 temp = ZFLAG; 1080 temp = ZFLAG;
1081 break; 1081 break;
1082 case NE: 1082 case NE:
1083 temp = !ZFLAG; 1083 temp = !ZFLAG;
1084 break; 1084 break;
1085 case VS: 1085 case VS:
1086 temp = VFLAG; 1086 temp = VFLAG;
1087 break; 1087 break;
1088 case VC: 1088 case VC:
1089 temp = !VFLAG; 1089 temp = !VFLAG;
1090 break; 1090 break;
1091 case MI: 1091 case MI:
1092 temp = NFLAG; 1092 temp = NFLAG;
1093 break; 1093 break;
1094 case PL: 1094 case PL:
1095 temp = !NFLAG; 1095 temp = !NFLAG;
1096 break; 1096 break;
1097 case CS: 1097 case CS:
1098 temp = CFLAG; 1098 temp = CFLAG;
1099 break; 1099 break;
1100 case CC: 1100 case CC:
1101 temp = !CFLAG; 1101 temp = !CFLAG;
1102 break; 1102 break;
1103 case HI: 1103 case HI:
1104 temp = (CFLAG && !ZFLAG); 1104 temp = (CFLAG && !ZFLAG);
1105 break; 1105 break;
1106 case LS: 1106 case LS:
1107 temp = (!CFLAG || ZFLAG); 1107 temp = (!CFLAG || ZFLAG);
1108 break; 1108 break;
1109 case GE: 1109 case GE:
1110 temp = ((!NFLAG && !VFLAG) || (NFLAG && VFLAG)); 1110 temp = ((!NFLAG && !VFLAG) || (NFLAG && VFLAG));
1111 break; 1111 break;
1112 case LT: 1112 case LT:
1113 temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)); 1113 temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG));
1114 break; 1114 break;
1115 case GT: 1115 case GT:
1116 temp = ((!NFLAG && !VFLAG && !ZFLAG) 1116 temp = ((!NFLAG && !VFLAG && !ZFLAG)
1117 || (NFLAG && VFLAG && !ZFLAG)); 1117 || (NFLAG && VFLAG && !ZFLAG));
1118 break; 1118 break;
1119 case LE: 1119 case LE:
1120 temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)) 1120 temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG))
1121 || ZFLAG; 1121 || ZFLAG;
1122 break; 1122 break;
1123 } /* cc check */ 1123 } /* cc check */
1124 1124
1125//chy 2003-08-24 now #if 0 .... #endif process cp14, cp15.reg14, I disable it... 1125//chy 2003-08-24 now #if 0 .... #endif process cp14, cp15.reg14, I disable it...
1126#if 0 1126#if 0
1127 /* Handle the Clock counter here. */ 1127 /* Handle the Clock counter here. */
1128 if (state->is_XScale) { 1128 if (state->is_XScale) {
1129 ARMword cp14r0; 1129 ARMword cp14r0;
1130 int ok; 1130 int ok;
1131 1131
1132 ok = state->CPRead[14] (state, 0, &cp14r0); 1132 ok = state->CPRead[14] (state, 0, &cp14r0);
1133 1133
1134 if (ok && (cp14r0 & ARMul_CP14_R0_ENABLE)) { 1134 if (ok && (cp14r0 & ARMul_CP14_R0_ENABLE)) {
1135 unsigned int newcycles, nowtime = 1135 unsigned int newcycles, nowtime =
1136 ARMul_Time (state); 1136 ARMul_Time (state);
1137 1137
1138 newcycles = nowtime - state->LastTime; 1138 newcycles = nowtime - state->LastTime;
1139 state->LastTime = nowtime; 1139 state->LastTime = nowtime;
1140 1140
1141 if (cp14r0 & ARMul_CP14_R0_CCD) { 1141 if (cp14r0 & ARMul_CP14_R0_CCD) {
1142 if (state->CP14R0_CCD == -1) 1142 if (state->CP14R0_CCD == -1)
1143 state->CP14R0_CCD = newcycles; 1143 state->CP14R0_CCD = newcycles;
1144 else 1144 else
1145 state->CP14R0_CCD += 1145 state->CP14R0_CCD +=
1146 newcycles; 1146 newcycles;
1147 1147
1148 if (state->CP14R0_CCD >= 64) { 1148 if (state->CP14R0_CCD >= 64) {
1149 newcycles = 0; 1149 newcycles = 0;
1150 1150
1151 while (state->CP14R0_CCD >= 1151 while (state->CP14R0_CCD >=
1152 64) 1152 64)
1153 state->CP14R0_CCD -= 1153 state->CP14R0_CCD -=
1154 64, 1154 64,
1155 newcycles++; 1155 newcycles++;
1156 1156
1157 goto check_PMUintr; 1157 goto check_PMUintr;
1158 } 1158 }
1159 } 1159 }
1160 else { 1160 else {
1161 ARMword cp14r1; 1161 ARMword cp14r1;
1162 int do_int = 0; 1162 int do_int = 0;
1163 1163
1164 state->CP14R0_CCD = -1; 1164 state->CP14R0_CCD = -1;
1165 check_PMUintr: 1165 check_PMUintr:
1166 cp14r0 |= ARMul_CP14_R0_FLAG2; 1166 cp14r0 |= ARMul_CP14_R0_FLAG2;
1167 (void) state->CPWrite[14] (state, 0, 1167 (void) state->CPWrite[14] (state, 0,
1168 cp14r0); 1168 cp14r0);
1169 1169
1170 ok = state->CPRead[14] (state, 1, 1170 ok = state->CPRead[14] (state, 1,
1171 &cp14r1); 1171 &cp14r1);
1172 1172
1173 /* Coded like this for portability. */ 1173 /* Coded like this for portability. */
1174 while (ok && newcycles) { 1174 while (ok && newcycles) {
1175 if (cp14r1 == 0xffffffff) { 1175 if (cp14r1 == 0xffffffff) {
1176 cp14r1 = 0; 1176 cp14r1 = 0;
1177 do_int = 1; 1177 do_int = 1;
1178 } 1178 }
1179 else 1179 else
1180 cp14r1++; 1180 cp14r1++;
1181 1181
1182 newcycles--; 1182 newcycles--;
1183 } 1183 }
1184 1184
1185 (void) state->CPWrite[14] (state, 1, 1185 (void) state->CPWrite[14] (state, 1,
1186 cp14r1); 1186 cp14r1);
1187 1187
1188 if (do_int 1188 if (do_int
1189 && (cp14r0 & 1189 && (cp14r0 &
1190 ARMul_CP14_R0_INTEN2)) { 1190 ARMul_CP14_R0_INTEN2)) {
1191 ARMword temp; 1191 ARMword temp;
1192 1192
1193 if (state-> 1193 if (state->
1194 CPRead[13] (state, 8, 1194 CPRead[13] (state, 8,
1195 &temp) 1195 &temp)
1196 && (temp & 1196 && (temp &
1197 ARMul_CP13_R8_PMUS)) 1197 ARMul_CP13_R8_PMUS))
1198 ARMul_Abort (state, 1198 ARMul_Abort (state,
1199 ARMul_FIQV); 1199 ARMul_FIQV);
1200 else 1200 else
1201 ARMul_Abort (state, 1201 ARMul_Abort (state,
1202 ARMul_IRQV); 1202 ARMul_IRQV);
1203 } 1203 }
1204 } 1204 }
1205 } 1205 }
1206 } 1206 }
1207 1207
1208 /* Handle hardware instructions breakpoints here. */ 1208 /* Handle hardware instructions breakpoints here. */
1209 if (state->is_XScale) { 1209 if (state->is_XScale) {
1210 if ((pc | 3) == (read_cp15_reg (14, 0, 8) | 2) 1210 if ((pc | 3) == (read_cp15_reg (14, 0, 8) | 2)
1211 || (pc | 3) == (read_cp15_reg (14, 0, 9) | 2)) { 1211 || (pc | 3) == (read_cp15_reg (14, 0, 9) | 2)) {
1212 if (XScale_debug_moe 1212 if (XScale_debug_moe
1213 (state, ARMul_CP14_R10_MOE_IB)) 1213 (state, ARMul_CP14_R10_MOE_IB))
1214 ARMul_OSHandleSWI (state, 1214 ARMul_OSHandleSWI (state,
1215 SWI_Breakpoint); 1215 SWI_Breakpoint);
1216 } 1216 }
1217 } 1217 }
1218#endif 1218#endif
1219 1219
1220 /* Actual execution of instructions begins here. */ 1220 /* Actual execution of instructions begins here. */
1221 /* If the condition codes don't match, stop here. */ 1221 /* If the condition codes don't match, stop here. */
1222 if (temp) { 1222 if (temp) {
1223 mainswitch: 1223 mainswitch:
1224 1224
1225 if (state->is_XScale) { 1225 if (state->is_XScale) {
1226 if (BIT (20) == 0 && BITS (25, 27) == 0) { 1226 if (BIT (20) == 0 && BITS (25, 27) == 0) {
1227 if (BITS (4, 7) == 0xD) { 1227 if (BITS (4, 7) == 0xD) {
1228 /* XScale Load Consecutive insn. */ 1228 /* XScale Load Consecutive insn. */
1229 ARMword temp = 1229 ARMword temp =
1230 GetLS7RHS (state, 1230 GetLS7RHS (state,
1231 instr); 1231 instr);
1232 ARMword temp2 = 1232 ARMword temp2 =
1233 BIT (23) ? LHS + 1233 BIT (23) ? LHS +
1234 temp : LHS - temp; 1234 temp : LHS - temp;
1235 ARMword addr = 1235 ARMword addr =
1236 BIT (24) ? temp2 : 1236 BIT (24) ? temp2 :
1237 LHS; 1237 LHS;
1238 1238
1239 if (BIT (12)) 1239 if (BIT (12))
1240 ARMul_UndefInstr 1240 ARMul_UndefInstr
1241 (state, 1241 (state,
1242 instr); 1242 instr);
1243 else if (addr & 7) 1243 else if (addr & 7)
1244 /* Alignment violation. */ 1244 /* Alignment violation. */
1245 ARMul_Abort (state, 1245 ARMul_Abort (state,
1246 ARMul_DataAbortV); 1246 ARMul_DataAbortV);
1247 else { 1247 else {
1248 int wb = BIT (21) 1248 int wb = BIT (21)
1249 || 1249 ||
1250 (!BIT (24)); 1250 (!BIT (24));
1251 1251
1252 state->Reg[BITS 1252 state->Reg[BITS
1253 (12, 15)] = 1253 (12, 15)] =
1254 ARMul_LoadWordN 1254 ARMul_LoadWordN
1255 (state, addr); 1255 (state, addr);
1256 state->Reg[BITS 1256 state->Reg[BITS
1257 (12, 1257 (12,
1258 15) + 1] = 1258 15) + 1] =
1259 ARMul_LoadWordN 1259 ARMul_LoadWordN
1260 (state, 1260 (state,
1261 addr + 4); 1261 addr + 4);
1262 if (wb) 1262 if (wb)
1263 LSBase = temp2; 1263 LSBase = temp2;
1264 } 1264 }
1265 1265
1266 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext; 1266 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext;
1267 } 1267 }
1268 else if (BITS (4, 7) == 0xF) { 1268 else if (BITS (4, 7) == 0xF) {
1269 /* XScale Store Consecutive insn. */ 1269 /* XScale Store Consecutive insn. */
1270 ARMword temp = 1270 ARMword temp =
1271 GetLS7RHS (state, 1271 GetLS7RHS (state,
1272 instr); 1272 instr);
1273 ARMword temp2 = 1273 ARMword temp2 =
1274 BIT (23) ? LHS + 1274 BIT (23) ? LHS +
1275 temp : LHS - temp; 1275 temp : LHS - temp;
1276 ARMword addr = 1276 ARMword addr =
1277 BIT (24) ? temp2 : 1277 BIT (24) ? temp2 :
1278 LHS; 1278 LHS;
1279 1279
1280 if (BIT (12)) 1280 if (BIT (12))
1281 ARMul_UndefInstr 1281 ARMul_UndefInstr
1282 (state, 1282 (state,
1283 instr); 1283 instr);
1284 else if (addr & 7) 1284 else if (addr & 7)
1285 /* Alignment violation. */ 1285 /* Alignment violation. */
1286 ARMul_Abort (state, 1286 ARMul_Abort (state,
1287 ARMul_DataAbortV); 1287 ARMul_DataAbortV);
1288 else { 1288 else {
1289 ARMul_StoreWordN 1289 ARMul_StoreWordN
1290 (state, addr, 1290 (state, addr,
1291 state-> 1291 state->
1292 Reg[BITS 1292 Reg[BITS
1293 (12, 1293 (12,
1294 15)]); 1294 15)]);
1295 ARMul_StoreWordN 1295 ARMul_StoreWordN
1296 (state, 1296 (state,
1297 addr + 4, 1297 addr + 4,
1298 state-> 1298 state->
1299 Reg[BITS 1299 Reg[BITS
1300 (12, 1300 (12,
1301 15) + 1301 15) +
1302 1]); 1302 1]);
1303 1303
1304 if (BIT (21) 1304 if (BIT (21)
1305 || !BIT (24)) 1305 || !BIT (24))
1306 LSBase = temp2; 1306 LSBase = temp2;
1307 } 1307 }
1308 1308
1309 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext; 1309 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext;
1310 } 1310 }
1311 } 1311 }
1312 //chy 2003-09-03 TMRRC(iwmmxt.c) and MRA has the same decoded instr???? 1312 //chy 2003-09-03 TMRRC(iwmmxt.c) and MRA has the same decoded instr????
1313 //Now, I commit iwmmxt process, may be future, I will change it!!!! 1313 //Now, I commit iwmmxt process, may be future, I will change it!!!!
1314 //if (ARMul_HandleIwmmxt (state, instr)) 1314 //if (ARMul_HandleIwmmxt (state, instr))
1315 // _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext; 1315 // _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext;
1316 } 1316 }
1317 1317
1318 /* shenoubang sbfx and ubfx instr 2012-3-16 */ 1318 /* shenoubang sbfx and ubfx instr 2012-3-16 */
1319 if (state->is_v6) { 1319 if (state->is_v6) {
1320 unsigned int m, lsb, width, Rd, Rn, data; 1320 unsigned int m, lsb, width, Rd, Rn, data;
1321 Rd = Rn = lsb = width = data = m = 0; 1321 Rd = Rn = lsb = width = data = m = 0;
1322 1322
1323 //printf("helloworld\n"); 1323 //printf("helloworld\n");
1324 if ((((int) BITS (21, 27)) == 0x3f) && (((int) BITS (4, 6)) == 0x5)) { 1324 if ((((int) BITS (21, 27)) == 0x3f) && (((int) BITS (4, 6)) == 0x5)) {
1325 m = (unsigned)BITS(7, 11); 1325 m = (unsigned)BITS(7, 11);
1326 width = (unsigned)BITS(16, 20); 1326 width = (unsigned)BITS(16, 20);
1327 Rd = (unsigned)BITS(12, 15); 1327 Rd = (unsigned)BITS(12, 15);
1328 Rn = (unsigned)BITS(0, 3); 1328 Rn = (unsigned)BITS(0, 3);
1329 if ((Rd == 15) || (Rn == 15)) { 1329 if ((Rd == 15) || (Rn == 15)) {
1330 ARMul_UndefInstr (state, instr); 1330 ARMul_UndefInstr (state, instr);
1331 } 1331 }
1332 else if ((m + width) < 32) { 1332 else if ((m + width) < 32) {
1333 data = state->Reg[Rn]; 1333 data = state->Reg[Rn];
1334 state->Reg[Rd] ^= state->Reg[Rd]; 1334 state->Reg[Rd] ^= state->Reg[Rd];
1335 state->Reg[Rd] = 1335 state->Reg[Rd] =
1336 ((ARMword)(data << (31 -(m + width))) >> ((31 - (m + width)) + (m))); 1336 ((ARMword)(data << (31 -(m + width))) >> ((31 - (m + width)) + (m)));
1337 //SKYEYE_LOG_IN_CLR(RED, "UBFX: In %s, line = %d, Reg_src[%d] = 0x%x, Reg_d[%d] = 0x%x, m = %d, width = %d, Rd = %d, Rn = %d\n", 1337 //SKYEYE_LOG_IN_CLR(RED, "UBFX: In %s, line = %d, Reg_src[%d] = 0x%x, Reg_d[%d] = 0x%x, m = %d, width = %d, Rd = %d, Rn = %d\n",
1338 // __FUNCTION__, __LINE__, Rn, data, Rd, state->Reg[Rd], m, width + 1, Rd, Rn); 1338 // __FUNCTION__, __LINE__, Rn, data, Rd, state->Reg[Rd], m, width + 1, Rd, Rn);
1339 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext; 1339 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext;
1340 } 1340 }
1341 } // ubfx instr 1341 } // ubfx instr
1342 else if ((((int) BITS (21, 27)) == 0x3d) && (((int) BITS (4, 6)) == 0x5)) { 1342 else if ((((int) BITS (21, 27)) == 0x3d) && (((int) BITS (4, 6)) == 0x5)) {
1343 int tmp = 0; 1343 int tmp = 0;
1344 Rd = BITS(12, 15); Rn = BITS(0, 3); 1344 Rd = BITS(12, 15); Rn = BITS(0, 3);
1345 lsb = BITS(7, 11); width = BITS(16, 20); 1345 lsb = BITS(7, 11); width = BITS(16, 20);
1346 if ((Rd == 15) || (Rn == 15)) { 1346 if ((Rd == 15) || (Rn == 15)) {
1347 ARMul_UndefInstr (state, instr); 1347 ARMul_UndefInstr (state, instr);
1348 } 1348 }
1349 else if ((lsb + width) < 32) { 1349 else if ((lsb + width) < 32) {
1350 state->Reg[Rd] ^= state->Reg[Rd]; 1350 state->Reg[Rd] ^= state->Reg[Rd];
1351 data = state->Reg[Rn]; 1351 data = state->Reg[Rn];
1352 tmp = (data << (32 - (lsb + width + 1))); 1352 tmp = (data << (32 - (lsb + width + 1)));
1353 state->Reg[Rd] = (tmp >> (32 - (lsb + width + 1))); 1353 state->Reg[Rd] = (tmp >> (32 - (lsb + width + 1)));
1354 //SKYEYE_LOG_IN_CLR(RED, "sbfx: In %s, line = %d, pc = 0x%x, instr = 0x%x,Rd = 0x%x, \ 1354 //SKYEYE_LOG_IN_CLR(RED, "sbfx: In %s, line = %d, pc = 0x%x, instr = 0x%x,Rd = 0x%x, \
1355 Rn = 0x%x, lsb = %d, width = %d, Rs[%d] = 0x%x, Rd[%d] = 0x%x\n", 1355 Rn = 0x%x, lsb = %d, width = %d, Rs[%d] = 0x%x, Rd[%d] = 0x%x\n",
1356 // __func__, __LINE__, pc, instr, Rd, Rn, lsb, width + 1, Rn, state->Reg[Rn], Rd, state->Reg[Rd]); 1356 // __func__, __LINE__, pc, instr, Rd, Rn, lsb, width + 1, Rn, state->Reg[Rn], Rd, state->Reg[Rd]);
1357 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext; 1357 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext;
1358 } 1358 }
1359 } // sbfx instr 1359 } // sbfx instr
1360 else if ((((int)BITS(21, 27)) == 0x3e) && ((int)BITS(4, 6) == 0x1)) { 1360 else if ((((int)BITS(21, 27)) == 0x3e) && ((int)BITS(4, 6) == 0x1)) {
1361 //(ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) 1361 //(ARMword)(instr<<(31-(n))) >> ((31-(n))+(m))
1362 unsigned msb ,tmp_rn, tmp_rd, dst; 1362 unsigned msb ,tmp_rn, tmp_rd, dst;
1363 msb = tmp_rd = tmp_rn = dst = 0; 1363 msb = tmp_rd = tmp_rn = dst = 0;
1364 Rd = BITS(12, 15); Rn = BITS(0, 3); 1364 Rd = BITS(12, 15); Rn = BITS(0, 3);
1365 lsb = BITS(7, 11); msb = BITS(16, 20); 1365 lsb = BITS(7, 11); msb = BITS(16, 20);
1366 if ((Rd == 15)) { 1366 if ((Rd == 15)) {
1367 ARMul_UndefInstr (state, instr); 1367 ARMul_UndefInstr (state, instr);
1368 } 1368 }
1369 else if ((Rn == 15)) { 1369 else if ((Rn == 15)) {
1370 data = state->Reg[Rd]; 1370 data = state->Reg[Rd];
1371 tmp_rd = ((ARMword)(data << (31 - lsb)) >> (31 - lsb)); 1371 tmp_rd = ((ARMword)(data << (31 - lsb)) >> (31 - lsb));
1372 dst = ((data >> msb) << (msb - lsb)); 1372 dst = ((data >> msb) << (msb - lsb));
1373 dst = (dst << lsb) | tmp_rd; 1373 dst = (dst << lsb) | tmp_rd;
1374 DEBUG_LOG(ARM11, "BFC instr: msb = %d, lsb = %d, Rd[%d] : 0x%x, dst = 0x%x\n", 1374 DEBUG_LOG(ARM11, "BFC instr: msb = %d, lsb = %d, Rd[%d] : 0x%x, dst = 0x%x\n",
1375 msb, lsb, Rd, state->Reg[Rd], dst); 1375 msb, lsb, Rd, state->Reg[Rd], dst);
1376 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext; 1376 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext;
1377 } // bfc instr 1377 } // bfc instr
1378 else if (((msb >= lsb) && (msb < 32))) { 1378 else if (((msb >= lsb) && (msb < 32))) {
1379 data = state->Reg[Rn]; 1379 data = state->Reg[Rn];
1380 tmp_rn = ((ARMword)(data << (31 - (msb - lsb))) >> (31 - (msb - lsb))); 1380 tmp_rn = ((ARMword)(data << (31 - (msb - lsb))) >> (31 - (msb - lsb)));
1381 data = state->Reg[Rd]; 1381 data = state->Reg[Rd];
1382 tmp_rd = ((ARMword)(data << (31 - lsb)) >> (31 - lsb)); 1382 tmp_rd = ((ARMword)(data << (31 - lsb)) >> (31 - lsb));
1383 dst = ((data >> msb) << (msb - lsb)) | tmp_rn; 1383 dst = ((data >> msb) << (msb - lsb)) | tmp_rn;
1384 dst = (dst << lsb) | tmp_rd; 1384 dst = (dst << lsb) | tmp_rd;
1385 DEBUG_LOG(ARM11, "BFI instr:msb = %d, lsb = %d, Rd[%d] : 0x%x, Rn[%d]: 0x%x, dst = 0x%x\n", 1385 DEBUG_LOG(ARM11, "BFI instr:msb = %d, lsb = %d, Rd[%d] : 0x%x, Rn[%d]: 0x%x, dst = 0x%x\n",
1386 msb, lsb, Rd, state->Reg[Rd], Rn, state->Reg[Rn], dst); 1386 msb, lsb, Rd, state->Reg[Rd], Rn, state->Reg[Rn], dst);
1387 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext; 1387 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext;
1388 } // bfi instr 1388 } // bfi instr
1389 } 1389 }
1390 } 1390 }
1391 1391
1392 switch ((int) BITS (20, 27)) { 1392 switch ((int) BITS (20, 27)) {
1393 /* Data Processing Register RHS Instructions. */ 1393 /* Data Processing Register RHS Instructions. */
1394 1394
1395 case 0x00: /* AND reg and MUL */ 1395 case 0x00: /* AND reg and MUL */
1396#ifdef MODET 1396#ifdef MODET
1397 if (BITS (4, 11) == 0xB) { 1397 if (BITS (4, 11) == 0xB) {
1398 /* STRH register offset, no write-back, down, post indexed. */ 1398 /* STRH register offset, no write-back, down, post indexed. */
1399 SHDOWNWB (); 1399 SHDOWNWB ();
1400 break; 1400 break;
1401 } 1401 }
1402 if (BITS (4, 7) == 0xD) { 1402 if (BITS (4, 7) == 0xD) {
1403 Handle_Load_Double (state, instr); 1403 Handle_Load_Double (state, instr);
1404 break; 1404 break;
1405 } 1405 }
1406 if (BITS (4, 7) == 0xF) { 1406 if (BITS (4, 7) == 0xF) {
1407 Handle_Store_Double (state, instr); 1407 Handle_Store_Double (state, instr);
1408 break; 1408 break;
1409 } 1409 }
1410#endif 1410#endif
1411 if (BITS (4, 7) == 9) { 1411 if (BITS (4, 7) == 9) {
1412 /* MUL */ 1412 /* MUL */
1413 rhs = state->Reg[MULRHSReg]; 1413 rhs = state->Reg[MULRHSReg];
1414 //if (MULLHSReg == MULDESTReg) { 1414 //if (MULLHSReg == MULDESTReg) {
1415 if(0){ /* For armv6, the restriction is removed */ 1415 if(0){ /* For armv6, the restriction is removed */
1416 UNDEF_MULDestEQOp1; 1416 UNDEF_MULDestEQOp1;
1417 state->Reg[MULDESTReg] = 0; 1417 state->Reg[MULDESTReg] = 0;
1418 } 1418 }
1419 else if (MULDESTReg != 15) 1419 else if (MULDESTReg != 15)
1420 state->Reg[MULDESTReg] = 1420 state->Reg[MULDESTReg] =
1421 state-> 1421 state->
1422 Reg[MULLHSReg] * rhs; 1422 Reg[MULLHSReg] * rhs;
1423 else 1423 else
1424 UNDEF_MULPCDest; 1424 UNDEF_MULPCDest;
1425 1425
1426 for (dest = 0, temp = 0; dest < 32; 1426 for (dest = 0, temp = 0; dest < 32;
1427 dest++) 1427 dest++)
1428 if (rhs & (1L << dest)) 1428 if (rhs & (1L << dest))
1429 temp = dest; 1429 temp = dest;
1430 1430
1431 /* Mult takes this many/2 I cycles. */ 1431 /* Mult takes this many/2 I cycles. */
1432 ARMul_Icycles (state, 1432 ARMul_Icycles (state,
1433 ARMul_MultTable[temp], 1433 ARMul_MultTable[temp],
1434 0L); 1434 0L);
1435 } 1435 }
1436 else { 1436 else {
1437 /* AND reg. */ 1437 /* AND reg. */
1438 rhs = DPRegRHS; 1438 rhs = DPRegRHS;
1439 dest = LHS & rhs; 1439 dest = LHS & rhs;
1440 WRITEDEST (dest); 1440 WRITEDEST (dest);
1441 } 1441 }
1442 break; 1442 break;
1443 1443
1444 case 0x01: /* ANDS reg and MULS */ 1444 case 0x01: /* ANDS reg and MULS */
1445#ifdef MODET 1445#ifdef MODET
1446 if ((BITS (4, 11) & 0xF9) == 0x9) 1446 if ((BITS (4, 11) & 0xF9) == 0x9)
1447 /* LDR register offset, no write-back, down, post indexed. */ 1447 /* LDR register offset, no write-back, down, post indexed. */
1448 LHPOSTDOWN (); 1448 LHPOSTDOWN ();
1449 /* Fall through to rest of decoding. */ 1449 /* Fall through to rest of decoding. */
1450#endif 1450#endif
1451 if (BITS (4, 7) == 9) { 1451 if (BITS (4, 7) == 9) {
1452 /* MULS */ 1452 /* MULS */
1453 rhs = state->Reg[MULRHSReg]; 1453 rhs = state->Reg[MULRHSReg];
1454 1454
1455 //if (MULLHSReg == MULDESTReg) { 1455 //if (MULLHSReg == MULDESTReg) {
1456 if(0){ 1456 if(0){
1457 printf("Something in %d line\n", __LINE__); 1457 printf("Something in %d line\n", __LINE__);
1458 UNDEF_WARNING; 1458 UNDEF_WARNING;
1459 UNDEF_MULDestEQOp1; 1459 UNDEF_MULDestEQOp1;
1460 state->Reg[MULDESTReg] = 0; 1460 state->Reg[MULDESTReg] = 0;
1461 CLEARN; 1461 CLEARN;
1462 SETZ; 1462 SETZ;
1463 } 1463 }
1464 else if (MULDESTReg != 15) { 1464 else if (MULDESTReg != 15) {
1465 dest = state->Reg[MULLHSReg] * 1465 dest = state->Reg[MULLHSReg] *
1466 rhs; 1466 rhs;
1467 ARMul_NegZero (state, dest); 1467 ARMul_NegZero (state, dest);
1468 state->Reg[MULDESTReg] = dest; 1468 state->Reg[MULDESTReg] = dest;
1469 } 1469 }
1470 else 1470 else
1471 UNDEF_MULPCDest; 1471 UNDEF_MULPCDest;
1472 1472
1473 for (dest = 0, temp = 0; dest < 32; 1473 for (dest = 0, temp = 0; dest < 32;
1474 dest++) 1474 dest++)
1475 if (rhs & (1L << dest)) 1475 if (rhs & (1L << dest))
1476 temp = dest; 1476 temp = dest;
1477 1477
1478 /* Mult takes this many/2 I cycles. */ 1478 /* Mult takes this many/2 I cycles. */
1479 ARMul_Icycles (state, 1479 ARMul_Icycles (state,
1480 ARMul_MultTable[temp], 1480 ARMul_MultTable[temp],
1481 0L); 1481 0L);
1482 } 1482 }
1483 else { 1483 else {
1484 /* ANDS reg. */ 1484 /* ANDS reg. */
1485 rhs = DPSRegRHS; 1485 rhs = DPSRegRHS;
1486 dest = LHS & rhs; 1486 dest = LHS & rhs;
1487 WRITESDEST (dest); 1487 WRITESDEST (dest);
1488 } 1488 }
1489 break; 1489 break;
1490 1490
1491 case 0x02: /* EOR reg and MLA */ 1491 case 0x02: /* EOR reg and MLA */
1492#ifdef MODET 1492#ifdef MODET
1493 if (BITS (4, 11) == 0xB) { 1493 if (BITS (4, 11) == 0xB) {
1494 /* STRH register offset, write-back, down, post indexed. */ 1494 /* STRH register offset, write-back, down, post indexed. */
1495 SHDOWNWB (); 1495 SHDOWNWB ();
1496 break; 1496 break;
1497 } 1497 }
1498#endif 1498#endif
1499 if (BITS (4, 7) == 9) { /* MLA */ 1499 if (BITS (4, 7) == 9) { /* MLA */
1500 rhs = state->Reg[MULRHSReg]; 1500 rhs = state->Reg[MULRHSReg];
1501 #if 0 1501 #if 0
1502 if (MULLHSReg == MULDESTReg) { 1502 if (MULLHSReg == MULDESTReg) {
1503 UNDEF_MULDestEQOp1; 1503 UNDEF_MULDestEQOp1;
1504 state->Reg[MULDESTReg] = 1504 state->Reg[MULDESTReg] =
1505 state->Reg[MULACCReg]; 1505 state->Reg[MULACCReg];
1506 } 1506 }
1507 else if (MULDESTReg != 15){ 1507 else if (MULDESTReg != 15){
1508 #endif 1508 #endif
1509 if (MULDESTReg != 15){ 1509 if (MULDESTReg != 15){
1510 state->Reg[MULDESTReg] = 1510 state->Reg[MULDESTReg] =
1511 state-> 1511 state->
1512 Reg[MULLHSReg] * rhs + 1512 Reg[MULLHSReg] * rhs +
1513 state->Reg[MULACCReg]; 1513 state->Reg[MULACCReg];
1514 } 1514 }
1515 else 1515 else
1516 UNDEF_MULPCDest; 1516 UNDEF_MULPCDest;
1517 1517
1518 for (dest = 0, temp = 0; dest < 32; 1518 for (dest = 0, temp = 0; dest < 32;
1519 dest++) 1519 dest++)
1520 if (rhs & (1L << dest)) 1520 if (rhs & (1L << dest))
1521 temp = dest; 1521 temp = dest;
1522 1522
1523 /* Mult takes this many/2 I cycles. */ 1523 /* Mult takes this many/2 I cycles. */
1524 ARMul_Icycles (state, 1524 ARMul_Icycles (state,
1525 ARMul_MultTable[temp], 1525 ARMul_MultTable[temp],
1526 0L); 1526 0L);
1527 } 1527 }
1528 else { 1528 else {
1529 rhs = DPRegRHS; 1529 rhs = DPRegRHS;
1530 dest = LHS ^ rhs; 1530 dest = LHS ^ rhs;
1531 WRITEDEST (dest); 1531 WRITEDEST (dest);
1532 } 1532 }
1533 break; 1533 break;
1534 1534
1535 case 0x03: /* EORS reg and MLAS */ 1535 case 0x03: /* EORS reg and MLAS */
1536#ifdef MODET 1536#ifdef MODET
1537 if ((BITS (4, 11) & 0xF9) == 0x9) 1537 if ((BITS (4, 11) & 0xF9) == 0x9)
1538 /* LDR register offset, write-back, down, post-indexed. */ 1538 /* LDR register offset, write-back, down, post-indexed. */
1539 LHPOSTDOWN (); 1539 LHPOSTDOWN ();
1540 /* Fall through to rest of the decoding. */ 1540 /* Fall through to rest of the decoding. */
1541#endif 1541#endif
1542 if (BITS (4, 7) == 9) { 1542 if (BITS (4, 7) == 9) {
1543 /* MLAS */ 1543 /* MLAS */
1544 rhs = state->Reg[MULRHSReg]; 1544 rhs = state->Reg[MULRHSReg];
1545 //if (MULLHSReg == MULDESTReg) { 1545 //if (MULLHSReg == MULDESTReg) {
1546 if (0) { 1546 if (0) {
1547 UNDEF_MULDestEQOp1; 1547 UNDEF_MULDestEQOp1;
1548 dest = state->Reg[MULACCReg]; 1548 dest = state->Reg[MULACCReg];
1549 ARMul_NegZero (state, dest); 1549 ARMul_NegZero (state, dest);
1550 state->Reg[MULDESTReg] = dest; 1550 state->Reg[MULDESTReg] = dest;
1551 } 1551 }
1552 else if (MULDESTReg != 15) { 1552 else if (MULDESTReg != 15) {
1553 dest = state->Reg[MULLHSReg] * 1553 dest = state->Reg[MULLHSReg] *
1554 rhs + 1554 rhs +
1555 state->Reg[MULACCReg]; 1555 state->Reg[MULACCReg];
1556 ARMul_NegZero (state, dest); 1556 ARMul_NegZero (state, dest);
1557 state->Reg[MULDESTReg] = dest; 1557 state->Reg[MULDESTReg] = dest;
1558 } 1558 }
1559 else 1559 else
1560 UNDEF_MULPCDest; 1560 UNDEF_MULPCDest;
1561 1561
1562 for (dest = 0, temp = 0; dest < 32; 1562 for (dest = 0, temp = 0; dest < 32;
1563 dest++) 1563 dest++)
1564 if (rhs & (1L << dest)) 1564 if (rhs & (1L << dest))
1565 temp = dest; 1565 temp = dest;
1566 1566
1567 /* Mult takes this many/2 I cycles. */ 1567 /* Mult takes this many/2 I cycles. */
1568 ARMul_Icycles (state, 1568 ARMul_Icycles (state,
1569 ARMul_MultTable[temp], 1569 ARMul_MultTable[temp],
1570 0L); 1570 0L);
1571 } 1571 }
1572 else { 1572 else {
1573 /* EORS Reg. */ 1573 /* EORS Reg. */
1574 rhs = DPSRegRHS; 1574 rhs = DPSRegRHS;
1575 dest = LHS ^ rhs; 1575 dest = LHS ^ rhs;
1576 WRITESDEST (dest); 1576 WRITESDEST (dest);
1577 } 1577 }
1578 break; 1578 break;
1579 1579
1580 case 0x04: /* SUB reg */ 1580 case 0x04: /* SUB reg */
1581#ifdef MODET 1581#ifdef MODET
1582 if (BITS (4, 7) == 0xB) { 1582 if (BITS (4, 7) == 0xB) {
1583 /* STRH immediate offset, no write-back, down, post indexed. */ 1583 /* STRH immediate offset, no write-back, down, post indexed. */
1584 SHDOWNWB (); 1584 SHDOWNWB ();
1585 break; 1585 break;
1586 } 1586 }
1587 if (BITS (4, 7) == 0xD) { 1587 if (BITS (4, 7) == 0xD) {
1588 Handle_Load_Double (state, instr); 1588 Handle_Load_Double (state, instr);
1589 break; 1589 break;
1590 } 1590 }
1591 if (BITS (4, 7) == 0xF) { 1591 if (BITS (4, 7) == 0xF) {
1592 Handle_Store_Double (state, instr); 1592 Handle_Store_Double (state, instr);
1593 break; 1593 break;
1594 } 1594 }
1595#endif 1595#endif
1596 rhs = DPRegRHS; 1596 rhs = DPRegRHS;
1597 dest = LHS - rhs; 1597 dest = LHS - rhs;
1598 WRITEDEST (dest); 1598 WRITEDEST (dest);
1599 break; 1599 break;
1600 1600
1601 case 0x05: /* SUBS reg */ 1601 case 0x05: /* SUBS reg */
1602#ifdef MODET 1602#ifdef MODET
1603 if ((BITS (4, 7) & 0x9) == 0x9) 1603 if ((BITS (4, 7) & 0x9) == 0x9)
1604 /* LDR immediate offset, no write-back, down, post indexed. */ 1604 /* LDR immediate offset, no write-back, down, post indexed. */
1605 LHPOSTDOWN (); 1605 LHPOSTDOWN ();
1606 /* Fall through to the rest of the instruction decoding. */ 1606 /* Fall through to the rest of the instruction decoding. */
1607#endif 1607#endif
1608 lhs = LHS; 1608 lhs = LHS;
1609 rhs = DPRegRHS; 1609 rhs = DPRegRHS;
1610 dest = lhs - rhs; 1610 dest = lhs - rhs;
1611 1611
1612 if ((lhs >= rhs) || ((rhs | lhs) >> 31)) { 1612 if ((lhs >= rhs) || ((rhs | lhs) >> 31)) {
1613 ARMul_SubCarry (state, lhs, rhs, 1613 ARMul_SubCarry (state, lhs, rhs,
1614 dest); 1614 dest);
1615 ARMul_SubOverflow (state, lhs, rhs, 1615 ARMul_SubOverflow (state, lhs, rhs,
1616 dest); 1616 dest);
1617 } 1617 }
1618 else { 1618 else {
1619 CLEARC; 1619 CLEARC;
1620 CLEARV; 1620 CLEARV;
1621 } 1621 }
1622 WRITESDEST (dest); 1622 WRITESDEST (dest);
1623 break; 1623 break;
1624 1624
1625 case 0x06: /* RSB reg */ 1625 case 0x06: /* RSB reg */
1626#ifdef MODET 1626#ifdef MODET
1627 if (BITS (4, 7) == 0xB) { 1627 if (BITS (4, 7) == 0xB) {
1628 /* STRH immediate offset, write-back, down, post indexed. */ 1628 /* STRH immediate offset, write-back, down, post indexed. */
1629 SHDOWNWB (); 1629 SHDOWNWB ();
1630 break; 1630 break;
1631 } 1631 }
1632#endif 1632#endif
1633 rhs = DPRegRHS; 1633 rhs = DPRegRHS;
1634 dest = rhs - LHS; 1634 dest = rhs - LHS;
1635 WRITEDEST (dest); 1635 WRITEDEST (dest);
1636 break; 1636 break;
1637 1637
1638 case 0x07: /* RSBS reg */ 1638 case 0x07: /* RSBS reg */
1639#ifdef MODET 1639#ifdef MODET
1640 if ((BITS (4, 7) & 0x9) == 0x9) 1640 if ((BITS (4, 7) & 0x9) == 0x9)
1641 /* LDR immediate offset, write-back, down, post indexed. */ 1641 /* LDR immediate offset, write-back, down, post indexed. */
1642 LHPOSTDOWN (); 1642 LHPOSTDOWN ();
1643 /* Fall through to remainder of instruction decoding. */ 1643 /* Fall through to remainder of instruction decoding. */
1644#endif 1644#endif
1645 lhs = LHS; 1645 lhs = LHS;
1646 rhs = DPRegRHS; 1646 rhs = DPRegRHS;
1647 dest = rhs - lhs; 1647 dest = rhs - lhs;
1648 1648
1649 if ((rhs >= lhs) || ((rhs | lhs) >> 31)) { 1649 if ((rhs >= lhs) || ((rhs | lhs) >> 31)) {
1650 ARMul_SubCarry (state, rhs, lhs, 1650 ARMul_SubCarry (state, rhs, lhs,
1651 dest); 1651 dest);
1652 ARMul_SubOverflow (state, rhs, lhs, 1652 ARMul_SubOverflow (state, rhs, lhs,
1653 dest); 1653 dest);
1654 } 1654 }
1655 else { 1655 else {
1656 CLEARC; 1656 CLEARC;
1657 CLEARV; 1657 CLEARV;
1658 } 1658 }
1659 WRITESDEST (dest); 1659 WRITESDEST (dest);
1660 break; 1660 break;
1661 1661
1662 case 0x08: /* ADD reg */ 1662 case 0x08: /* ADD reg */
1663#ifdef MODET 1663#ifdef MODET
1664 if (BITS (4, 11) == 0xB) { 1664 if (BITS (4, 11) == 0xB) {
1665 /* STRH register offset, no write-back, up, post indexed. */ 1665 /* STRH register offset, no write-back, up, post indexed. */
1666 SHUPWB (); 1666 SHUPWB ();
1667 break; 1667 break;
1668 } 1668 }
1669 if (BITS (4, 7) == 0xD) { 1669 if (BITS (4, 7) == 0xD) {
1670 Handle_Load_Double (state, instr); 1670 Handle_Load_Double (state, instr);
1671 break; 1671 break;
1672 } 1672 }
1673 if (BITS (4, 7) == 0xF) { 1673 if (BITS (4, 7) == 0xF) {
1674 Handle_Store_Double (state, instr); 1674 Handle_Store_Double (state, instr);
1675 break; 1675 break;
1676 } 1676 }
1677#endif 1677#endif
1678#ifdef MODET 1678#ifdef MODET
1679 if (BITS (4, 7) == 0x9) { 1679 if (BITS (4, 7) == 0x9) {
1680 /* MULL */ 1680 /* MULL */
1681 /* 32x32 = 64 */ 1681 /* 32x32 = 64 */
1682 ARMul_Icycles (state, 1682 ARMul_Icycles (state,
1683 Multiply64 (state, 1683 Multiply64 (state,
1684 instr, 1684 instr,
1685 LUNSIGNED, 1685 LUNSIGNED,
1686 LDEFAULT), 1686 LDEFAULT),
1687 0L); 1687 0L);
1688 break; 1688 break;
1689 } 1689 }
1690#endif 1690#endif
1691 rhs = DPRegRHS; 1691 rhs = DPRegRHS;
1692 dest = LHS + rhs; 1692 dest = LHS + rhs;
1693 WRITEDEST (dest); 1693 WRITEDEST (dest);
1694 break; 1694 break;
1695 1695
1696 case 0x09: /* ADDS reg */ 1696 case 0x09: /* ADDS reg */
1697#ifdef MODET 1697#ifdef MODET
1698 if ((BITS (4, 11) & 0xF9) == 0x9) 1698 if ((BITS (4, 11) & 0xF9) == 0x9)
1699 /* LDR register offset, no write-back, up, post indexed. */ 1699 /* LDR register offset, no write-back, up, post indexed. */
1700 LHPOSTUP (); 1700 LHPOSTUP ();
1701 /* Fall through to remaining instruction decoding. */ 1701 /* Fall through to remaining instruction decoding. */
1702#endif 1702#endif
1703#ifdef MODET 1703#ifdef MODET
1704 if (BITS (4, 7) == 0x9) { 1704 if (BITS (4, 7) == 0x9) {
1705 /* MULL */ 1705 /* MULL */
1706 /* 32x32=64 */ 1706 /* 32x32=64 */
1707 ARMul_Icycles (state, 1707 ARMul_Icycles (state,
1708 Multiply64 (state, 1708 Multiply64 (state,
1709 instr, 1709 instr,
1710 LUNSIGNED, 1710 LUNSIGNED,
1711 LSCC), 0L); 1711 LSCC), 0L);
1712 break; 1712 break;
1713 } 1713 }
1714#endif 1714#endif
1715 lhs = LHS; 1715 lhs = LHS;
1716 rhs = DPRegRHS; 1716 rhs = DPRegRHS;
1717 dest = lhs + rhs; 1717 dest = lhs + rhs;
1718 ASSIGNZ (dest == 0); 1718 ASSIGNZ (dest == 0);
1719 if ((lhs | rhs) >> 30) { 1719 if ((lhs | rhs) >> 30) {
1720 /* Possible C,V,N to set. */ 1720 /* Possible C,V,N to set. */
1721 ASSIGNN (NEG (dest)); 1721 ASSIGNN (NEG (dest));
1722 ARMul_AddCarry (state, lhs, rhs, 1722 ARMul_AddCarry (state, lhs, rhs,
1723 dest); 1723 dest);
1724 ARMul_AddOverflow (state, lhs, rhs, 1724 ARMul_AddOverflow (state, lhs, rhs,
1725 dest); 1725 dest);
1726 } 1726 }
1727 else { 1727 else {
1728 CLEARN; 1728 CLEARN;
1729 CLEARC; 1729 CLEARC;
1730 CLEARV; 1730 CLEARV;
1731 } 1731 }
1732 WRITESDEST (dest); 1732 WRITESDEST (dest);
1733 break; 1733 break;
1734 1734
1735 case 0x0a: /* ADC reg */ 1735 case 0x0a: /* ADC reg */
1736#ifdef MODET 1736#ifdef MODET
1737 if (BITS (4, 11) == 0xB) { 1737 if (BITS (4, 11) == 0xB) {
1738 /* STRH register offset, write-back, up, post-indexed. */ 1738 /* STRH register offset, write-back, up, post-indexed. */
1739 SHUPWB (); 1739 SHUPWB ();
1740 break; 1740 break;
1741 } 1741 }
1742 if (BITS (4, 7) == 0x9) { 1742 if (BITS (4, 7) == 0x9) {
1743 /* MULL */ 1743 /* MULL */
1744 /* 32x32=64 */ 1744 /* 32x32=64 */
1745 ARMul_Icycles (state, 1745 ARMul_Icycles (state,
1746 MultiplyAdd64 (state, 1746 MultiplyAdd64 (state,
1747 instr, 1747 instr,
1748 LUNSIGNED, 1748 LUNSIGNED,
1749 LDEFAULT), 1749 LDEFAULT),
1750 0L); 1750 0L);
1751 break; 1751 break;
1752 } 1752 }
1753#endif 1753#endif
1754 rhs = DPRegRHS; 1754 rhs = DPRegRHS;
1755 dest = LHS + rhs + CFLAG; 1755 dest = LHS + rhs + CFLAG;
1756 WRITEDEST (dest); 1756 WRITEDEST (dest);
1757 break; 1757 break;
1758 1758
1759 case 0x0b: /* ADCS reg */ 1759 case 0x0b: /* ADCS reg */
1760#ifdef MODET 1760#ifdef MODET
1761 if ((BITS (4, 11) & 0xF9) == 0x9) 1761 if ((BITS (4, 11) & 0xF9) == 0x9)
1762 /* LDR register offset, write-back, up, post indexed. */ 1762 /* LDR register offset, write-back, up, post indexed. */
1763 LHPOSTUP (); 1763 LHPOSTUP ();
1764 /* Fall through to remaining instruction decoding. */ 1764 /* Fall through to remaining instruction decoding. */
1765 if (BITS (4, 7) == 0x9) { 1765 if (BITS (4, 7) == 0x9) {
1766 /* MULL */ 1766 /* MULL */
1767 /* 32x32=64 */ 1767 /* 32x32=64 */
1768 ARMul_Icycles (state, 1768 ARMul_Icycles (state,
1769 MultiplyAdd64 (state, 1769 MultiplyAdd64 (state,
1770 instr, 1770 instr,
1771 LUNSIGNED, 1771 LUNSIGNED,
1772 LSCC), 1772 LSCC),
1773 0L); 1773 0L);
1774 break; 1774 break;
1775 } 1775 }
1776#endif 1776#endif
1777 lhs = LHS; 1777 lhs = LHS;
1778 rhs = DPRegRHS; 1778 rhs = DPRegRHS;
1779 dest = lhs + rhs + CFLAG; 1779 dest = lhs + rhs + CFLAG;
1780 ASSIGNZ (dest == 0); 1780 ASSIGNZ (dest == 0);
1781 if ((lhs | rhs) >> 30) { 1781 if ((lhs | rhs) >> 30) {
1782 /* Possible C,V,N to set. */ 1782 /* Possible C,V,N to set. */
1783 ASSIGNN (NEG (dest)); 1783 ASSIGNN (NEG (dest));
1784 ARMul_AddCarry (state, lhs, rhs, 1784 ARMul_AddCarry (state, lhs, rhs,
1785 dest); 1785 dest);
1786 ARMul_AddOverflow (state, lhs, rhs, 1786 ARMul_AddOverflow (state, lhs, rhs,
1787 dest); 1787 dest);
1788 } 1788 }
1789 else { 1789 else {
1790 CLEARN; 1790 CLEARN;
1791 CLEARC; 1791 CLEARC;
1792 CLEARV; 1792 CLEARV;
1793 } 1793 }
1794 WRITESDEST (dest); 1794 WRITESDEST (dest);
1795 break; 1795 break;
1796 1796
1797 case 0x0c: /* SBC reg */ 1797 case 0x0c: /* SBC reg */
1798#ifdef MODET 1798#ifdef MODET
1799 if (BITS (4, 7) == 0xB) { 1799 if (BITS (4, 7) == 0xB) {
1800 /* STRH immediate offset, no write-back, up post indexed. */ 1800 /* STRH immediate offset, no write-back, up post indexed. */
1801 SHUPWB (); 1801 SHUPWB ();
1802 break; 1802 break;
1803 } 1803 }
1804 if (BITS (4, 7) == 0xD) { 1804 if (BITS (4, 7) == 0xD) {
1805 Handle_Load_Double (state, instr); 1805 Handle_Load_Double (state, instr);
1806 break; 1806 break;
1807 } 1807 }
1808 if (BITS (4, 7) == 0xF) { 1808 if (BITS (4, 7) == 0xF) {
1809 Handle_Store_Double (state, instr); 1809 Handle_Store_Double (state, instr);
1810 break; 1810 break;
1811 } 1811 }
1812 if (BITS (4, 7) == 0x9) { 1812 if (BITS (4, 7) == 0x9) {
1813 /* MULL */ 1813 /* MULL */
1814 /* 32x32=64 */ 1814 /* 32x32=64 */
1815 ARMul_Icycles (state, 1815 ARMul_Icycles (state,
1816 Multiply64 (state, 1816 Multiply64 (state,
1817 instr, 1817 instr,
1818 LSIGNED, 1818 LSIGNED,
1819 LDEFAULT), 1819 LDEFAULT),
1820 0L); 1820 0L);
1821 break; 1821 break;
1822 } 1822 }
1823#endif 1823#endif
1824 rhs = DPRegRHS; 1824 rhs = DPRegRHS;
1825 dest = LHS - rhs - !CFLAG; 1825 dest = LHS - rhs - !CFLAG;
1826 WRITEDEST (dest); 1826 WRITEDEST (dest);
1827 break; 1827 break;
1828 1828
1829 case 0x0d: /* SBCS reg */ 1829 case 0x0d: /* SBCS reg */
1830#ifdef MODET 1830#ifdef MODET
1831 if ((BITS (4, 7) & 0x9) == 0x9) 1831 if ((BITS (4, 7) & 0x9) == 0x9)
1832 /* LDR immediate offset, no write-back, up, post indexed. */ 1832 /* LDR immediate offset, no write-back, up, post indexed. */
1833 LHPOSTUP (); 1833 LHPOSTUP ();
1834 1834
1835 if (BITS (4, 7) == 0x9) { 1835 if (BITS (4, 7) == 0x9) {
1836 /* MULL */ 1836 /* MULL */
1837 /* 32x32=64 */ 1837 /* 32x32=64 */
1838 ARMul_Icycles (state, 1838 ARMul_Icycles (state,
1839 Multiply64 (state, 1839 Multiply64 (state,
1840 instr, 1840 instr,
1841 LSIGNED, 1841 LSIGNED,
1842 LSCC), 0L); 1842 LSCC), 0L);
1843 break; 1843 break;
1844 } 1844 }
1845#endif 1845#endif
1846 lhs = LHS; 1846 lhs = LHS;
1847 rhs = DPRegRHS; 1847 rhs = DPRegRHS;
1848 dest = lhs - rhs - !CFLAG; 1848 dest = lhs - rhs - !CFLAG;
1849 if ((lhs >= rhs) || ((rhs | lhs) >> 31)) { 1849 if ((lhs >= rhs) || ((rhs | lhs) >> 31)) {
1850 ARMul_SubCarry (state, lhs, rhs, 1850 ARMul_SubCarry (state, lhs, rhs,
1851 dest); 1851 dest);
1852 ARMul_SubOverflow (state, lhs, rhs, 1852 ARMul_SubOverflow (state, lhs, rhs,
1853 dest); 1853 dest);
1854 } 1854 }
1855 else { 1855 else {
1856 CLEARC; 1856 CLEARC;
1857 CLEARV; 1857 CLEARV;
1858 } 1858 }
1859 WRITESDEST (dest); 1859 WRITESDEST (dest);
1860 break; 1860 break;
1861 1861
1862 case 0x0e: /* RSC reg */ 1862 case 0x0e: /* RSC reg */
1863#ifdef MODET 1863#ifdef MODET
1864 if (BITS (4, 7) == 0xB) { 1864 if (BITS (4, 7) == 0xB) {
1865 /* STRH immediate offset, write-back, up, post indexed. */ 1865 /* STRH immediate offset, write-back, up, post indexed. */
1866 SHUPWB (); 1866 SHUPWB ();
1867 break; 1867 break;
1868 } 1868 }
1869 1869
1870 if (BITS (4, 7) == 0x9) { 1870 if (BITS (4, 7) == 0x9) {
1871 /* MULL */ 1871 /* MULL */
1872 /* 32x32=64 */ 1872 /* 32x32=64 */
1873 ARMul_Icycles (state, 1873 ARMul_Icycles (state,
1874 MultiplyAdd64 (state, 1874 MultiplyAdd64 (state,
1875 instr, 1875 instr,
1876 LSIGNED, 1876 LSIGNED,
1877 LDEFAULT), 1877 LDEFAULT),
1878 0L); 1878 0L);
1879 break; 1879 break;
1880 } 1880 }
1881#endif 1881#endif
1882 rhs = DPRegRHS; 1882 rhs = DPRegRHS;
1883 dest = rhs - LHS - !CFLAG; 1883 dest = rhs - LHS - !CFLAG;
1884 WRITEDEST (dest); 1884 WRITEDEST (dest);
1885 break; 1885 break;
1886 1886
1887 case 0x0f: /* RSCS reg */ 1887 case 0x0f: /* RSCS reg */
1888#ifdef MODET 1888#ifdef MODET
1889 if ((BITS (4, 7) & 0x9) == 0x9) 1889 if ((BITS (4, 7) & 0x9) == 0x9)
1890 /* LDR immediate offset, write-back, up, post indexed. */ 1890 /* LDR immediate offset, write-back, up, post indexed. */
1891 LHPOSTUP (); 1891 LHPOSTUP ();
1892 /* Fall through to remaining instruction decoding. */ 1892 /* Fall through to remaining instruction decoding. */
1893 1893
1894 if (BITS (4, 7) == 0x9) { 1894 if (BITS (4, 7) == 0x9) {
1895 /* MULL */ 1895 /* MULL */
1896 /* 32x32=64 */ 1896 /* 32x32=64 */
1897 ARMul_Icycles (state, 1897 ARMul_Icycles (state,
1898 MultiplyAdd64 (state, 1898 MultiplyAdd64 (state,
1899 instr, 1899 instr,
1900 LSIGNED, 1900 LSIGNED,
1901 LSCC), 1901 LSCC),
1902 0L); 1902 0L);
1903 break; 1903 break;
1904 } 1904 }
1905#endif 1905#endif
1906 lhs = LHS; 1906 lhs = LHS;
1907 rhs = DPRegRHS; 1907 rhs = DPRegRHS;
1908 dest = rhs - lhs - !CFLAG; 1908 dest = rhs - lhs - !CFLAG;
1909 1909
1910 if ((rhs >= lhs) || ((rhs | lhs) >> 31)) { 1910 if ((rhs >= lhs) || ((rhs | lhs) >> 31)) {
1911 ARMul_SubCarry (state, rhs, lhs, 1911 ARMul_SubCarry (state, rhs, lhs,
1912 dest); 1912 dest);
1913 ARMul_SubOverflow (state, rhs, lhs, 1913 ARMul_SubOverflow (state, rhs, lhs,
1914 dest); 1914 dest);
1915 } 1915 }
1916 else { 1916 else {
1917 CLEARC; 1917 CLEARC;
1918 CLEARV; 1918 CLEARV;
1919 } 1919 }
1920 WRITESDEST (dest); 1920 WRITESDEST (dest);
1921 break; 1921 break;
1922 1922
1923 case 0x10: /* TST reg and MRS CPSR and SWP word. */ 1923 case 0x10: /* TST reg and MRS CPSR and SWP word. */
1924 if (state->is_v5e) { 1924 if (state->is_v5e) {
1925 if (BIT (4) == 0 && BIT (7) == 1) { 1925 if (BIT (4) == 0 && BIT (7) == 1) {
1926 /* ElSegundo SMLAxy insn. */ 1926 /* ElSegundo SMLAxy insn. */
1927 ARMword op1 = 1927 ARMword op1 =
1928 state-> 1928 state->
1929 Reg[BITS (0, 3)]; 1929 Reg[BITS (0, 3)];
1930 ARMword op2 = 1930 ARMword op2 =
1931 state-> 1931 state->
1932 Reg[BITS (8, 11)]; 1932 Reg[BITS (8, 11)];
1933 ARMword Rn = 1933 ARMword Rn =
1934 state-> 1934 state->
1935 Reg[BITS (12, 15)]; 1935 Reg[BITS (12, 15)];
1936 1936
1937 if (BIT (5)) 1937 if (BIT (5))
1938 op1 >>= 16; 1938 op1 >>= 16;
1939 if (BIT (6)) 1939 if (BIT (6))
1940 op2 >>= 16; 1940 op2 >>= 16;
1941 op1 &= 0xFFFF; 1941 op1 &= 0xFFFF;
1942 op2 &= 0xFFFF; 1942 op2 &= 0xFFFF;
1943 if (op1 & 0x8000) 1943 if (op1 & 0x8000)
1944 op1 -= 65536; 1944 op1 -= 65536;
1945 if (op2 & 0x8000) 1945 if (op2 & 0x8000)
1946 op2 -= 65536; 1946 op2 -= 65536;
1947 op1 *= op2; 1947 op1 *= op2;
1948 //printf("SMLA_INST:BB,op1=0x%x, op2=0x%x. Rn=0x%x\n", op1, op2, Rn); 1948 //printf("SMLA_INST:BB,op1=0x%x, op2=0x%x. Rn=0x%x\n", op1, op2, Rn);
1949 if (AddOverflow 1949 if (AddOverflow
1950 (op1, Rn, op1 + Rn)) 1950 (op1, Rn, op1 + Rn))
1951 SETS; 1951 SETS;
1952 state->Reg[BITS (16, 19)] = 1952 state->Reg[BITS (16, 19)] =
1953 op1 + Rn; 1953 op1 + Rn;
1954 break; 1954 break;
1955 } 1955 }
1956 1956
1957 if (BITS (4, 11) == 5) { 1957 if (BITS (4, 11) == 5) {
1958 /* ElSegundo QADD insn. */ 1958 /* ElSegundo QADD insn. */
1959 ARMword op1 = 1959 ARMword op1 =
1960 state-> 1960 state->
1961 Reg[BITS (0, 3)]; 1961 Reg[BITS (0, 3)];
1962 ARMword op2 = 1962 ARMword op2 =
1963 state-> 1963 state->
1964 Reg[BITS (16, 19)]; 1964 Reg[BITS (16, 19)];
1965 ARMword result = op1 + op2; 1965 ARMword result = op1 + op2;
1966 if (AddOverflow 1966 if (AddOverflow
1967 (op1, op2, result)) { 1967 (op1, op2, result)) {
1968 result = POS (result) 1968 result = POS (result)
1969 ? 0x80000000 : 1969 ? 0x80000000 :
1970 0x7fffffff; 1970 0x7fffffff;
1971 SETS; 1971 SETS;
1972 } 1972 }
1973 state->Reg[BITS (12, 15)] = 1973 state->Reg[BITS (12, 15)] =
1974 result; 1974 result;
1975 break; 1975 break;
1976 } 1976 }
1977 } 1977 }
1978#ifdef MODET 1978#ifdef MODET
1979 if (BITS (4, 11) == 0xB) { 1979 if (BITS (4, 11) == 0xB) {
1980 /* STRH register offset, no write-back, down, pre indexed. */ 1980 /* STRH register offset, no write-back, down, pre indexed. */
1981 SHPREDOWN (); 1981 SHPREDOWN ();
1982 break; 1982 break;
1983 } 1983 }
1984 if (BITS (4, 7) == 0xD) { 1984 if (BITS (4, 7) == 0xD) {
1985 Handle_Load_Double (state, instr); 1985 Handle_Load_Double (state, instr);
1986 break; 1986 break;
1987 } 1987 }
1988 if (BITS (4, 7) == 0xF) { 1988 if (BITS (4, 7) == 0xF) {
1989 Handle_Store_Double (state, instr); 1989 Handle_Store_Double (state, instr);
1990 break; 1990 break;
1991 } 1991 }
1992#endif 1992#endif
1993 if (BITS (4, 11) == 9) { 1993 if (BITS (4, 11) == 9) {
1994 /* SWP */ 1994 /* SWP */
1995 UNDEF_SWPPC; 1995 UNDEF_SWPPC;
1996 temp = LHS; 1996 temp = LHS;
1997 BUSUSEDINCPCS; 1997 BUSUSEDINCPCS;
1998#ifndef MODE32 1998#ifndef MODE32
1999 if (VECTORACCESS (temp) 1999 if (VECTORACCESS (temp)
2000 || ADDREXCEPT (temp)) { 2000 || ADDREXCEPT (temp)) {
2001 INTERNALABORT (temp); 2001 INTERNALABORT (temp);
2002 (void) ARMul_LoadWordN (state, 2002 (void) ARMul_LoadWordN (state,
2003 temp); 2003 temp);
2004 (void) ARMul_LoadWordN (state, 2004 (void) ARMul_LoadWordN (state,
2005 temp); 2005 temp);
2006 } 2006 }
2007 else 2007 else
2008#endif 2008#endif
2009 dest = ARMul_SwapWord (state, 2009 dest = ARMul_SwapWord (state,
2010 temp, 2010 temp,
2011 state-> 2011 state->
2012 Reg 2012 Reg
2013 [RHSReg]); 2013 [RHSReg]);
2014 if (temp & 3) 2014 if (temp & 3)
2015 DEST = ARMul_Align (state, 2015 DEST = ARMul_Align (state,
2016 temp, 2016 temp,
2017 dest); 2017 dest);
2018 else 2018 else
2019 DEST = dest; 2019 DEST = dest;
2020 if (state->abortSig || state->Aborted) 2020 if (state->abortSig || state->Aborted)
2021 TAKEABORT; 2021 TAKEABORT;
2022 } 2022 }
2023 else if ((BITS (0, 11) == 0) && (LHSReg == 15)) { /* MRS CPSR */ 2023 else if ((BITS (0, 11) == 0) && (LHSReg == 15)) { /* MRS CPSR */
2024 UNDEF_MRSPC; 2024 UNDEF_MRSPC;
2025 DEST = ECC | EINT | EMODE; 2025 DEST = ECC | EINT | EMODE;
2026 } 2026 }
2027 else { 2027 else {
2028 UNDEF_Test; 2028 UNDEF_Test;
2029 } 2029 }
2030 break; 2030 break;
2031 2031
2032 case 0x11: /* TSTP reg */ 2032 case 0x11: /* TSTP reg */
2033#ifdef MODET 2033#ifdef MODET
2034 if ((BITS (4, 11) & 0xF9) == 0x9) 2034 if ((BITS (4, 11) & 0xF9) == 0x9)
2035 /* LDR register offset, no write-back, down, pre indexed. */ 2035 /* LDR register offset, no write-back, down, pre indexed. */
2036 LHPREDOWN (); 2036 LHPREDOWN ();
2037 /* Continue with remaining instruction decode. */ 2037 /* Continue with remaining instruction decode. */
2038#endif 2038#endif
2039 if (DESTReg == 15) { 2039 if (DESTReg == 15) {
2040 /* TSTP reg */ 2040 /* TSTP reg */
2041#ifdef MODE32 2041#ifdef MODE32
2042 //chy 2006-02-15 if in user mode, can not set cpsr 0:23 2042 //chy 2006-02-15 if in user mode, can not set cpsr 0:23
2043 //from p165 of ARMARM book 2043 //from p165 of ARMARM book
2044 state->Cpsr = GETSPSR (state->Bank); 2044 state->Cpsr = GETSPSR (state->Bank);
2045 ARMul_CPSRAltered (state); 2045 ARMul_CPSRAltered (state);
2046#else 2046#else
2047 rhs = DPRegRHS; 2047 rhs = DPRegRHS;
2048 temp = LHS & rhs; 2048 temp = LHS & rhs;
2049 SETR15PSR (temp); 2049 SETR15PSR (temp);
2050#endif 2050#endif
2051 } 2051 }
2052 else { 2052 else {
2053 /* TST reg */ 2053 /* TST reg */
2054 rhs = DPSRegRHS; 2054 rhs = DPSRegRHS;
2055 dest = LHS & rhs; 2055 dest = LHS & rhs;
2056 ARMul_NegZero (state, dest); 2056 ARMul_NegZero (state, dest);
2057 } 2057 }
2058 break; 2058 break;
2059 2059
2060 case 0x12: /* TEQ reg and MSR reg to CPSR (ARM6). */ 2060 case 0x12: /* TEQ reg and MSR reg to CPSR (ARM6). */
2061 2061
2062 if (state->is_v5) { 2062 if (state->is_v5) {
2063 if (BITS (4, 7) == 3) { 2063 if (BITS (4, 7) == 3) {
2064 /* BLX(2) */ 2064 /* BLX(2) */
2065 ARMword temp; 2065 ARMword temp;
2066 2066
2067 if (TFLAG) 2067 if (TFLAG)
2068 temp = (pc + 2) | 1; 2068 temp = (pc + 2) | 1;
2069 else 2069 else
2070 temp = pc + 4; 2070 temp = pc + 4;
2071 2071
2072 WriteR15Branch (state, 2072 WriteR15Branch (state,
2073 state-> 2073 state->
2074 Reg[RHSReg]); 2074 Reg[RHSReg]);
2075 state->Reg[14] = temp; 2075 state->Reg[14] = temp;
2076 break; 2076 break;
2077 } 2077 }
2078 } 2078 }
2079 2079
2080 if (state->is_v5e) { 2080 if (state->is_v5e) {
2081 if (BIT (4) == 0 && BIT (7) == 1 2081 if (BIT (4) == 0 && BIT (7) == 1
2082 && (BIT (5) == 0 2082 && (BIT (5) == 0
2083 || BITS (12, 15) == 0)) { 2083 || BITS (12, 15) == 0)) {
2084 /* ElSegundo SMLAWy/SMULWy insn. */ 2084 /* ElSegundo SMLAWy/SMULWy insn. */
2085 unsigned long long op1 = 2085 unsigned long long op1 =
2086 state-> 2086 state->
2087 Reg[BITS (0, 3)]; 2087 Reg[BITS (0, 3)];
2088 unsigned long long op2 = 2088 unsigned long long op2 =
2089 state-> 2089 state->
2090 Reg[BITS (8, 11)]; 2090 Reg[BITS (8, 11)];
2091 unsigned long long result; 2091 unsigned long long result;
2092 2092
2093 if (BIT (6)) 2093 if (BIT (6))
2094 op2 >>= 16; 2094 op2 >>= 16;
2095 if (op1 & 0x80000000) 2095 if (op1 & 0x80000000)
2096 op1 -= 1ULL << 32; 2096 op1 -= 1ULL << 32;
2097 op2 &= 0xFFFF; 2097 op2 &= 0xFFFF;
2098 if (op2 & 0x8000) 2098 if (op2 & 0x8000)
2099 op2 -= 65536; 2099 op2 -= 65536;
2100 result = (op1 * op2) >> 16; 2100 result = (op1 * op2) >> 16;
2101 2101
2102 if (BIT (5) == 0) { 2102 if (BIT (5) == 0) {
2103 ARMword Rn = 2103 ARMword Rn =
2104 state-> 2104 state->
2105 Reg[BITS 2105 Reg[BITS
2106 (12, 15)]; 2106 (12, 15)];
2107 2107
2108 if (AddOverflow 2108 if (AddOverflow
2109 (result, Rn, 2109 (result, Rn,
2110 result + Rn)) 2110 result + Rn))
2111 SETS; 2111 SETS;
2112 result += Rn; 2112 result += Rn;
2113 } 2113 }
2114 state->Reg[BITS (16, 19)] = 2114 state->Reg[BITS (16, 19)] =
2115 result; 2115 result;
2116 break; 2116 break;
2117 } 2117 }
2118 2118
2119 if (BITS (4, 11) == 5) { 2119 if (BITS (4, 11) == 5) {
2120 /* ElSegundo QSUB insn. */ 2120 /* ElSegundo QSUB insn. */
2121 ARMword op1 = 2121 ARMword op1 =
2122 state-> 2122 state->
2123 Reg[BITS (0, 3)]; 2123 Reg[BITS (0, 3)];
2124 ARMword op2 = 2124 ARMword op2 =
2125 state-> 2125 state->
2126 Reg[BITS (16, 19)]; 2126 Reg[BITS (16, 19)];
2127 ARMword result = op1 - op2; 2127 ARMword result = op1 - op2;
2128 2128
2129 if (SubOverflow 2129 if (SubOverflow
2130 (op1, op2, result)) { 2130 (op1, op2, result)) {
2131 result = POS (result) 2131 result = POS (result)
2132 ? 0x80000000 : 2132 ? 0x80000000 :
2133 0x7fffffff; 2133 0x7fffffff;
2134 SETS; 2134 SETS;
2135 } 2135 }
2136 2136
2137 state->Reg[BITS (12, 15)] = 2137 state->Reg[BITS (12, 15)] =
2138 result; 2138 result;
2139 break; 2139 break;
2140 } 2140 }
2141 } 2141 }
2142#ifdef MODET 2142#ifdef MODET
2143 if (BITS (4, 11) == 0xB) { 2143 if (BITS (4, 11) == 0xB) {
2144 /* STRH register offset, write-back, down, pre indexed. */ 2144 /* STRH register offset, write-back, down, pre indexed. */
2145 SHPREDOWNWB (); 2145 SHPREDOWNWB ();
2146 break; 2146 break;
2147 } 2147 }
2148 if (BITS (4, 27) == 0x12FFF1) { 2148 if (BITS (4, 27) == 0x12FFF1) {
2149 /* BX */ 2149 /* BX */
2150 WriteR15Branch (state, 2150 WriteR15Branch (state,
2151 state->Reg[RHSReg]); 2151 state->Reg[RHSReg]);
2152 break; 2152 break;
2153 } 2153 }
2154 if (BITS (4, 7) == 0xD) { 2154 if (BITS (4, 7) == 0xD) {
2155 Handle_Load_Double (state, instr); 2155 Handle_Load_Double (state, instr);
2156 break; 2156 break;
2157 } 2157 }
2158 if (BITS (4, 7) == 0xF) { 2158 if (BITS (4, 7) == 0xF) {
2159 Handle_Store_Double (state, instr); 2159 Handle_Store_Double (state, instr);
2160 break; 2160 break;
2161 } 2161 }
2162#endif 2162#endif
2163 if (state->is_v5) { 2163 if (state->is_v5) {
2164 if (BITS (4, 7) == 0x7) { 2164 if (BITS (4, 7) == 0x7) {
2165 ARMword value; 2165 ARMword value;
2166 extern int 2166 extern int
2167 SWI_vector_installed; 2167 SWI_vector_installed;
2168 2168
2169 /* Hardware is allowed to optionally override this 2169 /* Hardware is allowed to optionally override this
2170 instruction and treat it as a breakpoint. Since 2170 instruction and treat it as a breakpoint. Since
2171 this is a simulator not hardware, we take the position 2171 this is a simulator not hardware, we take the position
2172 that if a SWI vector was not installed, then an Abort 2172 that if a SWI vector was not installed, then an Abort
2173 vector was probably not installed either, and so 2173 vector was probably not installed either, and so
2174 normally this instruction would be ignored, even if an 2174 normally this instruction would be ignored, even if an
2175 Abort is generated. This is a bad thing, since GDB 2175 Abort is generated. This is a bad thing, since GDB
2176 uses this instruction for its breakpoints (at least in 2176 uses this instruction for its breakpoints (at least in
2177 Thumb mode it does). So intercept the instruction here 2177 Thumb mode it does). So intercept the instruction here
2178 and generate a breakpoint SWI instead. */ 2178 and generate a breakpoint SWI instead. */
2179 if (!SWI_vector_installed) 2179 if (!SWI_vector_installed)
2180 ARMul_OSHandleSWI 2180 ARMul_OSHandleSWI
2181 (state, 2181 (state,
2182 SWI_Breakpoint); 2182 SWI_Breakpoint);
2183 else { 2183 else {
2184 /* BKPT - normally this will cause an abort, but on the 2184 /* BKPT - normally this will cause an abort, but on the
2185 XScale we must check the DCSR. */ 2185 XScale we must check the DCSR. */
2186 XScale_set_fsr_far 2186 XScale_set_fsr_far
2187 (state, 2187 (state,
2188 ARMul_CP15_R5_MMU_EXCPT, 2188 ARMul_CP15_R5_MMU_EXCPT,
2189 pc); 2189 pc);
2190 //if (!XScale_debug_moe 2190 //if (!XScale_debug_moe
2191 // (state, 2191 // (state,
2192 // ARMul_CP14_R10_MOE_BT)) 2192 // ARMul_CP14_R10_MOE_BT))
2193 // break; // Disabled /bunnei 2193 // break; // Disabled /bunnei
2194 } 2194 }
2195 2195
2196 /* Force the next instruction to be refetched. */ 2196 /* Force the next instruction to be refetched. */
2197 state->NextInstr = RESUME; 2197 state->NextInstr = RESUME;
2198 break; 2198 break;
2199 } 2199 }
2200 } 2200 }
2201 if (DESTReg == 15) { 2201 if (DESTReg == 15) {
2202 /* MSR reg to CPSR. */ 2202 /* MSR reg to CPSR. */
2203 UNDEF_MSRPC; 2203 UNDEF_MSRPC;
2204 temp = DPRegRHS; 2204 temp = DPRegRHS;
2205#ifdef MODET 2205#ifdef MODET
2206 /* Don't allow TBIT to be set by MSR. */ 2206 /* Don't allow TBIT to be set by MSR. */
2207 temp &= ~TBIT; 2207 temp &= ~TBIT;
2208#endif 2208#endif
2209 ARMul_FixCPSR (state, instr, temp); 2209 ARMul_FixCPSR (state, instr, temp);
2210 } 2210 }
2211 else 2211 else
2212 UNDEF_Test; 2212 UNDEF_Test;
2213 2213
2214 break; 2214 break;
2215 2215
2216 case 0x13: /* TEQP reg */ 2216 case 0x13: /* TEQP reg */
2217#ifdef MODET 2217#ifdef MODET
2218 if ((BITS (4, 11) & 0xF9) == 0x9) 2218 if ((BITS (4, 11) & 0xF9) == 0x9)
2219 /* LDR register offset, write-back, down, pre indexed. */ 2219 /* LDR register offset, write-back, down, pre indexed. */
2220 LHPREDOWNWB (); 2220 LHPREDOWNWB ();
2221 /* Continue with remaining instruction decode. */ 2221 /* Continue with remaining instruction decode. */
2222#endif 2222#endif
2223 if (DESTReg == 15) { 2223 if (DESTReg == 15) {
2224 /* TEQP reg */ 2224 /* TEQP reg */
2225#ifdef MODE32 2225#ifdef MODE32
2226 state->Cpsr = GETSPSR (state->Bank); 2226 state->Cpsr = GETSPSR (state->Bank);
2227 ARMul_CPSRAltered (state); 2227 ARMul_CPSRAltered (state);
2228#else 2228#else
2229 rhs = DPRegRHS; 2229 rhs = DPRegRHS;
2230 temp = LHS ^ rhs; 2230 temp = LHS ^ rhs;
2231 SETR15PSR (temp); 2231 SETR15PSR (temp);
2232#endif 2232#endif
2233 } 2233 }
2234 else { 2234 else {
2235 /* TEQ Reg. */ 2235 /* TEQ Reg. */
2236 rhs = DPSRegRHS; 2236 rhs = DPSRegRHS;
2237 dest = LHS ^ rhs; 2237 dest = LHS ^ rhs;
2238 ARMul_NegZero (state, dest); 2238 ARMul_NegZero (state, dest);
2239 } 2239 }
2240 break; 2240 break;
2241 2241
2242 case 0x14: /* CMP reg and MRS SPSR and SWP byte. */ 2242 case 0x14: /* CMP reg and MRS SPSR and SWP byte. */
2243 if (state->is_v5e) { 2243 if (state->is_v5e) {
2244 if (BIT (4) == 0 && BIT (7) == 1) { 2244 if (BIT (4) == 0 && BIT (7) == 1) {
2245 /* ElSegundo SMLALxy insn. */ 2245 /* ElSegundo SMLALxy insn. */
2246 unsigned long long op1 = 2246 unsigned long long op1 =
2247 state-> 2247 state->
2248 Reg[BITS (0, 3)]; 2248 Reg[BITS (0, 3)];
2249 unsigned long long op2 = 2249 unsigned long long op2 =
2250 state-> 2250 state->
2251 Reg[BITS (8, 11)]; 2251 Reg[BITS (8, 11)];
2252 unsigned long long dest; 2252 unsigned long long dest;
2253 unsigned long long result; 2253 unsigned long long result;
2254 2254
2255 if (BIT (5)) 2255 if (BIT (5))
2256 op1 >>= 16; 2256 op1 >>= 16;
2257 if (BIT (6)) 2257 if (BIT (6))
2258 op2 >>= 16; 2258 op2 >>= 16;
2259 op1 &= 0xFFFF; 2259 op1 &= 0xFFFF;
2260 if (op1 & 0x8000) 2260 if (op1 & 0x8000)
2261 op1 -= 65536; 2261 op1 -= 65536;
2262 op2 &= 0xFFFF; 2262 op2 &= 0xFFFF;
2263 if (op2 & 0x8000) 2263 if (op2 & 0x8000)
2264 op2 -= 65536; 2264 op2 -= 65536;
2265 2265
2266 dest = (unsigned long long) 2266 dest = (unsigned long long)
2267 state-> 2267 state->
2268 Reg[BITS (16, 19)] << 2268 Reg[BITS (16, 19)] <<
2269 32; 2269 32;
2270 dest |= state-> 2270 dest |= state->
2271 Reg[BITS (12, 15)]; 2271 Reg[BITS (12, 15)];
2272 dest += op1 * op2; 2272 dest += op1 * op2;
2273 state->Reg[BITS (12, 15)] = 2273 state->Reg[BITS (12, 15)] =
2274 dest; 2274 dest;
2275 state->Reg[BITS (16, 19)] = 2275 state->Reg[BITS (16, 19)] =
2276 dest >> 32; 2276 dest >> 32;
2277 break; 2277 break;
2278 } 2278 }
2279 2279
2280 if (BITS (4, 11) == 5) { 2280 if (BITS (4, 11) == 5) {
2281 /* ElSegundo QDADD insn. */ 2281 /* ElSegundo QDADD insn. */
2282 ARMword op1 = 2282 ARMword op1 =
2283 state-> 2283 state->
2284 Reg[BITS (0, 3)]; 2284 Reg[BITS (0, 3)];
2285 ARMword op2 = 2285 ARMword op2 =
2286 state-> 2286 state->
2287 Reg[BITS (16, 19)]; 2287 Reg[BITS (16, 19)];
2288 ARMword op2d = op2 + op2; 2288 ARMword op2d = op2 + op2;
2289 ARMword result; 2289 ARMword result;
2290 2290
2291 if (AddOverflow 2291 if (AddOverflow
2292 (op2, op2, op2d)) { 2292 (op2, op2, op2d)) {
2293 SETS; 2293 SETS;
2294 op2d = POS (op2d) ? 2294 op2d = POS (op2d) ?
2295 0x80000000 : 2295 0x80000000 :
2296 0x7fffffff; 2296 0x7fffffff;
2297 } 2297 }
2298 2298
2299 result = op1 + op2d; 2299 result = op1 + op2d;
2300 if (AddOverflow 2300 if (AddOverflow
2301 (op1, op2d, result)) { 2301 (op1, op2d, result)) {
2302 SETS; 2302 SETS;
2303 result = POS (result) 2303 result = POS (result)
2304 ? 0x80000000 : 2304 ? 0x80000000 :
2305 0x7fffffff; 2305 0x7fffffff;
2306 } 2306 }
2307 2307
2308 state->Reg[BITS (12, 15)] = 2308 state->Reg[BITS (12, 15)] =
2309 result; 2309 result;
2310 break; 2310 break;
2311 } 2311 }
2312 } 2312 }
2313#ifdef MODET 2313#ifdef MODET
2314 if (BITS (4, 7) == 0xB) { 2314 if (BITS (4, 7) == 0xB) {
2315 /* STRH immediate offset, no write-back, down, pre indexed. */ 2315 /* STRH immediate offset, no write-back, down, pre indexed. */
2316 SHPREDOWN (); 2316 SHPREDOWN ();
2317 break; 2317 break;
2318 } 2318 }
2319 if (BITS (4, 7) == 0xD) { 2319 if (BITS (4, 7) == 0xD) {
2320 Handle_Load_Double (state, instr); 2320 Handle_Load_Double (state, instr);
2321 break; 2321 break;
2322 } 2322 }
2323 if (BITS (4, 7) == 0xF) { 2323 if (BITS (4, 7) == 0xF) {
2324 Handle_Store_Double (state, instr); 2324 Handle_Store_Double (state, instr);
2325 break; 2325 break;
2326 } 2326 }
2327#endif 2327#endif
2328 if (BITS (4, 11) == 9) { 2328 if (BITS (4, 11) == 9) {
2329 /* SWP */ 2329 /* SWP */
2330 UNDEF_SWPPC; 2330 UNDEF_SWPPC;
2331 temp = LHS; 2331 temp = LHS;
2332 BUSUSEDINCPCS; 2332 BUSUSEDINCPCS;
2333#ifndef MODE32 2333#ifndef MODE32
2334 if (VECTORACCESS (temp) 2334 if (VECTORACCESS (temp)
2335 || ADDREXCEPT (temp)) { 2335 || ADDREXCEPT (temp)) {
2336 INTERNALABORT (temp); 2336 INTERNALABORT (temp);
2337 (void) ARMul_LoadByte (state, 2337 (void) ARMul_LoadByte (state,
2338 temp); 2338 temp);
2339 (void) ARMul_LoadByte (state, 2339 (void) ARMul_LoadByte (state,
2340 temp); 2340 temp);
2341 } 2341 }
2342 else 2342 else
2343#endif 2343#endif
2344 DEST = ARMul_SwapByte (state, 2344 DEST = ARMul_SwapByte (state,
2345 temp, 2345 temp,
2346 state-> 2346 state->
2347 Reg 2347 Reg
2348 [RHSReg]); 2348 [RHSReg]);
2349 if (state->abortSig || state->Aborted) 2349 if (state->abortSig || state->Aborted)
2350 TAKEABORT; 2350 TAKEABORT;
2351 } 2351 }
2352 else if ((BITS (0, 11) == 0) 2352 else if ((BITS (0, 11) == 0)
2353 && (LHSReg == 15)) { 2353 && (LHSReg == 15)) {
2354 /* MRS SPSR */ 2354 /* MRS SPSR */
2355 UNDEF_MRSPC; 2355 UNDEF_MRSPC;
2356 DEST = GETSPSR (state->Bank); 2356 DEST = GETSPSR (state->Bank);
2357 } 2357 }
2358 else 2358 else
2359 UNDEF_Test; 2359 UNDEF_Test;
2360 2360
2361 break; 2361 break;
2362 2362
2363 case 0x15: /* CMPP reg. */ 2363 case 0x15: /* CMPP reg. */
2364#ifdef MODET 2364#ifdef MODET
2365 if ((BITS (4, 7) & 0x9) == 0x9) 2365 if ((BITS (4, 7) & 0x9) == 0x9)
2366 /* LDR immediate offset, no write-back, down, pre indexed. */ 2366 /* LDR immediate offset, no write-back, down, pre indexed. */
2367 LHPREDOWN (); 2367 LHPREDOWN ();
2368 /* Continue with remaining instruction decode. */ 2368 /* Continue with remaining instruction decode. */
2369#endif 2369#endif
2370 if (DESTReg == 15) { 2370 if (DESTReg == 15) {
2371 /* CMPP reg. */ 2371 /* CMPP reg. */
2372#ifdef MODE32 2372#ifdef MODE32
2373 state->Cpsr = GETSPSR (state->Bank); 2373 state->Cpsr = GETSPSR (state->Bank);
2374 ARMul_CPSRAltered (state); 2374 ARMul_CPSRAltered (state);
2375#else 2375#else
2376 rhs = DPRegRHS; 2376 rhs = DPRegRHS;
2377 temp = LHS - rhs; 2377 temp = LHS - rhs;
2378 SETR15PSR (temp); 2378 SETR15PSR (temp);
2379#endif 2379#endif
2380 } 2380 }
2381 else { 2381 else {
2382 /* CMP reg. */ 2382 /* CMP reg. */
2383 lhs = LHS; 2383 lhs = LHS;
2384 rhs = DPRegRHS; 2384 rhs = DPRegRHS;
2385 dest = lhs - rhs; 2385 dest = lhs - rhs;
2386 ARMul_NegZero (state, dest); 2386 ARMul_NegZero (state, dest);
2387 if ((lhs >= rhs) 2387 if ((lhs >= rhs)
2388 || ((rhs | lhs) >> 31)) { 2388 || ((rhs | lhs) >> 31)) {
2389 ARMul_SubCarry (state, lhs, 2389 ARMul_SubCarry (state, lhs,
2390 rhs, dest); 2390 rhs, dest);
2391 ARMul_SubOverflow (state, lhs, 2391 ARMul_SubOverflow (state, lhs,
2392 rhs, dest); 2392 rhs, dest);
2393 } 2393 }
2394 else { 2394 else {
2395 CLEARC; 2395 CLEARC;
2396 CLEARV; 2396 CLEARV;
2397 } 2397 }
2398 } 2398 }
2399 break; 2399 break;
2400 2400
2401 case 0x16: /* CMN reg and MSR reg to SPSR */ 2401 case 0x16: /* CMN reg and MSR reg to SPSR */
2402 if (state->is_v5e) { 2402 if (state->is_v5e) {
2403 if (BIT (4) == 0 && BIT (7) == 1 2403 if (BIT (4) == 0 && BIT (7) == 1
2404 && BITS (12, 15) == 0) { 2404 && BITS (12, 15) == 0) {
2405 /* ElSegundo SMULxy insn. */ 2405 /* ElSegundo SMULxy insn. */
2406 ARMword op1 = 2406 ARMword op1 =
2407 state-> 2407 state->
2408 Reg[BITS (0, 3)]; 2408 Reg[BITS (0, 3)];
2409 ARMword op2 = 2409 ARMword op2 =
2410 state-> 2410 state->
2411 Reg[BITS (8, 11)]; 2411 Reg[BITS (8, 11)];
2412 ARMword Rn = 2412 ARMword Rn =
2413 state-> 2413 state->
2414 Reg[BITS (12, 15)]; 2414 Reg[BITS (12, 15)];
2415 2415
2416 if (BIT (5)) 2416 if (BIT (5))
2417 op1 >>= 16; 2417 op1 >>= 16;
2418 if (BIT (6)) 2418 if (BIT (6))
2419 op2 >>= 16; 2419 op2 >>= 16;
2420 op1 &= 0xFFFF; 2420 op1 &= 0xFFFF;
2421 op2 &= 0xFFFF; 2421 op2 &= 0xFFFF;
2422 if (op1 & 0x8000) 2422 if (op1 & 0x8000)
2423 op1 -= 65536; 2423 op1 -= 65536;
2424 if (op2 & 0x8000) 2424 if (op2 & 0x8000)
2425 op2 -= 65536; 2425 op2 -= 65536;
2426 2426
2427 state->Reg[BITS (16, 19)] = 2427 state->Reg[BITS (16, 19)] =
2428 op1 * op2; 2428 op1 * op2;
2429 break; 2429 break;
2430 } 2430 }
2431 2431
2432 if (BITS (4, 11) == 5) { 2432 if (BITS (4, 11) == 5) {
2433 /* ElSegundo QDSUB insn. */ 2433 /* ElSegundo QDSUB insn. */
2434 ARMword op1 = 2434 ARMword op1 =
2435 state-> 2435 state->
2436 Reg[BITS (0, 3)]; 2436 Reg[BITS (0, 3)];
2437 ARMword op2 = 2437 ARMword op2 =
2438 state-> 2438 state->
2439 Reg[BITS (16, 19)]; 2439 Reg[BITS (16, 19)];
2440 ARMword op2d = op2 + op2; 2440 ARMword op2d = op2 + op2;
2441 ARMword result; 2441 ARMword result;
2442 2442
2443 if (AddOverflow 2443 if (AddOverflow
2444 (op2, op2, op2d)) { 2444 (op2, op2, op2d)) {
2445 SETS; 2445 SETS;
2446 op2d = POS (op2d) ? 2446 op2d = POS (op2d) ?
2447 0x80000000 : 2447 0x80000000 :
2448 0x7fffffff; 2448 0x7fffffff;
2449 } 2449 }
2450 2450
2451 result = op1 - op2d; 2451 result = op1 - op2d;
2452 if (SubOverflow 2452 if (SubOverflow
2453 (op1, op2d, result)) { 2453 (op1, op2d, result)) {
2454 SETS; 2454 SETS;
2455 result = POS (result) 2455 result = POS (result)
2456 ? 0x80000000 : 2456 ? 0x80000000 :
2457 0x7fffffff; 2457 0x7fffffff;
2458 } 2458 }
2459 2459
2460 state->Reg[BITS (12, 15)] = 2460 state->Reg[BITS (12, 15)] =
2461 result; 2461 result;
2462 break; 2462 break;
2463 } 2463 }
2464 } 2464 }
2465 2465
2466 if (state->is_v5) { 2466 if (state->is_v5) {
2467 if (BITS (4, 11) == 0xF1 2467 if (BITS (4, 11) == 0xF1
2468 && BITS (16, 19) == 0xF) { 2468 && BITS (16, 19) == 0xF) {
2469 /* ARM5 CLZ insn. */ 2469 /* ARM5 CLZ insn. */
2470 ARMword op1 = 2470 ARMword op1 =
2471 state-> 2471 state->
2472 Reg[BITS (0, 3)]; 2472 Reg[BITS (0, 3)];
2473 int result = 32; 2473 int result = 32;
2474 2474
2475 if (op1) 2475 if (op1)
2476 for (result = 0; 2476 for (result = 0;
2477 (op1 & 2477 (op1 &
2478 0x80000000) == 2478 0x80000000) ==
2479 0; op1 <<= 1) 2479 0; op1 <<= 1)
2480 result++; 2480 result++;
2481 state->Reg[BITS (12, 15)] = 2481 state->Reg[BITS (12, 15)] =
2482 result; 2482 result;
2483 break; 2483 break;
2484 } 2484 }
2485 } 2485 }
2486 2486
2487#ifdef MODET 2487#ifdef MODET
2488 if (BITS (4, 7) == 0xB) { 2488 if (BITS (4, 7) == 0xB) {
2489 /* STRH immediate offset, write-back, down, pre indexed. */ 2489 /* STRH immediate offset, write-back, down, pre indexed. */
2490 SHPREDOWNWB (); 2490 SHPREDOWNWB ();
2491 break; 2491 break;
2492 } 2492 }
2493 if (BITS (4, 7) == 0xD) { 2493 if (BITS (4, 7) == 0xD) {
2494 Handle_Load_Double (state, instr); 2494 Handle_Load_Double (state, instr);
2495 break; 2495 break;
2496 } 2496 }
2497 if (BITS (4, 7) == 0xF) { 2497 if (BITS (4, 7) == 0xF) {
2498 Handle_Store_Double (state, instr); 2498 Handle_Store_Double (state, instr);
2499 break; 2499 break;
2500 } 2500 }
2501#endif 2501#endif
2502 if (DESTReg == 15) { 2502 if (DESTReg == 15) {
2503 /* MSR */ 2503 /* MSR */
2504 UNDEF_MSRPC; 2504 UNDEF_MSRPC;
2505 ARMul_FixSPSR (state, instr, 2505 ARMul_FixSPSR (state, instr,
2506 DPRegRHS); 2506 DPRegRHS);
2507 } 2507 }
2508 else { 2508 else {
2509 UNDEF_Test; 2509 UNDEF_Test;
2510 } 2510 }
2511 break; 2511 break;
2512 2512
2513 case 0x17: /* CMNP reg */ 2513 case 0x17: /* CMNP reg */
2514#ifdef MODET 2514#ifdef MODET
2515 if ((BITS (4, 7) & 0x9) == 0x9) 2515 if ((BITS (4, 7) & 0x9) == 0x9)
2516 /* LDR immediate offset, write-back, down, pre indexed. */ 2516 /* LDR immediate offset, write-back, down, pre indexed. */
2517 LHPREDOWNWB (); 2517 LHPREDOWNWB ();
2518 /* Continue with remaining instruction decoding. */ 2518 /* Continue with remaining instruction decoding. */
2519#endif 2519#endif
2520 if (DESTReg == 15) { 2520 if (DESTReg == 15) {
2521#ifdef MODE32 2521#ifdef MODE32
2522 state->Cpsr = GETSPSR (state->Bank); 2522 state->Cpsr = GETSPSR (state->Bank);
2523 ARMul_CPSRAltered (state); 2523 ARMul_CPSRAltered (state);
2524#else 2524#else
2525 rhs = DPRegRHS; 2525 rhs = DPRegRHS;
2526 temp = LHS + rhs; 2526 temp = LHS + rhs;
2527 SETR15PSR (temp); 2527 SETR15PSR (temp);
2528#endif 2528#endif
2529 break; 2529 break;
2530 } 2530 }
2531 else { 2531 else {
2532 /* CMN reg. */ 2532 /* CMN reg. */
2533 lhs = LHS; 2533 lhs = LHS;
2534 rhs = DPRegRHS; 2534 rhs = DPRegRHS;
2535 dest = lhs + rhs; 2535 dest = lhs + rhs;
2536 ASSIGNZ (dest == 0); 2536 ASSIGNZ (dest == 0);
2537 if ((lhs | rhs) >> 30) { 2537 if ((lhs | rhs) >> 30) {
2538 /* Possible C,V,N to set. */ 2538 /* Possible C,V,N to set. */
2539 ASSIGNN (NEG (dest)); 2539 ASSIGNN (NEG (dest));
2540 ARMul_AddCarry (state, lhs, 2540 ARMul_AddCarry (state, lhs,
2541 rhs, dest); 2541 rhs, dest);
2542 ARMul_AddOverflow (state, lhs, 2542 ARMul_AddOverflow (state, lhs,
2543 rhs, dest); 2543 rhs, dest);
2544 } 2544 }
2545 else { 2545 else {
2546 CLEARN; 2546 CLEARN;
2547 CLEARC; 2547 CLEARC;
2548 CLEARV; 2548 CLEARV;
2549 } 2549 }
2550 } 2550 }
2551 break; 2551 break;
2552 2552
2553 case 0x18: /* ORR reg */ 2553 case 0x18: /* ORR reg */
2554#ifdef MODET 2554#ifdef MODET
2555 /* dyf add armv6 instr strex 2010.9.17 */ 2555 /* dyf add armv6 instr strex 2010.9.17 */
2556 if (state->is_v6) { 2556 if (state->is_v6) {
2557 if (BITS (4, 7) == 0x9) 2557 if (BITS (4, 7) == 0x9)
2558 if (handle_v6_insn (state, instr)) 2558 if (handle_v6_insn (state, instr))
2559 break; 2559 break;
2560 } 2560 }
2561 2561
2562 if (BITS (4, 11) == 0xB) { 2562 if (BITS (4, 11) == 0xB) {
2563 /* STRH register offset, no write-back, up, pre indexed. */ 2563 /* STRH register offset, no write-back, up, pre indexed. */
2564 SHPREUP (); 2564 SHPREUP ();
2565 break; 2565 break;
2566 } 2566 }
2567 if (BITS (4, 7) == 0xD) { 2567 if (BITS (4, 7) == 0xD) {
2568 Handle_Load_Double (state, instr); 2568 Handle_Load_Double (state, instr);
2569 break; 2569 break;
2570 } 2570 }
2571 if (BITS (4, 7) == 0xF) { 2571 if (BITS (4, 7) == 0xF) {
2572 Handle_Store_Double (state, instr); 2572 Handle_Store_Double (state, instr);
2573 break; 2573 break;
2574 } 2574 }
2575#endif 2575#endif
2576 rhs = DPRegRHS; 2576 rhs = DPRegRHS;
2577 dest = LHS | rhs; 2577 dest = LHS | rhs;
2578 WRITEDEST (dest); 2578 WRITEDEST (dest);
2579 break; 2579 break;
2580 2580
2581 case 0x19: /* ORRS reg */ 2581 case 0x19: /* ORRS reg */
2582#ifdef MODET 2582#ifdef MODET
2583 /* dyf add armv6 instr ldrex */ 2583 /* dyf add armv6 instr ldrex */
2584 if (state->is_v6) { 2584 if (state->is_v6) {
2585 if (BITS (4, 7) == 0x9) { 2585 if (BITS (4, 7) == 0x9) {
2586 if (handle_v6_insn (state, instr)) 2586 if (handle_v6_insn (state, instr))
2587 break; 2587 break;
2588 } 2588 }
2589 } 2589 }
2590 if ((BITS (4, 11) & 0xF9) == 0x9) 2590 if ((BITS (4, 11) & 0xF9) == 0x9)
2591 /* LDR register offset, no write-back, up, pre indexed. */ 2591 /* LDR register offset, no write-back, up, pre indexed. */
2592 LHPREUP (); 2592 LHPREUP ();
2593 /* Continue with remaining instruction decoding. */ 2593 /* Continue with remaining instruction decoding. */
2594#endif 2594#endif
2595 rhs = DPSRegRHS; 2595 rhs = DPSRegRHS;
2596 dest = LHS | rhs; 2596 dest = LHS | rhs;
2597 WRITESDEST (dest); 2597 WRITESDEST (dest);
2598 break; 2598 break;
2599 2599
2600 case 0x1a: /* MOV reg */ 2600 case 0x1a: /* MOV reg */
2601#ifdef MODET 2601#ifdef MODET
2602 if (BITS (4, 11) == 0xB) { 2602 if (BITS (4, 11) == 0xB) {
2603 /* STRH register offset, write-back, up, pre indexed. */ 2603 /* STRH register offset, write-back, up, pre indexed. */
2604 SHPREUPWB (); 2604 SHPREUPWB ();
2605 break; 2605 break;
2606 } 2606 }
2607 if (BITS (4, 7) == 0xD) { 2607 if (BITS (4, 7) == 0xD) {
2608 Handle_Load_Double (state, instr); 2608 Handle_Load_Double (state, instr);
2609 break; 2609 break;
2610 } 2610 }
2611 if (BITS (4, 7) == 0xF) { 2611 if (BITS (4, 7) == 0xF) {
2612 Handle_Store_Double (state, instr); 2612 Handle_Store_Double (state, instr);
2613 break; 2613 break;
2614 } 2614 }
2615#endif 2615#endif
2616 dest = DPRegRHS; 2616 dest = DPRegRHS;
2617 WRITEDEST (dest); 2617 WRITEDEST (dest);
2618 break; 2618 break;
2619 2619
2620 case 0x1b: /* MOVS reg */ 2620 case 0x1b: /* MOVS reg */
2621#ifdef MODET 2621#ifdef MODET
2622 if ((BITS (4, 11) & 0xF9) == 0x9) 2622 if ((BITS (4, 11) & 0xF9) == 0x9)
2623 /* LDR register offset, write-back, up, pre indexed. */ 2623 /* LDR register offset, write-back, up, pre indexed. */
2624 LHPREUPWB (); 2624 LHPREUPWB ();
2625 /* Continue with remaining instruction decoding. */ 2625 /* Continue with remaining instruction decoding. */
2626#endif 2626#endif
2627 dest = DPSRegRHS; 2627 dest = DPSRegRHS;
2628 WRITESDEST (dest); 2628 WRITESDEST (dest);
2629 break; 2629 break;
2630 2630
2631 case 0x1c: /* BIC reg */ 2631 case 0x1c: /* BIC reg */
2632#ifdef MODET 2632#ifdef MODET
2633 /* dyf add for STREXB */ 2633 /* dyf add for STREXB */
2634 if (state->is_v6) { 2634 if (state->is_v6) {
2635 if (BITS (4, 7) == 0x9) { 2635 if (BITS (4, 7) == 0x9) {
2636 if (handle_v6_insn (state, instr)) 2636 if (handle_v6_insn (state, instr))
2637 break; 2637 break;
2638 } 2638 }
2639 } 2639 }
2640 if (BITS (4, 7) == 0xB) { 2640 if (BITS (4, 7) == 0xB) {
2641 /* STRH immediate offset, no write-back, up, pre indexed. */ 2641 /* STRH immediate offset, no write-back, up, pre indexed. */
2642 SHPREUP (); 2642 SHPREUP ();
2643 break; 2643 break;
2644 } 2644 }
2645 if (BITS (4, 7) == 0xD) { 2645 if (BITS (4, 7) == 0xD) {
2646 Handle_Load_Double (state, instr); 2646 Handle_Load_Double (state, instr);
2647 break; 2647 break;
2648 } 2648 }
2649 else if (BITS (4, 7) == 0xF) { 2649 else if (BITS (4, 7) == 0xF) {
2650 Handle_Store_Double (state, instr); 2650 Handle_Store_Double (state, instr);
2651 break; 2651 break;
2652 } 2652 }
2653#endif 2653#endif
2654 rhs = DPRegRHS; 2654 rhs = DPRegRHS;
2655 dest = LHS & ~rhs; 2655 dest = LHS & ~rhs;
2656 WRITEDEST (dest); 2656 WRITEDEST (dest);
2657 break; 2657 break;
2658 2658
2659 case 0x1d: /* BICS reg */ 2659 case 0x1d: /* BICS reg */
2660#ifdef MODET 2660#ifdef MODET
2661 /* ladsh P=1 U=1 W=0 L=1 S=1 H=1 */ 2661 /* ladsh P=1 U=1 W=0 L=1 S=1 H=1 */
2662 if (BITS(4, 7) == 0xF) { 2662 if (BITS(4, 7) == 0xF) {
2663 temp = LHS + GetLS7RHS (state, instr); 2663 temp = LHS + GetLS7RHS (state, instr);
2664 LoadHalfWord (state, instr, temp, LSIGNED); 2664 LoadHalfWord (state, instr, temp, LSIGNED);
2665 break; 2665 break;
2666 2666
2667 } 2667 }
2668 if (BITS (4, 7) == 0xb) { 2668 if (BITS (4, 7) == 0xb) {
2669 /* LDRH immediate offset, no write-back, up, pre indexed. */ 2669 /* LDRH immediate offset, no write-back, up, pre indexed. */
2670 temp = LHS + GetLS7RHS (state, instr); 2670 temp = LHS + GetLS7RHS (state, instr);
2671 LoadHalfWord (state, instr, temp, LUNSIGNED); 2671 LoadHalfWord (state, instr, temp, LUNSIGNED);
2672 break; 2672 break;
2673 } 2673 }
2674 if (BITS (4, 7) == 0xd) { 2674 if (BITS (4, 7) == 0xd) {
2675 // alex-ykl fix: 2011-07-20 missing ldrsb instruction 2675 // alex-ykl fix: 2011-07-20 missing ldrsb instruction
2676 temp = LHS + GetLS7RHS (state, instr); 2676 temp = LHS + GetLS7RHS (state, instr);
2677 LoadByte (state, instr, temp, LSIGNED); 2677 LoadByte (state, instr, temp, LSIGNED);
2678 break; 2678 break;
2679 } 2679 }
2680 2680
2681 /* Continue with instruction decoding. */ 2681 /* Continue with instruction decoding. */
2682 /*if ((BITS (4, 7) & 0x9) == 0x9) */ 2682 /*if ((BITS (4, 7) & 0x9) == 0x9) */
2683 if ((BITS (4, 7)) == 0x9) { 2683 if ((BITS (4, 7)) == 0x9) {
2684 /* ldrexb */ 2684 /* ldrexb */
2685 if (state->is_v6) { 2685 if (state->is_v6) {
2686 if (handle_v6_insn (state, instr)) 2686 if (handle_v6_insn (state, instr))
2687 break; 2687 break;
2688 } 2688 }
2689 /* LDR immediate offset, no write-back, up, pre indexed. */ 2689 /* LDR immediate offset, no write-back, up, pre indexed. */
2690 LHPREUP (); 2690 LHPREUP ();
2691 2691
2692 } 2692 }
2693 2693
2694#endif 2694#endif
2695 rhs = DPSRegRHS; 2695 rhs = DPSRegRHS;
2696 dest = LHS & ~rhs; 2696 dest = LHS & ~rhs;
2697 WRITESDEST (dest); 2697 WRITESDEST (dest);
2698 break; 2698 break;
2699 2699
2700 case 0x1e: /* MVN reg */ 2700 case 0x1e: /* MVN reg */
2701#ifdef MODET 2701#ifdef MODET
2702 if (BITS (4, 7) == 0xB) { 2702 if (BITS (4, 7) == 0xB) {
2703 /* STRH immediate offset, write-back, up, pre indexed. */ 2703 /* STRH immediate offset, write-back, up, pre indexed. */
2704 SHPREUPWB (); 2704 SHPREUPWB ();
2705 break; 2705 break;
2706 } 2706 }
2707 if (BITS (4, 7) == 0xD) { 2707 if (BITS (4, 7) == 0xD) {
2708 Handle_Load_Double (state, instr); 2708 Handle_Load_Double (state, instr);
2709 break; 2709 break;
2710 } 2710 }
2711 if (BITS (4, 7) == 0xF) { 2711 if (BITS (4, 7) == 0xF) {
2712 Handle_Store_Double (state, instr); 2712 Handle_Store_Double (state, instr);
2713 break; 2713 break;
2714 } 2714 }
2715#endif 2715#endif
2716 dest = ~DPRegRHS; 2716 dest = ~DPRegRHS;
2717 WRITEDEST (dest); 2717 WRITEDEST (dest);
2718 break; 2718 break;
2719 2719
2720 case 0x1f: /* MVNS reg */ 2720 case 0x1f: /* MVNS reg */
2721#ifdef MODET 2721#ifdef MODET
2722 if ((BITS (4, 7) & 0x9) == 0x9) 2722 if ((BITS (4, 7) & 0x9) == 0x9)
2723 /* LDR immediate offset, write-back, up, pre indexed. */ 2723 /* LDR immediate offset, write-back, up, pre indexed. */
2724 LHPREUPWB (); 2724 LHPREUPWB ();
2725 /* Continue instruction decoding. */ 2725 /* Continue instruction decoding. */
2726#endif 2726#endif
2727 dest = ~DPSRegRHS; 2727 dest = ~DPSRegRHS;
2728 WRITESDEST (dest); 2728 WRITESDEST (dest);
2729 break; 2729 break;
2730 2730
2731 2731
2732 /* Data Processing Immediate RHS Instructions. */ 2732 /* Data Processing Immediate RHS Instructions. */
2733 2733
2734 case 0x20: /* AND immed */ 2734 case 0x20: /* AND immed */
2735 dest = LHS & DPImmRHS; 2735 dest = LHS & DPImmRHS;
2736 WRITEDEST (dest); 2736 WRITEDEST (dest);
2737 break; 2737 break;
2738 2738
2739 case 0x21: /* ANDS immed */ 2739 case 0x21: /* ANDS immed */
2740 DPSImmRHS; 2740 DPSImmRHS;
2741 dest = LHS & rhs; 2741 dest = LHS & rhs;
2742 WRITESDEST (dest); 2742 WRITESDEST (dest);
2743 break; 2743 break;
2744 2744
2745 case 0x22: /* EOR immed */ 2745 case 0x22: /* EOR immed */
2746 dest = LHS ^ DPImmRHS; 2746 dest = LHS ^ DPImmRHS;
2747 WRITEDEST (dest); 2747 WRITEDEST (dest);
2748 break; 2748 break;
2749 2749
2750 case 0x23: /* EORS immed */ 2750 case 0x23: /* EORS immed */
2751 DPSImmRHS; 2751 DPSImmRHS;
2752 dest = LHS ^ rhs; 2752 dest = LHS ^ rhs;
2753 WRITESDEST (dest); 2753 WRITESDEST (dest);
2754 break; 2754 break;
2755 2755
2756 case 0x24: /* SUB immed */ 2756 case 0x24: /* SUB immed */
2757 dest = LHS - DPImmRHS; 2757 dest = LHS - DPImmRHS;
2758 WRITEDEST (dest); 2758 WRITEDEST (dest);
2759 break; 2759 break;
2760 2760
2761 case 0x25: /* SUBS immed */ 2761 case 0x25: /* SUBS immed */
2762 lhs = LHS; 2762 lhs = LHS;
2763 rhs = DPImmRHS; 2763 rhs = DPImmRHS;
2764 dest = lhs - rhs; 2764 dest = lhs - rhs;
2765 2765
2766 if ((lhs >= rhs) || ((rhs | lhs) >> 31)) { 2766 if ((lhs >= rhs) || ((rhs | lhs) >> 31)) {
2767 ARMul_SubCarry (state, lhs, rhs, 2767 ARMul_SubCarry (state, lhs, rhs,
2768 dest); 2768 dest);
2769 ARMul_SubOverflow (state, lhs, rhs, 2769 ARMul_SubOverflow (state, lhs, rhs,
2770 dest); 2770 dest);
2771 } 2771 }
2772 else { 2772 else {
2773 CLEARC; 2773 CLEARC;
2774 CLEARV; 2774 CLEARV;
2775 } 2775 }
2776 WRITESDEST (dest); 2776 WRITESDEST (dest);
2777 break; 2777 break;
2778 2778
2779 case 0x26: /* RSB immed */ 2779 case 0x26: /* RSB immed */
2780 dest = DPImmRHS - LHS; 2780 dest = DPImmRHS - LHS;
2781 WRITEDEST (dest); 2781 WRITEDEST (dest);
2782 break; 2782 break;
2783 2783
2784 case 0x27: /* RSBS immed */ 2784 case 0x27: /* RSBS immed */
2785 lhs = LHS; 2785 lhs = LHS;
2786 rhs = DPImmRHS; 2786 rhs = DPImmRHS;
2787 dest = rhs - lhs; 2787 dest = rhs - lhs;
2788 2788
2789 if ((rhs >= lhs) || ((rhs | lhs) >> 31)) { 2789 if ((rhs >= lhs) || ((rhs | lhs) >> 31)) {
2790 ARMul_SubCarry (state, rhs, lhs, 2790 ARMul_SubCarry (state, rhs, lhs,
2791 dest); 2791 dest);
2792 ARMul_SubOverflow (state, rhs, lhs, 2792 ARMul_SubOverflow (state, rhs, lhs,
2793 dest); 2793 dest);
2794 } 2794 }
2795 else { 2795 else {
2796 CLEARC; 2796 CLEARC;
2797 CLEARV; 2797 CLEARV;
2798 } 2798 }
2799 WRITESDEST (dest); 2799 WRITESDEST (dest);
2800 break; 2800 break;
2801 2801
2802 case 0x28: /* ADD immed */ 2802 case 0x28: /* ADD immed */
2803 dest = LHS + DPImmRHS; 2803 dest = LHS + DPImmRHS;
2804 WRITEDEST (dest); 2804 WRITEDEST (dest);
2805 break; 2805 break;
2806 2806
2807 case 0x29: /* ADDS immed */ 2807 case 0x29: /* ADDS immed */
2808 lhs = LHS; 2808 lhs = LHS;
2809 rhs = DPImmRHS; 2809 rhs = DPImmRHS;
2810 dest = lhs + rhs; 2810 dest = lhs + rhs;
2811 ASSIGNZ (dest == 0); 2811 ASSIGNZ (dest == 0);
2812 2812
2813 if ((lhs | rhs) >> 30) { 2813 if ((lhs | rhs) >> 30) {
2814 /* Possible C,V,N to set. */ 2814 /* Possible C,V,N to set. */
2815 ASSIGNN (NEG (dest)); 2815 ASSIGNN (NEG (dest));
2816 ARMul_AddCarry (state, lhs, rhs, 2816 ARMul_AddCarry (state, lhs, rhs,
2817 dest); 2817 dest);
2818 ARMul_AddOverflow (state, lhs, rhs, 2818 ARMul_AddOverflow (state, lhs, rhs,
2819 dest); 2819 dest);
2820 } 2820 }
2821 else { 2821 else {
2822 CLEARN; 2822 CLEARN;
2823 CLEARC; 2823 CLEARC;
2824 CLEARV; 2824 CLEARV;
2825 } 2825 }
2826 WRITESDEST (dest); 2826 WRITESDEST (dest);
2827 break; 2827 break;
2828 2828
2829 case 0x2a: /* ADC immed */ 2829 case 0x2a: /* ADC immed */
2830 dest = LHS + DPImmRHS + CFLAG; 2830 dest = LHS + DPImmRHS + CFLAG;
2831 WRITEDEST (dest); 2831 WRITEDEST (dest);
2832 break; 2832 break;
2833 2833
2834 case 0x2b: /* ADCS immed */ 2834 case 0x2b: /* ADCS immed */
2835 lhs = LHS; 2835 lhs = LHS;
2836 rhs = DPImmRHS; 2836 rhs = DPImmRHS;
2837 dest = lhs + rhs + CFLAG; 2837 dest = lhs + rhs + CFLAG;
2838 ASSIGNZ (dest == 0); 2838 ASSIGNZ (dest == 0);
2839 if ((lhs | rhs) >> 30) { 2839 if ((lhs | rhs) >> 30) {
2840 /* Possible C,V,N to set. */ 2840 /* Possible C,V,N to set. */
2841 ASSIGNN (NEG (dest)); 2841 ASSIGNN (NEG (dest));
2842 ARMul_AddCarry (state, lhs, rhs, 2842 ARMul_AddCarry (state, lhs, rhs,
2843 dest); 2843 dest);
2844 ARMul_AddOverflow (state, lhs, rhs, 2844 ARMul_AddOverflow (state, lhs, rhs,
2845 dest); 2845 dest);
2846 } 2846 }
2847 else { 2847 else {
2848 CLEARN; 2848 CLEARN;
2849 CLEARC; 2849 CLEARC;
2850 CLEARV; 2850 CLEARV;
2851 } 2851 }
2852 WRITESDEST (dest); 2852 WRITESDEST (dest);
2853 break; 2853 break;
2854 2854
2855 case 0x2c: /* SBC immed */ 2855 case 0x2c: /* SBC immed */
2856 dest = LHS - DPImmRHS - !CFLAG; 2856 dest = LHS - DPImmRHS - !CFLAG;
2857 WRITEDEST (dest); 2857 WRITEDEST (dest);
2858 break; 2858 break;
2859 2859
2860 case 0x2d: /* SBCS immed */ 2860 case 0x2d: /* SBCS immed */
2861 lhs = LHS; 2861 lhs = LHS;
2862 rhs = DPImmRHS; 2862 rhs = DPImmRHS;
2863 dest = lhs - rhs - !CFLAG; 2863 dest = lhs - rhs - !CFLAG;
2864 if ((lhs >= rhs) || ((rhs | lhs) >> 31)) { 2864 if ((lhs >= rhs) || ((rhs | lhs) >> 31)) {
2865 ARMul_SubCarry (state, lhs, rhs, 2865 ARMul_SubCarry (state, lhs, rhs,
2866 dest); 2866 dest);
2867 ARMul_SubOverflow (state, lhs, rhs, 2867 ARMul_SubOverflow (state, lhs, rhs,
2868 dest); 2868 dest);
2869 } 2869 }
2870 else { 2870 else {
2871 CLEARC; 2871 CLEARC;
2872 CLEARV; 2872 CLEARV;
2873 } 2873 }
2874 WRITESDEST (dest); 2874 WRITESDEST (dest);
2875 break; 2875 break;
2876 2876
2877 case 0x2e: /* RSC immed */ 2877 case 0x2e: /* RSC immed */
2878 dest = DPImmRHS - LHS - !CFLAG; 2878 dest = DPImmRHS - LHS - !CFLAG;
2879 WRITEDEST (dest); 2879 WRITEDEST (dest);
2880 break; 2880 break;
2881 2881
2882 case 0x2f: /* RSCS immed */ 2882 case 0x2f: /* RSCS immed */
2883 lhs = LHS; 2883 lhs = LHS;
2884 rhs = DPImmRHS; 2884 rhs = DPImmRHS;
2885 dest = rhs - lhs - !CFLAG; 2885 dest = rhs - lhs - !CFLAG;
2886 if ((rhs >= lhs) || ((rhs | lhs) >> 31)) { 2886 if ((rhs >= lhs) || ((rhs | lhs) >> 31)) {
2887 ARMul_SubCarry (state, rhs, lhs, 2887 ARMul_SubCarry (state, rhs, lhs,
2888 dest); 2888 dest);
2889 ARMul_SubOverflow (state, rhs, lhs, 2889 ARMul_SubOverflow (state, rhs, lhs,
2890 dest); 2890 dest);
2891 } 2891 }
2892 else { 2892 else {
2893 CLEARC; 2893 CLEARC;
2894 CLEARV; 2894 CLEARV;
2895 } 2895 }
2896 WRITESDEST (dest); 2896 WRITESDEST (dest);
2897 break; 2897 break;
2898 2898
2899 case 0x30: /* TST immed */ 2899 case 0x30: /* TST immed */
2900 /* shenoubang 2012-3-14*/ 2900 /* shenoubang 2012-3-14*/
2901 if (state->is_v6) { /* movw, ARMV6, ARMv7 */ 2901 if (state->is_v6) { /* movw, ARMV6, ARMv7 */
2902 dest ^= dest; 2902 dest ^= dest;
2903 dest = BITS(16, 19); 2903 dest = BITS(16, 19);
2904 dest = ((dest<<12) | BITS(0, 11)); 2904 dest = ((dest<<12) | BITS(0, 11));
2905 WRITEDEST(dest); 2905 WRITEDEST(dest);
2906 //SKYEYE_DBG("In %s, line = %d, pc = 0x%x, instr = 0x%x, R[0:11]: 0x%x, R[16:19]: 0x%x, R[%d]:0x%x\n", 2906 //SKYEYE_DBG("In %s, line = %d, pc = 0x%x, instr = 0x%x, R[0:11]: 0x%x, R[16:19]: 0x%x, R[%d]:0x%x\n",
2907 // __func__, __LINE__, pc, instr, BITS(0, 11), BITS(16, 19), DESTReg, state->Reg[DESTReg]); 2907 // __func__, __LINE__, pc, instr, BITS(0, 11), BITS(16, 19), DESTReg, state->Reg[DESTReg]);
2908 break; 2908 break;
2909 } 2909 }
2910 else { 2910 else {
2911 UNDEF_Test; 2911 UNDEF_Test;
2912 break; 2912 break;
2913 } 2913 }
2914 2914
2915 case 0x31: /* TSTP immed */ 2915 case 0x31: /* TSTP immed */
2916 if (DESTReg == 15) { 2916 if (DESTReg == 15) {
2917 /* TSTP immed. */ 2917 /* TSTP immed. */
2918#ifdef MODE32 2918#ifdef MODE32
2919 state->Cpsr = GETSPSR (state->Bank); 2919 state->Cpsr = GETSPSR (state->Bank);
2920 ARMul_CPSRAltered (state); 2920 ARMul_CPSRAltered (state);
2921#else 2921#else
2922 temp = LHS & DPImmRHS; 2922 temp = LHS & DPImmRHS;
2923 SETR15PSR (temp); 2923 SETR15PSR (temp);
2924#endif 2924#endif
2925 } 2925 }
2926 else { 2926 else {
2927 /* TST immed. */ 2927 /* TST immed. */
2928 DPSImmRHS; 2928 DPSImmRHS;
2929 dest = LHS & rhs; 2929 dest = LHS & rhs;
2930 ARMul_NegZero (state, dest); 2930 ARMul_NegZero (state, dest);
2931 } 2931 }
2932 break; 2932 break;
2933 2933
2934 case 0x32: /* TEQ immed and MSR immed to CPSR */ 2934 case 0x32: /* TEQ immed and MSR immed to CPSR */
2935 if (DESTReg == 15) 2935 if (DESTReg == 15)
2936 /* MSR immed to CPSR. */ 2936 /* MSR immed to CPSR. */
2937 ARMul_FixCPSR (state, instr, 2937 ARMul_FixCPSR (state, instr,
2938 DPImmRHS); 2938 DPImmRHS);
2939 else 2939 else
2940 UNDEF_Test; 2940 UNDEF_Test;
2941 break; 2941 break;
2942 2942
2943 case 0x33: /* TEQP immed */ 2943 case 0x33: /* TEQP immed */
2944 if (DESTReg == 15) { 2944 if (DESTReg == 15) {
2945 /* TEQP immed. */ 2945 /* TEQP immed. */
2946#ifdef MODE32 2946#ifdef MODE32
2947 state->Cpsr = GETSPSR (state->Bank); 2947 state->Cpsr = GETSPSR (state->Bank);
2948 ARMul_CPSRAltered (state); 2948 ARMul_CPSRAltered (state);
2949#else 2949#else
2950 temp = LHS ^ DPImmRHS; 2950 temp = LHS ^ DPImmRHS;
2951 SETR15PSR (temp); 2951 SETR15PSR (temp);
2952#endif 2952#endif
2953 } 2953 }
2954 else { 2954 else {
2955 DPSImmRHS; /* TEQ immed */ 2955 DPSImmRHS; /* TEQ immed */
2956 dest = LHS ^ rhs; 2956 dest = LHS ^ rhs;
2957 ARMul_NegZero (state, dest); 2957 ARMul_NegZero (state, dest);
2958 } 2958 }
2959 break; 2959 break;
2960 2960
2961 case 0x34: /* CMP immed */ 2961 case 0x34: /* CMP immed */
2962 UNDEF_Test; 2962 UNDEF_Test;
2963 break; 2963 break;
2964 2964
2965 case 0x35: /* CMPP immed */ 2965 case 0x35: /* CMPP immed */
2966 if (DESTReg == 15) { 2966 if (DESTReg == 15) {
2967 /* CMPP immed. */ 2967 /* CMPP immed. */
2968#ifdef MODE32 2968#ifdef MODE32
2969 state->Cpsr = GETSPSR (state->Bank); 2969 state->Cpsr = GETSPSR (state->Bank);
2970 ARMul_CPSRAltered (state); 2970 ARMul_CPSRAltered (state);
2971#else 2971#else
2972 temp = LHS - DPImmRHS; 2972 temp = LHS - DPImmRHS;
2973 SETR15PSR (temp); 2973 SETR15PSR (temp);
2974#endif 2974#endif
2975 break; 2975 break;
2976 } 2976 }
2977 else { 2977 else {
2978 /* CMP immed. */ 2978 /* CMP immed. */
2979 lhs = LHS; 2979 lhs = LHS;
2980 rhs = DPImmRHS; 2980 rhs = DPImmRHS;
2981 dest = lhs - rhs; 2981 dest = lhs - rhs;
2982 ARMul_NegZero (state, dest); 2982 ARMul_NegZero (state, dest);
2983 2983
2984 if ((lhs >= rhs) 2984 if ((lhs >= rhs)
2985 || ((rhs | lhs) >> 31)) { 2985 || ((rhs | lhs) >> 31)) {
2986 ARMul_SubCarry (state, lhs, 2986 ARMul_SubCarry (state, lhs,
2987 rhs, dest); 2987 rhs, dest);
2988 ARMul_SubOverflow (state, lhs, 2988 ARMul_SubOverflow (state, lhs,
2989 rhs, dest); 2989 rhs, dest);
2990 } 2990 }
2991 else { 2991 else {
2992 CLEARC; 2992 CLEARC;
2993 CLEARV; 2993 CLEARV;
2994 } 2994 }
2995 } 2995 }
2996 break; 2996 break;
2997 2997
2998 case 0x36: /* CMN immed and MSR immed to SPSR */ 2998 case 0x36: /* CMN immed and MSR immed to SPSR */
2999 if (DESTReg == 15) 2999 if (DESTReg == 15)
3000 ARMul_FixSPSR (state, instr, 3000 ARMul_FixSPSR (state, instr,
3001 DPImmRHS); 3001 DPImmRHS);
3002 else 3002 else
3003 UNDEF_Test; 3003 UNDEF_Test;
3004 break; 3004 break;
3005 3005
3006 case 0x37: /* CMNP immed. */ 3006 case 0x37: /* CMNP immed. */
3007 if (DESTReg == 15) { 3007 if (DESTReg == 15) {
3008 /* CMNP immed. */ 3008 /* CMNP immed. */
3009#ifdef MODE32 3009#ifdef MODE32
3010 state->Cpsr = GETSPSR (state->Bank); 3010 state->Cpsr = GETSPSR (state->Bank);
3011 ARMul_CPSRAltered (state); 3011 ARMul_CPSRAltered (state);
3012#else 3012#else
3013 temp = LHS + DPImmRHS; 3013 temp = LHS + DPImmRHS;
3014 SETR15PSR (temp); 3014 SETR15PSR (temp);
3015#endif 3015#endif
3016 break; 3016 break;
3017 } 3017 }
3018 else { 3018 else {
3019 /* CMN immed. */ 3019 /* CMN immed. */
3020 lhs = LHS; 3020 lhs = LHS;
3021 rhs = DPImmRHS; 3021 rhs = DPImmRHS;
3022 dest = lhs + rhs; 3022 dest = lhs + rhs;
3023 ASSIGNZ (dest == 0); 3023 ASSIGNZ (dest == 0);
3024 if ((lhs | rhs) >> 30) { 3024 if ((lhs | rhs) >> 30) {
3025 /* Possible C,V,N to set. */ 3025 /* Possible C,V,N to set. */
3026 ASSIGNN (NEG (dest)); 3026 ASSIGNN (NEG (dest));
3027 ARMul_AddCarry (state, lhs, 3027 ARMul_AddCarry (state, lhs,
3028 rhs, dest); 3028 rhs, dest);
3029 ARMul_AddOverflow (state, lhs, 3029 ARMul_AddOverflow (state, lhs,
3030 rhs, dest); 3030 rhs, dest);
3031 } 3031 }
3032 else { 3032 else {
3033 CLEARN; 3033 CLEARN;
3034 CLEARC; 3034 CLEARC;
3035 CLEARV; 3035 CLEARV;
3036 } 3036 }
3037 } 3037 }
3038 break; 3038 break;
3039 3039
3040 case 0x38: /* ORR immed. */ 3040 case 0x38: /* ORR immed. */
3041 dest = LHS | DPImmRHS; 3041 dest = LHS | DPImmRHS;
3042 WRITEDEST (dest); 3042 WRITEDEST (dest);
3043 break; 3043 break;
3044 3044
3045 case 0x39: /* ORRS immed. */ 3045 case 0x39: /* ORRS immed. */
3046 DPSImmRHS; 3046 DPSImmRHS;
3047 dest = LHS | rhs; 3047 dest = LHS | rhs;
3048 WRITESDEST (dest); 3048 WRITESDEST (dest);
3049 break; 3049 break;
3050 3050
3051 case 0x3a: /* MOV immed. */ 3051 case 0x3a: /* MOV immed. */
3052 dest = DPImmRHS; 3052 dest = DPImmRHS;
3053 WRITEDEST (dest); 3053 WRITEDEST (dest);
3054 break; 3054 break;
3055 3055
3056 case 0x3b: /* MOVS immed. */ 3056 case 0x3b: /* MOVS immed. */
3057 DPSImmRHS; 3057 DPSImmRHS;
3058 WRITESDEST (rhs); 3058 WRITESDEST (rhs);
3059 break; 3059 break;
3060 3060
3061 case 0x3c: /* BIC immed. */ 3061 case 0x3c: /* BIC immed. */
3062 dest = LHS & ~DPImmRHS; 3062 dest = LHS & ~DPImmRHS;
3063 WRITEDEST (dest); 3063 WRITEDEST (dest);
3064 break; 3064 break;
3065 3065
3066 case 0x3d: /* BICS immed. */ 3066 case 0x3d: /* BICS immed. */
3067 DPSImmRHS; 3067 DPSImmRHS;
3068 dest = LHS & ~rhs; 3068 dest = LHS & ~rhs;
3069 WRITESDEST (dest); 3069 WRITESDEST (dest);
3070 break; 3070 break;
3071 3071
3072 case 0x3e: /* MVN immed. */ 3072 case 0x3e: /* MVN immed. */
3073 dest = ~DPImmRHS; 3073 dest = ~DPImmRHS;
3074 WRITEDEST (dest); 3074 WRITEDEST (dest);
3075 break; 3075 break;
3076 3076
3077 case 0x3f: /* MVNS immed. */ 3077 case 0x3f: /* MVNS immed. */
3078 DPSImmRHS; 3078 DPSImmRHS;
3079 WRITESDEST (~rhs); 3079 WRITESDEST (~rhs);
3080 break; 3080 break;
3081 3081
3082 3082
3083 /* Single Data Transfer Immediate RHS Instructions. */ 3083 /* Single Data Transfer Immediate RHS Instructions. */
3084 3084
3085 case 0x40: /* Store Word, No WriteBack, Post Dec, Immed. */ 3085 case 0x40: /* Store Word, No WriteBack, Post Dec, Immed. */
3086 lhs = LHS; 3086 lhs = LHS;
3087 if (StoreWord (state, instr, lhs)) 3087 if (StoreWord (state, instr, lhs))
3088 LSBase = lhs - LSImmRHS; 3088 LSBase = lhs - LSImmRHS;
3089 break; 3089 break;
3090 3090
3091 case 0x41: /* Load Word, No WriteBack, Post Dec, Immed. */ 3091 case 0x41: /* Load Word, No WriteBack, Post Dec, Immed. */
3092 lhs = LHS; 3092 lhs = LHS;
3093 if (LoadWord (state, instr, lhs)) 3093 if (LoadWord (state, instr, lhs))
3094 LSBase = lhs - LSImmRHS; 3094 LSBase = lhs - LSImmRHS;
3095 break; 3095 break;
3096 3096
3097 case 0x42: /* Store Word, WriteBack, Post Dec, Immed. */ 3097 case 0x42: /* Store Word, WriteBack, Post Dec, Immed. */
3098 UNDEF_LSRBaseEQDestWb; 3098 UNDEF_LSRBaseEQDestWb;
3099 UNDEF_LSRPCBaseWb; 3099 UNDEF_LSRPCBaseWb;
3100 lhs = LHS; 3100 lhs = LHS;
3101 temp = lhs - LSImmRHS; 3101 temp = lhs - LSImmRHS;
3102 state->NtransSig = LOW; 3102 state->NtransSig = LOW;
3103 if (StoreWord (state, instr, lhs)) 3103 if (StoreWord (state, instr, lhs))
3104 LSBase = temp; 3104 LSBase = temp;
3105 state->NtransSig = 3105 state->NtransSig =
3106 (state->Mode & 3) ? HIGH : LOW; 3106 (state->Mode & 3) ? HIGH : LOW;
3107 break; 3107 break;
3108 3108
3109 case 0x43: /* Load Word, WriteBack, Post Dec, Immed. */ 3109 case 0x43: /* Load Word, WriteBack, Post Dec, Immed. */
3110 UNDEF_LSRBaseEQDestWb; 3110 UNDEF_LSRBaseEQDestWb;
3111 UNDEF_LSRPCBaseWb; 3111 UNDEF_LSRPCBaseWb;
3112 lhs = LHS; 3112 lhs = LHS;
3113 state->NtransSig = LOW; 3113 state->NtransSig = LOW;
3114 if (LoadWord (state, instr, lhs)) 3114 if (LoadWord (state, instr, lhs))
3115 LSBase = lhs - LSImmRHS; 3115 LSBase = lhs - LSImmRHS;
3116 state->NtransSig = 3116 state->NtransSig =
3117 (state->Mode & 3) ? HIGH : LOW; 3117 (state->Mode & 3) ? HIGH : LOW;
3118 break; 3118 break;
3119 3119
3120 case 0x44: /* Store Byte, No WriteBack, Post Dec, Immed. */ 3120 case 0x44: /* Store Byte, No WriteBack, Post Dec, Immed. */
3121 lhs = LHS; 3121 lhs = LHS;
3122 if (StoreByte (state, instr, lhs)) 3122 if (StoreByte (state, instr, lhs))
3123 LSBase = lhs - LSImmRHS; 3123 LSBase = lhs - LSImmRHS;
3124 break; 3124 break;
3125 3125
3126 case 0x45: /* Load Byte, No WriteBack, Post Dec, Immed. */ 3126 case 0x45: /* Load Byte, No WriteBack, Post Dec, Immed. */
3127 lhs = LHS; 3127 lhs = LHS;
3128 if (LoadByte (state, instr, lhs, LUNSIGNED)) 3128 if (LoadByte (state, instr, lhs, LUNSIGNED))
3129 LSBase = lhs - LSImmRHS; 3129 LSBase = lhs - LSImmRHS;
3130 break; 3130 break;
3131 3131
3132 case 0x46: /* Store Byte, WriteBack, Post Dec, Immed. */ 3132 case 0x46: /* Store Byte, WriteBack, Post Dec, Immed. */
3133 UNDEF_LSRBaseEQDestWb; 3133 UNDEF_LSRBaseEQDestWb;
3134 UNDEF_LSRPCBaseWb; 3134 UNDEF_LSRPCBaseWb;
3135 lhs = LHS; 3135 lhs = LHS;
3136 state->NtransSig = LOW; 3136 state->NtransSig = LOW;
3137 if (StoreByte (state, instr, lhs)) 3137 if (StoreByte (state, instr, lhs))
3138 LSBase = lhs - LSImmRHS; 3138 LSBase = lhs - LSImmRHS;
3139 state->NtransSig = 3139 state->NtransSig =
3140 (state->Mode & 3) ? HIGH : LOW; 3140 (state->Mode & 3) ? HIGH : LOW;
3141 break; 3141 break;
3142 3142
3143 case 0x47: /* Load Byte, WriteBack, Post Dec, Immed. */ 3143 case 0x47: /* Load Byte, WriteBack, Post Dec, Immed. */
3144 UNDEF_LSRBaseEQDestWb; 3144 UNDEF_LSRBaseEQDestWb;
3145 UNDEF_LSRPCBaseWb; 3145 UNDEF_LSRPCBaseWb;
3146 lhs = LHS; 3146 lhs = LHS;
3147 state->NtransSig = LOW; 3147 state->NtransSig = LOW;
3148 if (LoadByte (state, instr, lhs, LUNSIGNED)) 3148 if (LoadByte (state, instr, lhs, LUNSIGNED))
3149 LSBase = lhs - LSImmRHS; 3149 LSBase = lhs - LSImmRHS;
3150 state->NtransSig = 3150 state->NtransSig =
3151 (state->Mode & 3) ? HIGH : LOW; 3151 (state->Mode & 3) ? HIGH : LOW;
3152 break; 3152 break;
3153 3153
3154 case 0x48: /* Store Word, No WriteBack, Post Inc, Immed. */ 3154 case 0x48: /* Store Word, No WriteBack, Post Inc, Immed. */
3155 lhs = LHS; 3155 lhs = LHS;
3156 if (StoreWord (state, instr, lhs)) 3156 if (StoreWord (state, instr, lhs))
3157 LSBase = lhs + LSImmRHS; 3157 LSBase = lhs + LSImmRHS;
3158 break; 3158 break;
3159 3159
3160 case 0x49: /* Load Word, No WriteBack, Post Inc, Immed. */ 3160 case 0x49: /* Load Word, No WriteBack, Post Inc, Immed. */
3161 lhs = LHS; 3161 lhs = LHS;
3162 if (LoadWord (state, instr, lhs)) 3162 if (LoadWord (state, instr, lhs))
3163 LSBase = lhs + LSImmRHS; 3163 LSBase = lhs + LSImmRHS;
3164 break; 3164 break;
3165 3165
3166 case 0x4a: /* Store Word, WriteBack, Post Inc, Immed. */ 3166 case 0x4a: /* Store Word, WriteBack, Post Inc, Immed. */
3167 UNDEF_LSRBaseEQDestWb; 3167 UNDEF_LSRBaseEQDestWb;
3168 UNDEF_LSRPCBaseWb; 3168 UNDEF_LSRPCBaseWb;
3169 lhs = LHS; 3169 lhs = LHS;
3170 state->NtransSig = LOW; 3170 state->NtransSig = LOW;
3171 if (StoreWord (state, instr, lhs)) 3171 if (StoreWord (state, instr, lhs))
3172 LSBase = lhs + LSImmRHS; 3172 LSBase = lhs + LSImmRHS;
3173 state->NtransSig = 3173 state->NtransSig =
3174 (state->Mode & 3) ? HIGH : LOW; 3174 (state->Mode & 3) ? HIGH : LOW;
3175 break; 3175 break;
3176 3176
3177 case 0x4b: /* Load Word, WriteBack, Post Inc, Immed. */ 3177 case 0x4b: /* Load Word, WriteBack, Post Inc, Immed. */
3178 UNDEF_LSRBaseEQDestWb; 3178 UNDEF_LSRBaseEQDestWb;
3179 UNDEF_LSRPCBaseWb; 3179 UNDEF_LSRPCBaseWb;
3180 lhs = LHS; 3180 lhs = LHS;
3181 state->NtransSig = LOW; 3181 state->NtransSig = LOW;
3182 if (LoadWord (state, instr, lhs)) 3182 if (LoadWord (state, instr, lhs))
3183 LSBase = lhs + LSImmRHS; 3183 LSBase = lhs + LSImmRHS;
3184 state->NtransSig = 3184 state->NtransSig =
3185 (state->Mode & 3) ? HIGH : LOW; 3185 (state->Mode & 3) ? HIGH : LOW;
3186 break; 3186 break;
3187 3187
3188 case 0x4c: /* Store Byte, No WriteBack, Post Inc, Immed. */ 3188 case 0x4c: /* Store Byte, No WriteBack, Post Inc, Immed. */
3189 lhs = LHS; 3189 lhs = LHS;
3190 if (StoreByte (state, instr, lhs)) 3190 if (StoreByte (state, instr, lhs))
3191 LSBase = lhs + LSImmRHS; 3191 LSBase = lhs + LSImmRHS;
3192 break; 3192 break;
3193 3193
3194 case 0x4d: /* Load Byte, No WriteBack, Post Inc, Immed. */ 3194 case 0x4d: /* Load Byte, No WriteBack, Post Inc, Immed. */
3195 lhs = LHS; 3195 lhs = LHS;
3196 if (LoadByte (state, instr, lhs, LUNSIGNED)) 3196 if (LoadByte (state, instr, lhs, LUNSIGNED))
3197 LSBase = lhs + LSImmRHS; 3197 LSBase = lhs + LSImmRHS;
3198 break; 3198 break;
3199 3199
3200 case 0x4e: /* Store Byte, WriteBack, Post Inc, Immed. */ 3200 case 0x4e: /* Store Byte, WriteBack, Post Inc, Immed. */
3201 UNDEF_LSRBaseEQDestWb; 3201 UNDEF_LSRBaseEQDestWb;
3202 UNDEF_LSRPCBaseWb; 3202 UNDEF_LSRPCBaseWb;
3203 lhs = LHS; 3203 lhs = LHS;
3204 state->NtransSig = LOW; 3204 state->NtransSig = LOW;
3205 if (StoreByte (state, instr, lhs)) 3205 if (StoreByte (state, instr, lhs))
3206 LSBase = lhs + LSImmRHS; 3206 LSBase = lhs + LSImmRHS;
3207 state->NtransSig = 3207 state->NtransSig =
3208 (state->Mode & 3) ? HIGH : LOW; 3208 (state->Mode & 3) ? HIGH : LOW;
3209 break; 3209 break;
3210 3210
3211 case 0x4f: /* Load Byte, WriteBack, Post Inc, Immed. */ 3211 case 0x4f: /* Load Byte, WriteBack, Post Inc, Immed. */
3212 UNDEF_LSRBaseEQDestWb; 3212 UNDEF_LSRBaseEQDestWb;
3213 UNDEF_LSRPCBaseWb; 3213 UNDEF_LSRPCBaseWb;
3214 lhs = LHS; 3214 lhs = LHS;
3215 state->NtransSig = LOW; 3215 state->NtransSig = LOW;
3216 if (LoadByte (state, instr, lhs, LUNSIGNED)) 3216 if (LoadByte (state, instr, lhs, LUNSIGNED))
3217 LSBase = lhs + LSImmRHS; 3217 LSBase = lhs + LSImmRHS;
3218 state->NtransSig = 3218 state->NtransSig =
3219 (state->Mode & 3) ? HIGH : LOW; 3219 (state->Mode & 3) ? HIGH : LOW;
3220 break; 3220 break;
3221 3221
3222 3222
3223 case 0x50: /* Store Word, No WriteBack, Pre Dec, Immed. */ 3223 case 0x50: /* Store Word, No WriteBack, Pre Dec, Immed. */
3224 (void) StoreWord (state, instr, 3224 (void) StoreWord (state, instr,
3225 LHS - LSImmRHS); 3225 LHS - LSImmRHS);
3226 break; 3226 break;
3227 3227
3228 case 0x51: /* Load Word, No WriteBack, Pre Dec, Immed. */ 3228 case 0x51: /* Load Word, No WriteBack, Pre Dec, Immed. */
3229 (void) LoadWord (state, instr, 3229 (void) LoadWord (state, instr,
3230 LHS - LSImmRHS); 3230 LHS - LSImmRHS);
3231 break; 3231 break;
3232 3232
3233 case 0x52: /* Store Word, WriteBack, Pre Dec, Immed. */ 3233 case 0x52: /* Store Word, WriteBack, Pre Dec, Immed. */
3234 UNDEF_LSRBaseEQDestWb; 3234 UNDEF_LSRBaseEQDestWb;
3235 UNDEF_LSRPCBaseWb; 3235 UNDEF_LSRPCBaseWb;
3236 temp = LHS - LSImmRHS; 3236 temp = LHS - LSImmRHS;
3237 if (StoreWord (state, instr, temp)) 3237 if (StoreWord (state, instr, temp))
3238 LSBase = temp; 3238 LSBase = temp;
3239 break; 3239 break;
3240 3240
3241 case 0x53: /* Load Word, WriteBack, Pre Dec, Immed. */ 3241 case 0x53: /* Load Word, WriteBack, Pre Dec, Immed. */
3242 UNDEF_LSRBaseEQDestWb; 3242 UNDEF_LSRBaseEQDestWb;
3243 UNDEF_LSRPCBaseWb; 3243 UNDEF_LSRPCBaseWb;
3244 temp = LHS - LSImmRHS; 3244 temp = LHS - LSImmRHS;
3245 if (LoadWord (state, instr, temp)) 3245 if (LoadWord (state, instr, temp))
3246 LSBase = temp; 3246 LSBase = temp;
3247 break; 3247 break;
3248 3248
3249 case 0x54: /* Store Byte, No WriteBack, Pre Dec, Immed. */ 3249 case 0x54: /* Store Byte, No WriteBack, Pre Dec, Immed. */
3250 (void) StoreByte (state, instr, 3250 (void) StoreByte (state, instr,
3251 LHS - LSImmRHS); 3251 LHS - LSImmRHS);
3252 break; 3252 break;
3253 3253
3254 case 0x55: /* Load Byte, No WriteBack, Pre Dec, Immed. */ 3254 case 0x55: /* Load Byte, No WriteBack, Pre Dec, Immed. */
3255 (void) LoadByte (state, instr, LHS - LSImmRHS, 3255 (void) LoadByte (state, instr, LHS - LSImmRHS,
3256 LUNSIGNED); 3256 LUNSIGNED);
3257 break; 3257 break;
3258 3258
3259 case 0x56: /* Store Byte, WriteBack, Pre Dec, Immed. */ 3259 case 0x56: /* Store Byte, WriteBack, Pre Dec, Immed. */
3260 UNDEF_LSRBaseEQDestWb; 3260 UNDEF_LSRBaseEQDestWb;
3261 UNDEF_LSRPCBaseWb; 3261 UNDEF_LSRPCBaseWb;
3262 temp = LHS - LSImmRHS; 3262 temp = LHS - LSImmRHS;
3263 if (StoreByte (state, instr, temp)) 3263 if (StoreByte (state, instr, temp))
3264 LSBase = temp; 3264 LSBase = temp;
3265 break; 3265 break;
3266 3266
3267 case 0x57: /* Load Byte, WriteBack, Pre Dec, Immed. */ 3267 case 0x57: /* Load Byte, WriteBack, Pre Dec, Immed. */
3268 UNDEF_LSRBaseEQDestWb; 3268 UNDEF_LSRBaseEQDestWb;
3269 UNDEF_LSRPCBaseWb; 3269 UNDEF_LSRPCBaseWb;
3270 temp = LHS - LSImmRHS; 3270 temp = LHS - LSImmRHS;
3271 if (LoadByte (state, instr, temp, LUNSIGNED)) 3271 if (LoadByte (state, instr, temp, LUNSIGNED))
3272 LSBase = temp; 3272 LSBase = temp;
3273 break; 3273 break;
3274 3274
3275 case 0x58: /* Store Word, No WriteBack, Pre Inc, Immed. */ 3275 case 0x58: /* Store Word, No WriteBack, Pre Inc, Immed. */
3276 (void) StoreWord (state, instr, 3276 (void) StoreWord (state, instr,
3277 LHS + LSImmRHS); 3277 LHS + LSImmRHS);
3278 break; 3278 break;
3279 3279
3280 case 0x59: /* Load Word, No WriteBack, Pre Inc, Immed. */ 3280 case 0x59: /* Load Word, No WriteBack, Pre Inc, Immed. */
3281 (void) LoadWord (state, instr, 3281 (void) LoadWord (state, instr,
3282 LHS + LSImmRHS); 3282 LHS + LSImmRHS);
3283 break; 3283 break;
3284 3284
3285 case 0x5a: /* Store Word, WriteBack, Pre Inc, Immed. */ 3285 case 0x5a: /* Store Word, WriteBack, Pre Inc, Immed. */
3286 UNDEF_LSRBaseEQDestWb; 3286 UNDEF_LSRBaseEQDestWb;
3287 UNDEF_LSRPCBaseWb; 3287 UNDEF_LSRPCBaseWb;
3288 temp = LHS + LSImmRHS; 3288 temp = LHS + LSImmRHS;
3289 if (StoreWord (state, instr, temp)) 3289 if (StoreWord (state, instr, temp))
3290 LSBase = temp; 3290 LSBase = temp;
3291 break; 3291 break;
3292 3292
3293 case 0x5b: /* Load Word, WriteBack, Pre Inc, Immed. */ 3293 case 0x5b: /* Load Word, WriteBack, Pre Inc, Immed. */
3294 UNDEF_LSRBaseEQDestWb; 3294 UNDEF_LSRBaseEQDestWb;
3295 UNDEF_LSRPCBaseWb; 3295 UNDEF_LSRPCBaseWb;
3296 temp = LHS + LSImmRHS; 3296 temp = LHS + LSImmRHS;
3297 if (LoadWord (state, instr, temp)) 3297 if (LoadWord (state, instr, temp))
3298 LSBase = temp; 3298 LSBase = temp;
3299 break; 3299 break;
3300 3300
3301 case 0x5c: /* Store Byte, No WriteBack, Pre Inc, Immed. */ 3301 case 0x5c: /* Store Byte, No WriteBack, Pre Inc, Immed. */
3302 (void) StoreByte (state, instr, 3302 (void) StoreByte (state, instr,
3303 LHS + LSImmRHS); 3303 LHS + LSImmRHS);
3304 break; 3304 break;
3305 3305
3306 case 0x5d: /* Load Byte, No WriteBack, Pre Inc, Immed. */ 3306 case 0x5d: /* Load Byte, No WriteBack, Pre Inc, Immed. */
3307 (void) LoadByte (state, instr, LHS + LSImmRHS, 3307 (void) LoadByte (state, instr, LHS + LSImmRHS,
3308 LUNSIGNED); 3308 LUNSIGNED);
3309 break; 3309 break;
3310 3310
3311 case 0x5e: /* Store Byte, WriteBack, Pre Inc, Immed. */ 3311 case 0x5e: /* Store Byte, WriteBack, Pre Inc, Immed. */
3312 UNDEF_LSRBaseEQDestWb; 3312 UNDEF_LSRBaseEQDestWb;
3313 UNDEF_LSRPCBaseWb; 3313 UNDEF_LSRPCBaseWb;
3314 temp = LHS + LSImmRHS; 3314 temp = LHS + LSImmRHS;
3315 if (StoreByte (state, instr, temp)) 3315 if (StoreByte (state, instr, temp))
3316 LSBase = temp; 3316 LSBase = temp;
3317 break; 3317 break;
3318 3318
3319 case 0x5f: /* Load Byte, WriteBack, Pre Inc, Immed. */ 3319 case 0x5f: /* Load Byte, WriteBack, Pre Inc, Immed. */
3320 UNDEF_LSRBaseEQDestWb; 3320 UNDEF_LSRBaseEQDestWb;
3321 UNDEF_LSRPCBaseWb; 3321 UNDEF_LSRPCBaseWb;
3322 temp = LHS + LSImmRHS; 3322 temp = LHS + LSImmRHS;
3323 if (LoadByte (state, instr, temp, LUNSIGNED)) 3323 if (LoadByte (state, instr, temp, LUNSIGNED))
3324 LSBase = temp; 3324 LSBase = temp;
3325 break; 3325 break;
3326 3326
3327 3327
3328 /* Single Data Transfer Register RHS Instructions. */ 3328 /* Single Data Transfer Register RHS Instructions. */
3329 3329
3330 case 0x60: /* Store Word, No WriteBack, Post Dec, Reg. */ 3330 case 0x60: /* Store Word, No WriteBack, Post Dec, Reg. */
3331 if (BIT (4)) { 3331 if (BIT (4)) {
3332 ARMul_UndefInstr (state, instr); 3332 ARMul_UndefInstr (state, instr);
3333 break; 3333 break;
3334 } 3334 }
3335 UNDEF_LSRBaseEQOffWb; 3335 UNDEF_LSRBaseEQOffWb;
3336 UNDEF_LSRBaseEQDestWb; 3336 UNDEF_LSRBaseEQDestWb;
3337 UNDEF_LSRPCBaseWb; 3337 UNDEF_LSRPCBaseWb;
3338 UNDEF_LSRPCOffWb; 3338 UNDEF_LSRPCOffWb;
3339 lhs = LHS; 3339 lhs = LHS;
3340 if (StoreWord (state, instr, lhs)) 3340 if (StoreWord (state, instr, lhs))
3341 LSBase = lhs - LSRegRHS; 3341 LSBase = lhs - LSRegRHS;
3342 break; 3342 break;
3343 3343
3344 case 0x61: /* Load Word, No WriteBack, Post Dec, Reg. */ 3344 case 0x61: /* Load Word, No WriteBack, Post Dec, Reg. */
3345 if (BIT (4)) { 3345 if (BIT (4)) {
3346#ifdef MODE32 3346#ifdef MODE32
3347 if (state->is_v6 3347 if (state->is_v6
3348 && handle_v6_insn (state, instr)) 3348 && handle_v6_insn (state, instr))
3349 break; 3349 break;
3350#endif 3350#endif
3351 3351
3352 ARMul_UndefInstr (state, instr); 3352 ARMul_UndefInstr (state, instr);
3353 break; 3353 break;
3354 } 3354 }
3355 UNDEF_LSRBaseEQOffWb; 3355 UNDEF_LSRBaseEQOffWb;
3356 UNDEF_LSRBaseEQDestWb; 3356 UNDEF_LSRBaseEQDestWb;
3357 UNDEF_LSRPCBaseWb; 3357 UNDEF_LSRPCBaseWb;
3358 UNDEF_LSRPCOffWb; 3358 UNDEF_LSRPCOffWb;
3359 lhs = LHS; 3359 lhs = LHS;
3360 temp = lhs - LSRegRHS; 3360 temp = lhs - LSRegRHS;
3361 if (LoadWord (state, instr, lhs)) 3361 if (LoadWord (state, instr, lhs))
3362 LSBase = temp; 3362 LSBase = temp;
3363 break; 3363 break;
3364 3364
3365 case 0x62: /* Store Word, WriteBack, Post Dec, Reg. */ 3365 case 0x62: /* Store Word, WriteBack, Post Dec, Reg. */
3366 if (BIT (4)) { 3366 if (BIT (4)) {
3367#ifdef MODE32 3367#ifdef MODE32
3368 if (state->is_v6 3368 if (state->is_v6
3369 && handle_v6_insn (state, instr)) 3369 && handle_v6_insn (state, instr))
3370 break; 3370 break;
3371#endif 3371#endif
3372 3372
3373 ARMul_UndefInstr (state, instr); 3373 ARMul_UndefInstr (state, instr);
3374 break; 3374 break;
3375 } 3375 }
3376 UNDEF_LSRBaseEQOffWb; 3376 UNDEF_LSRBaseEQOffWb;
3377 UNDEF_LSRBaseEQDestWb; 3377 UNDEF_LSRBaseEQDestWb;
3378 UNDEF_LSRPCBaseWb; 3378 UNDEF_LSRPCBaseWb;
3379 UNDEF_LSRPCOffWb; 3379 UNDEF_LSRPCOffWb;
3380 lhs = LHS; 3380 lhs = LHS;
3381 state->NtransSig = LOW; 3381 state->NtransSig = LOW;
3382 if (StoreWord (state, instr, lhs)) 3382 if (StoreWord (state, instr, lhs))
3383 LSBase = lhs - LSRegRHS; 3383 LSBase = lhs - LSRegRHS;
3384 state->NtransSig = 3384 state->NtransSig =
3385 (state->Mode & 3) ? HIGH : LOW; 3385 (state->Mode & 3) ? HIGH : LOW;
3386 break; 3386 break;
3387 3387
3388 case 0x63: /* Load Word, WriteBack, Post Dec, Reg. */ 3388 case 0x63: /* Load Word, WriteBack, Post Dec, Reg. */
3389 if (BIT (4)) { 3389 if (BIT (4)) {
3390#ifdef MODE32 3390#ifdef MODE32
3391 if (state->is_v6 3391 if (state->is_v6
3392 && handle_v6_insn (state, instr)) 3392 && handle_v6_insn (state, instr))
3393 break; 3393 break;
3394#endif 3394#endif
3395 3395
3396 ARMul_UndefInstr (state, instr); 3396 ARMul_UndefInstr (state, instr);
3397 break; 3397 break;
3398 } 3398 }
3399 UNDEF_LSRBaseEQOffWb; 3399 UNDEF_LSRBaseEQOffWb;
3400 UNDEF_LSRBaseEQDestWb; 3400 UNDEF_LSRBaseEQDestWb;
3401 UNDEF_LSRPCBaseWb; 3401 UNDEF_LSRPCBaseWb;
3402 UNDEF_LSRPCOffWb; 3402 UNDEF_LSRPCOffWb;
3403 lhs = LHS; 3403 lhs = LHS;
3404 temp = lhs - LSRegRHS; 3404 temp = lhs - LSRegRHS;
3405 state->NtransSig = LOW; 3405 state->NtransSig = LOW;
3406 if (LoadWord (state, instr, lhs)) 3406 if (LoadWord (state, instr, lhs))
3407 LSBase = temp; 3407 LSBase = temp;
3408 state->NtransSig = 3408 state->NtransSig =
3409 (state->Mode & 3) ? HIGH : LOW; 3409 (state->Mode & 3) ? HIGH : LOW;
3410 break; 3410 break;
3411 3411
3412 case 0x64: /* Store Byte, No WriteBack, Post Dec, Reg. */ 3412 case 0x64: /* Store Byte, No WriteBack, Post Dec, Reg. */
3413 if (BIT (4)) { 3413 if (BIT (4)) {
3414 ARMul_UndefInstr (state, instr); 3414 ARMul_UndefInstr (state, instr);
3415 break; 3415 break;
3416 } 3416 }
3417 UNDEF_LSRBaseEQOffWb; 3417 UNDEF_LSRBaseEQOffWb;
3418 UNDEF_LSRBaseEQDestWb; 3418 UNDEF_LSRBaseEQDestWb;
3419 UNDEF_LSRPCBaseWb; 3419 UNDEF_LSRPCBaseWb;
3420 UNDEF_LSRPCOffWb; 3420 UNDEF_LSRPCOffWb;
3421 lhs = LHS; 3421 lhs = LHS;
3422 if (StoreByte (state, instr, lhs)) 3422 if (StoreByte (state, instr, lhs))
3423 LSBase = lhs - LSRegRHS; 3423 LSBase = lhs - LSRegRHS;
3424 break; 3424 break;
3425 3425
3426 case 0x65: /* Load Byte, No WriteBack, Post Dec, Reg. */ 3426 case 0x65: /* Load Byte, No WriteBack, Post Dec, Reg. */
3427 if (BIT (4)) { 3427 if (BIT (4)) {
3428#ifdef MODE32 3428#ifdef MODE32
3429 if (state->is_v6 3429 if (state->is_v6
3430 && handle_v6_insn (state, instr)) 3430 && handle_v6_insn (state, instr))
3431 break; 3431 break;
3432#endif 3432#endif
3433 3433
3434 ARMul_UndefInstr (state, instr); 3434 ARMul_UndefInstr (state, instr);
3435 break; 3435 break;
3436 } 3436 }
3437 UNDEF_LSRBaseEQOffWb; 3437 UNDEF_LSRBaseEQOffWb;
3438 UNDEF_LSRBaseEQDestWb; 3438 UNDEF_LSRBaseEQDestWb;
3439 UNDEF_LSRPCBaseWb; 3439 UNDEF_LSRPCBaseWb;
3440 UNDEF_LSRPCOffWb; 3440 UNDEF_LSRPCOffWb;
3441 lhs = LHS; 3441 lhs = LHS;
3442 temp = lhs - LSRegRHS; 3442 temp = lhs - LSRegRHS;
3443 if (LoadByte (state, instr, lhs, LUNSIGNED)) 3443 if (LoadByte (state, instr, lhs, LUNSIGNED))
3444 LSBase = temp; 3444 LSBase = temp;
3445 break; 3445 break;
3446 3446
3447 case 0x66: /* Store Byte, WriteBack, Post Dec, Reg. */ 3447 case 0x66: /* Store Byte, WriteBack, Post Dec, Reg. */
3448 if (BIT (4)) { 3448 if (BIT (4)) {
3449#ifdef MODE32 3449#ifdef MODE32
3450 if (state->is_v6 3450 if (state->is_v6
3451 && handle_v6_insn (state, instr)) 3451 && handle_v6_insn (state, instr))
3452 break; 3452 break;
3453#endif 3453#endif
3454 3454
3455 ARMul_UndefInstr (state, instr); 3455 ARMul_UndefInstr (state, instr);
3456 break; 3456 break;
3457 } 3457 }
3458 UNDEF_LSRBaseEQOffWb; 3458 UNDEF_LSRBaseEQOffWb;
3459 UNDEF_LSRBaseEQDestWb; 3459 UNDEF_LSRBaseEQDestWb;
3460 UNDEF_LSRPCBaseWb; 3460 UNDEF_LSRPCBaseWb;
3461 UNDEF_LSRPCOffWb; 3461 UNDEF_LSRPCOffWb;
3462 lhs = LHS; 3462 lhs = LHS;
3463 state->NtransSig = LOW; 3463 state->NtransSig = LOW;
3464 if (StoreByte (state, instr, lhs)) 3464 if (StoreByte (state, instr, lhs))
3465 LSBase = lhs - LSRegRHS; 3465 LSBase = lhs - LSRegRHS;
3466 state->NtransSig = 3466 state->NtransSig =
3467 (state->Mode & 3) ? HIGH : LOW; 3467 (state->Mode & 3) ? HIGH : LOW;
3468 break; 3468 break;
3469 3469
3470 case 0x67: /* Load Byte, WriteBack, Post Dec, Reg. */ 3470 case 0x67: /* Load Byte, WriteBack, Post Dec, Reg. */
3471 if (BIT (4)) { 3471 if (BIT (4)) {
3472#ifdef MODE32 3472#ifdef MODE32
3473 if (state->is_v6 3473 if (state->is_v6
3474 && handle_v6_insn (state, instr)) 3474 && handle_v6_insn (state, instr))
3475 break; 3475 break;
3476#endif 3476#endif
3477 3477
3478 ARMul_UndefInstr (state, instr); 3478 ARMul_UndefInstr (state, instr);
3479 break; 3479 break;
3480 } 3480 }
3481 UNDEF_LSRBaseEQOffWb; 3481 UNDEF_LSRBaseEQOffWb;
3482 UNDEF_LSRBaseEQDestWb; 3482 UNDEF_LSRBaseEQDestWb;
3483 UNDEF_LSRPCBaseWb; 3483 UNDEF_LSRPCBaseWb;
3484 UNDEF_LSRPCOffWb; 3484 UNDEF_LSRPCOffWb;
3485 lhs = LHS; 3485 lhs = LHS;
3486 temp = lhs - LSRegRHS; 3486 temp = lhs - LSRegRHS;
3487 state->NtransSig = LOW; 3487 state->NtransSig = LOW;
3488 if (LoadByte (state, instr, lhs, LUNSIGNED)) 3488 if (LoadByte (state, instr, lhs, LUNSIGNED))
3489 LSBase = temp; 3489 LSBase = temp;
3490 state->NtransSig = 3490 state->NtransSig =
3491 (state->Mode & 3) ? HIGH : LOW; 3491 (state->Mode & 3) ? HIGH : LOW;
3492 break; 3492 break;
3493 3493
3494 case 0x68: /* Store Word, No WriteBack, Post Inc, Reg. */ 3494 case 0x68: /* Store Word, No WriteBack, Post Inc, Reg. */
3495 if (BIT (4)) { 3495 if (BIT (4)) {
3496#ifdef MODE32 3496#ifdef MODE32
3497 if (state->is_v6 3497 if (state->is_v6
3498 && handle_v6_insn (state, instr)) 3498 && handle_v6_insn (state, instr))
3499 break; 3499 break;
3500#endif 3500#endif
3501 3501
3502 ARMul_UndefInstr (state, instr); 3502 ARMul_UndefInstr (state, instr);
3503 break; 3503 break;
3504 } 3504 }
3505 UNDEF_LSRBaseEQOffWb; 3505 UNDEF_LSRBaseEQOffWb;
3506 UNDEF_LSRBaseEQDestWb; 3506 UNDEF_LSRBaseEQDestWb;
3507 UNDEF_LSRPCBaseWb; 3507 UNDEF_LSRPCBaseWb;
3508 UNDEF_LSRPCOffWb; 3508 UNDEF_LSRPCOffWb;
3509 lhs = LHS; 3509 lhs = LHS;
3510 if (StoreWord (state, instr, lhs)) 3510 if (StoreWord (state, instr, lhs))
3511 LSBase = lhs + LSRegRHS; 3511 LSBase = lhs + LSRegRHS;
3512 break; 3512 break;
3513 3513
3514 case 0x69: /* Load Word, No WriteBack, Post Inc, Reg. */ 3514 case 0x69: /* Load Word, No WriteBack, Post Inc, Reg. */
3515 if (BIT (4)) { 3515 if (BIT (4)) {
3516 ARMul_UndefInstr (state, instr); 3516 ARMul_UndefInstr (state, instr);
3517 break; 3517 break;
3518 } 3518 }
3519 UNDEF_LSRBaseEQOffWb; 3519 UNDEF_LSRBaseEQOffWb;
3520 UNDEF_LSRBaseEQDestWb; 3520 UNDEF_LSRBaseEQDestWb;
3521 UNDEF_LSRPCBaseWb; 3521 UNDEF_LSRPCBaseWb;
3522 UNDEF_LSRPCOffWb; 3522 UNDEF_LSRPCOffWb;
3523 lhs = LHS; 3523 lhs = LHS;
3524 temp = lhs + LSRegRHS; 3524 temp = lhs + LSRegRHS;
3525 if (LoadWord (state, instr, lhs)) 3525 if (LoadWord (state, instr, lhs))
3526 LSBase = temp; 3526 LSBase = temp;
3527 break; 3527 break;
3528 3528
3529 case 0x6a: /* Store Word, WriteBack, Post Inc, Reg. */ 3529 case 0x6a: /* Store Word, WriteBack, Post Inc, Reg. */
3530 if (BIT (4)) { 3530 if (BIT (4)) {
3531#ifdef MODE32 3531#ifdef MODE32
3532 if (state->is_v6 3532 if (state->is_v6
3533 && handle_v6_insn (state, instr)) 3533 && handle_v6_insn (state, instr))
3534 break; 3534 break;
3535#endif 3535#endif
3536 3536
3537 ARMul_UndefInstr (state, instr); 3537 ARMul_UndefInstr (state, instr);
3538 break; 3538 break;
3539 } 3539 }
3540 UNDEF_LSRBaseEQOffWb; 3540 UNDEF_LSRBaseEQOffWb;
3541 UNDEF_LSRBaseEQDestWb; 3541 UNDEF_LSRBaseEQDestWb;
3542 UNDEF_LSRPCBaseWb; 3542 UNDEF_LSRPCBaseWb;
3543 UNDEF_LSRPCOffWb; 3543 UNDEF_LSRPCOffWb;
3544 lhs = LHS; 3544 lhs = LHS;
3545 state->NtransSig = LOW; 3545 state->NtransSig = LOW;
3546 if (StoreWord (state, instr, lhs)) 3546 if (StoreWord (state, instr, lhs))
3547 LSBase = lhs + LSRegRHS; 3547 LSBase = lhs + LSRegRHS;
3548 state->NtransSig = 3548 state->NtransSig =
3549 (state->Mode & 3) ? HIGH : LOW; 3549 (state->Mode & 3) ? HIGH : LOW;
3550 break; 3550 break;
3551 3551
3552 case 0x6b: /* Load Word, WriteBack, Post Inc, Reg. */ 3552 case 0x6b: /* Load Word, WriteBack, Post Inc, Reg. */
3553 if (BIT (4)) { 3553 if (BIT (4)) {
3554#ifdef MODE32 3554#ifdef MODE32
3555 if (state->is_v6 3555 if (state->is_v6
3556 && handle_v6_insn (state, instr)) 3556 && handle_v6_insn (state, instr))
3557 break; 3557 break;
3558#endif 3558#endif
3559 3559
3560 ARMul_UndefInstr (state, instr); 3560 ARMul_UndefInstr (state, instr);
3561 break; 3561 break;
3562 } 3562 }
3563 UNDEF_LSRBaseEQOffWb; 3563 UNDEF_LSRBaseEQOffWb;
3564 UNDEF_LSRBaseEQDestWb; 3564 UNDEF_LSRBaseEQDestWb;
3565 UNDEF_LSRPCBaseWb; 3565 UNDEF_LSRPCBaseWb;
3566 UNDEF_LSRPCOffWb; 3566 UNDEF_LSRPCOffWb;
3567 lhs = LHS; 3567 lhs = LHS;
3568 temp = lhs + LSRegRHS; 3568 temp = lhs + LSRegRHS;
3569 state->NtransSig = LOW; 3569 state->NtransSig = LOW;
3570 if (LoadWord (state, instr, lhs)) 3570 if (LoadWord (state, instr, lhs))
3571 LSBase = temp; 3571 LSBase = temp;
3572 state->NtransSig = 3572 state->NtransSig =
3573 (state->Mode & 3) ? HIGH : LOW; 3573 (state->Mode & 3) ? HIGH : LOW;
3574 break; 3574 break;
3575 3575
3576 case 0x6c: /* Store Byte, No WriteBack, Post Inc, Reg. */ 3576 case 0x6c: /* Store Byte, No WriteBack, Post Inc, Reg. */
3577 if (BIT (4)) { 3577 if (BIT (4)) {
3578#ifdef MODE32 3578#ifdef MODE32
3579 if (state->is_v6 3579 if (state->is_v6
3580 && handle_v6_insn (state, instr)) 3580 && handle_v6_insn (state, instr))
3581 break; 3581 break;
3582#endif 3582#endif
3583 3583
3584 ARMul_UndefInstr (state, instr); 3584 ARMul_UndefInstr (state, instr);
3585 break; 3585 break;
3586 } 3586 }
3587 UNDEF_LSRBaseEQOffWb; 3587 UNDEF_LSRBaseEQOffWb;
3588 UNDEF_LSRBaseEQDestWb; 3588 UNDEF_LSRBaseEQDestWb;
3589 UNDEF_LSRPCBaseWb; 3589 UNDEF_LSRPCBaseWb;
3590 UNDEF_LSRPCOffWb; 3590 UNDEF_LSRPCOffWb;
3591 lhs = LHS; 3591 lhs = LHS;
3592 if (StoreByte (state, instr, lhs)) 3592 if (StoreByte (state, instr, lhs))
3593 LSBase = lhs + LSRegRHS; 3593 LSBase = lhs + LSRegRHS;
3594 break; 3594 break;
3595 3595
3596 case 0x6d: /* Load Byte, No WriteBack, Post Inc, Reg. */ 3596 case 0x6d: /* Load Byte, No WriteBack, Post Inc, Reg. */
3597 if (BIT (4)) { 3597 if (BIT (4)) {
3598 ARMul_UndefInstr (state, instr); 3598 ARMul_UndefInstr (state, instr);
3599 break; 3599 break;
3600 } 3600 }
3601 UNDEF_LSRBaseEQOffWb; 3601 UNDEF_LSRBaseEQOffWb;
3602 UNDEF_LSRBaseEQDestWb; 3602 UNDEF_LSRBaseEQDestWb;
3603 UNDEF_LSRPCBaseWb; 3603 UNDEF_LSRPCBaseWb;
3604 UNDEF_LSRPCOffWb; 3604 UNDEF_LSRPCOffWb;
3605 lhs = LHS; 3605 lhs = LHS;
3606 temp = lhs + LSRegRHS; 3606 temp = lhs + LSRegRHS;
3607 if (LoadByte (state, instr, lhs, LUNSIGNED)) 3607 if (LoadByte (state, instr, lhs, LUNSIGNED))
3608 LSBase = temp; 3608 LSBase = temp;
3609 break; 3609 break;
3610 3610
3611 case 0x6e: /* Store Byte, WriteBack, Post Inc, Reg. */ 3611 case 0x6e: /* Store Byte, WriteBack, Post Inc, Reg. */
3612#if 0 3612#if 0
3613 if (state->is_v6) { 3613 if (state->is_v6) {
3614 int Rm = 0; 3614 int Rm = 0;
3615 /* utxb */ 3615 /* utxb */
3616 if (BITS(15, 19) == 0xf && BITS(4, 7) == 0x7) { 3616 if (BITS(15, 19) == 0xf && BITS(4, 7) == 0x7) {
3617 3617
3618 Rm = (RHS >> (8 * BITS(10, 11))) & 0xff; 3618 Rm = (RHS >> (8 * BITS(10, 11))) & 0xff;
3619 DEST = Rm; 3619 DEST = Rm;
3620 } 3620 }
3621 3621
3622 } 3622 }
3623#endif 3623#endif
3624 if (BIT (4)) { 3624 if (BIT (4)) {
3625#ifdef MODE32 3625#ifdef MODE32
3626 if (state->is_v6 3626 if (state->is_v6
3627 && handle_v6_insn (state, instr)) 3627 && handle_v6_insn (state, instr))
3628 break; 3628 break;
3629#endif 3629#endif
3630 3630
3631 ARMul_UndefInstr (state, instr); 3631 ARMul_UndefInstr (state, instr);
3632 break; 3632 break;
3633 } 3633 }
3634 UNDEF_LSRBaseEQOffWb; 3634 UNDEF_LSRBaseEQOffWb;
3635 UNDEF_LSRBaseEQDestWb; 3635 UNDEF_LSRBaseEQDestWb;
3636 UNDEF_LSRPCBaseWb; 3636 UNDEF_LSRPCBaseWb;
3637 UNDEF_LSRPCOffWb; 3637 UNDEF_LSRPCOffWb;
3638 lhs = LHS; 3638 lhs = LHS;
3639 state->NtransSig = LOW; 3639 state->NtransSig = LOW;
3640 if (StoreByte (state, instr, lhs)) 3640 if (StoreByte (state, instr, lhs))
3641 LSBase = lhs + LSRegRHS; 3641 LSBase = lhs + LSRegRHS;
3642 state->NtransSig = 3642 state->NtransSig =
3643 (state->Mode & 3) ? HIGH : LOW; 3643 (state->Mode & 3) ? HIGH : LOW;
3644 break; 3644 break;
3645 3645
3646 case 0x6f: /* Load Byte, WriteBack, Post Inc, Reg. */ 3646 case 0x6f: /* Load Byte, WriteBack, Post Inc, Reg. */
3647 if (BIT (4)) { 3647 if (BIT (4)) {
3648#ifdef MODE32 3648#ifdef MODE32
3649 if (state->is_v6 3649 if (state->is_v6
3650 && handle_v6_insn (state, instr)) 3650 && handle_v6_insn (state, instr))
3651 break; 3651 break;
3652#endif 3652#endif
3653 3653
3654 ARMul_UndefInstr (state, instr); 3654 ARMul_UndefInstr (state, instr);
3655 break; 3655 break;
3656 } 3656 }
3657 UNDEF_LSRBaseEQOffWb; 3657 UNDEF_LSRBaseEQOffWb;
3658 UNDEF_LSRBaseEQDestWb; 3658 UNDEF_LSRBaseEQDestWb;
3659 UNDEF_LSRPCBaseWb; 3659 UNDEF_LSRPCBaseWb;
3660 UNDEF_LSRPCOffWb; 3660 UNDEF_LSRPCOffWb;
3661 lhs = LHS; 3661 lhs = LHS;
3662 temp = lhs + LSRegRHS; 3662 temp = lhs + LSRegRHS;
3663 state->NtransSig = LOW; 3663 state->NtransSig = LOW;
3664 if (LoadByte (state, instr, lhs, LUNSIGNED)) 3664 if (LoadByte (state, instr, lhs, LUNSIGNED))
3665 LSBase = temp; 3665 LSBase = temp;
3666 state->NtransSig = 3666 state->NtransSig =
3667 (state->Mode & 3) ? HIGH : LOW; 3667 (state->Mode & 3) ? HIGH : LOW;
3668 break; 3668 break;
3669 3669
3670 3670
3671 case 0x70: /* Store Word, No WriteBack, Pre Dec, Reg. */ 3671 case 0x70: /* Store Word, No WriteBack, Pre Dec, Reg. */
3672 if (BIT (4)) { 3672 if (BIT (4)) {
3673#ifdef MODE32 3673#ifdef MODE32
3674 if (state->is_v6 3674 if (state->is_v6
3675 && handle_v6_insn (state, instr)) 3675 && handle_v6_insn (state, instr))
3676 break; 3676 break;
3677#endif 3677#endif
3678 3678
3679 ARMul_UndefInstr (state, instr); 3679 ARMul_UndefInstr (state, instr);
3680 break; 3680 break;
3681 } 3681 }
3682 (void) StoreWord (state, instr, 3682 (void) StoreWord (state, instr,
3683 LHS - LSRegRHS); 3683 LHS - LSRegRHS);
3684 break; 3684 break;
3685 3685
3686 case 0x71: /* Load Word, No WriteBack, Pre Dec, Reg. */ 3686 case 0x71: /* Load Word, No WriteBack, Pre Dec, Reg. */
3687 if (BIT (4)) { 3687 if (BIT (4)) {
3688 ARMul_UndefInstr (state, instr); 3688 ARMul_UndefInstr (state, instr);
3689 break; 3689 break;
3690 } 3690 }
3691 (void) LoadWord (state, instr, 3691 (void) LoadWord (state, instr,
3692 LHS - LSRegRHS); 3692 LHS - LSRegRHS);
3693 break; 3693 break;
3694 3694
3695 case 0x72: /* Store Word, WriteBack, Pre Dec, Reg. */ 3695 case 0x72: /* Store Word, WriteBack, Pre Dec, Reg. */
3696 if (BIT (4)) { 3696 if (BIT (4)) {
3697 ARMul_UndefInstr (state, instr); 3697 ARMul_UndefInstr (state, instr);
3698 break; 3698 break;
3699 } 3699 }
3700 UNDEF_LSRBaseEQOffWb; 3700 UNDEF_LSRBaseEQOffWb;
3701 UNDEF_LSRBaseEQDestWb; 3701 UNDEF_LSRBaseEQDestWb;
3702 UNDEF_LSRPCBaseWb; 3702 UNDEF_LSRPCBaseWb;
3703 UNDEF_LSRPCOffWb; 3703 UNDEF_LSRPCOffWb;
3704 temp = LHS - LSRegRHS; 3704 temp = LHS - LSRegRHS;
3705 if (StoreWord (state, instr, temp)) 3705 if (StoreWord (state, instr, temp))
3706 LSBase = temp; 3706 LSBase = temp;
3707 break; 3707 break;
3708 3708
3709 case 0x73: /* Load Word, WriteBack, Pre Dec, Reg. */ 3709 case 0x73: /* Load Word, WriteBack, Pre Dec, Reg. */
3710 if (BIT (4)) { 3710 if (BIT (4)) {
3711 ARMul_UndefInstr (state, instr); 3711 ARMul_UndefInstr (state, instr);
3712 break; 3712 break;
3713 } 3713 }
3714 UNDEF_LSRBaseEQOffWb; 3714 UNDEF_LSRBaseEQOffWb;
3715 UNDEF_LSRBaseEQDestWb; 3715 UNDEF_LSRBaseEQDestWb;
3716 UNDEF_LSRPCBaseWb; 3716 UNDEF_LSRPCBaseWb;
3717 UNDEF_LSRPCOffWb; 3717 UNDEF_LSRPCOffWb;
3718 temp = LHS - LSRegRHS; 3718 temp = LHS - LSRegRHS;
3719 if (LoadWord (state, instr, temp)) 3719 if (LoadWord (state, instr, temp))
3720 LSBase = temp; 3720 LSBase = temp;
3721 break; 3721 break;
3722 3722
3723 case 0x74: /* Store Byte, No WriteBack, Pre Dec, Reg. */ 3723 case 0x74: /* Store Byte, No WriteBack, Pre Dec, Reg. */
3724 if (BIT (4)) { 3724 if (BIT (4)) {
3725#ifdef MODE32 3725#ifdef MODE32
3726 if (state->is_v6 3726 if (state->is_v6
3727 && handle_v6_insn (state, instr)) 3727 && handle_v6_insn (state, instr))
3728 break; 3728 break;
3729#endif 3729#endif
3730 3730
3731 ARMul_UndefInstr (state, instr); 3731 ARMul_UndefInstr (state, instr);
3732 break; 3732 break;
3733 } 3733 }
3734 (void) StoreByte (state, instr, 3734 (void) StoreByte (state, instr,
3735 LHS - LSRegRHS); 3735 LHS - LSRegRHS);
3736 break; 3736 break;
3737 3737
3738 case 0x75: /* Load Byte, No WriteBack, Pre Dec, Reg. */ 3738 case 0x75: /* Load Byte, No WriteBack, Pre Dec, Reg. */
3739 if (BIT (4)) { 3739 if (BIT (4)) {
3740#ifdef MODE32 3740#ifdef MODE32
3741 if (state->is_v6 3741 if (state->is_v6
3742 && handle_v6_insn (state, instr)) 3742 && handle_v6_insn (state, instr))
3743 break; 3743 break;
3744#endif 3744#endif
3745 3745
3746 ARMul_UndefInstr (state, instr); 3746 ARMul_UndefInstr (state, instr);
3747 break; 3747 break;
3748 } 3748 }
3749 (void) LoadByte (state, instr, LHS - LSRegRHS, 3749 (void) LoadByte (state, instr, LHS - LSRegRHS,
3750 LUNSIGNED); 3750 LUNSIGNED);
3751 break; 3751 break;
3752 3752
3753 case 0x76: /* Store Byte, WriteBack, Pre Dec, Reg. */ 3753 case 0x76: /* Store Byte, WriteBack, Pre Dec, Reg. */
3754 if (BIT (4)) { 3754 if (BIT (4)) {
3755 ARMul_UndefInstr (state, instr); 3755 ARMul_UndefInstr (state, instr);
3756 break; 3756 break;
3757 } 3757 }
3758 UNDEF_LSRBaseEQOffWb; 3758 UNDEF_LSRBaseEQOffWb;
3759 UNDEF_LSRBaseEQDestWb; 3759 UNDEF_LSRBaseEQDestWb;
3760 UNDEF_LSRPCBaseWb; 3760 UNDEF_LSRPCBaseWb;
3761 UNDEF_LSRPCOffWb; 3761 UNDEF_LSRPCOffWb;
3762 temp = LHS - LSRegRHS; 3762 temp = LHS - LSRegRHS;
3763 if (StoreByte (state, instr, temp)) 3763 if (StoreByte (state, instr, temp))
3764 LSBase = temp; 3764 LSBase = temp;
3765 break; 3765 break;
3766 3766
3767 case 0x77: /* Load Byte, WriteBack, Pre Dec, Reg. */ 3767 case 0x77: /* Load Byte, WriteBack, Pre Dec, Reg. */
3768 if (BIT (4)) { 3768 if (BIT (4)) {
3769 ARMul_UndefInstr (state, instr); 3769 ARMul_UndefInstr (state, instr);
3770 break; 3770 break;
3771 } 3771 }
3772 UNDEF_LSRBaseEQOffWb; 3772 UNDEF_LSRBaseEQOffWb;
3773 UNDEF_LSRBaseEQDestWb; 3773 UNDEF_LSRBaseEQDestWb;
3774 UNDEF_LSRPCBaseWb; 3774 UNDEF_LSRPCBaseWb;
3775 UNDEF_LSRPCOffWb; 3775 UNDEF_LSRPCOffWb;
3776 temp = LHS - LSRegRHS; 3776 temp = LHS - LSRegRHS;
3777 if (LoadByte (state, instr, temp, LUNSIGNED)) 3777 if (LoadByte (state, instr, temp, LUNSIGNED))
3778 LSBase = temp; 3778 LSBase = temp;
3779 break; 3779 break;
3780 3780
3781 case 0x78: /* Store Word, No WriteBack, Pre Inc, Reg. */ 3781 case 0x78: /* Store Word, No WriteBack, Pre Inc, Reg. */
3782 if (BIT (4)) { 3782 if (BIT (4)) {
3783#ifdef MODE32 3783#ifdef MODE32
3784 if (state->is_v6 3784 if (state->is_v6
3785 && handle_v6_insn (state, instr)) 3785 && handle_v6_insn (state, instr))
3786 break; 3786 break;
3787#endif 3787#endif
3788 3788
3789 ARMul_UndefInstr (state, instr); 3789 ARMul_UndefInstr (state, instr);
3790 break; 3790 break;
3791 } 3791 }
3792 (void) StoreWord (state, instr, 3792 (void) StoreWord (state, instr,
3793 LHS + LSRegRHS); 3793 LHS + LSRegRHS);
3794 break; 3794 break;
3795 3795
3796 case 0x79: /* Load Word, No WriteBack, Pre Inc, Reg. */ 3796 case 0x79: /* Load Word, No WriteBack, Pre Inc, Reg. */
3797 if (BIT (4)) { 3797 if (BIT (4)) {
3798 ARMul_UndefInstr (state, instr); 3798 ARMul_UndefInstr (state, instr);
3799 break; 3799 break;
3800 } 3800 }
3801 (void) LoadWord (state, instr, 3801 (void) LoadWord (state, instr,
3802 LHS + LSRegRHS); 3802 LHS + LSRegRHS);
3803 break; 3803 break;
3804 3804
3805 case 0x7a: /* Store Word, WriteBack, Pre Inc, Reg. */ 3805 case 0x7a: /* Store Word, WriteBack, Pre Inc, Reg. */
3806 if (BIT (4)) { 3806 if (BIT (4)) {
3807#ifdef MODE32 3807#ifdef MODE32
3808 if (state->is_v6 3808 if (state->is_v6
3809 && handle_v6_insn (state, instr)) 3809 && handle_v6_insn (state, instr))
3810 break; 3810 break;
3811#endif 3811#endif
3812 3812
3813 ARMul_UndefInstr (state, instr); 3813 ARMul_UndefInstr (state, instr);
3814 break; 3814 break;
3815 } 3815 }
3816 UNDEF_LSRBaseEQOffWb; 3816 UNDEF_LSRBaseEQOffWb;
3817 UNDEF_LSRBaseEQDestWb; 3817 UNDEF_LSRBaseEQDestWb;
3818 UNDEF_LSRPCBaseWb; 3818 UNDEF_LSRPCBaseWb;
3819 UNDEF_LSRPCOffWb; 3819 UNDEF_LSRPCOffWb;
3820 temp = LHS + LSRegRHS; 3820 temp = LHS + LSRegRHS;
3821 if (StoreWord (state, instr, temp)) 3821 if (StoreWord (state, instr, temp))
3822 LSBase = temp; 3822 LSBase = temp;
3823 break; 3823 break;
3824 3824
3825 case 0x7b: /* Load Word, WriteBack, Pre Inc, Reg. */ 3825 case 0x7b: /* Load Word, WriteBack, Pre Inc, Reg. */
3826 if (BIT (4)) { 3826 if (BIT (4)) {
3827 ARMul_UndefInstr (state, instr); 3827 ARMul_UndefInstr (state, instr);
3828 break; 3828 break;
3829 } 3829 }
3830 UNDEF_LSRBaseEQOffWb; 3830 UNDEF_LSRBaseEQOffWb;
3831 UNDEF_LSRBaseEQDestWb; 3831 UNDEF_LSRBaseEQDestWb;
3832 UNDEF_LSRPCBaseWb; 3832 UNDEF_LSRPCBaseWb;
3833 UNDEF_LSRPCOffWb; 3833 UNDEF_LSRPCOffWb;
3834 temp = LHS + LSRegRHS; 3834 temp = LHS + LSRegRHS;
3835 if (LoadWord (state, instr, temp)) 3835 if (LoadWord (state, instr, temp))
3836 LSBase = temp; 3836 LSBase = temp;
3837 break; 3837 break;
3838 3838
3839 case 0x7c: /* Store Byte, No WriteBack, Pre Inc, Reg. */ 3839 case 0x7c: /* Store Byte, No WriteBack, Pre Inc, Reg. */
3840 if (BIT (4)) { 3840 if (BIT (4)) {
3841#ifdef MODE32 3841#ifdef MODE32
3842 if (state->is_v6 3842 if (state->is_v6
3843 && handle_v6_insn (state, instr)) 3843 && handle_v6_insn (state, instr))
3844 break; 3844 break;
3845#endif 3845#endif
3846 3846
3847 ARMul_UndefInstr (state, instr); 3847 ARMul_UndefInstr (state, instr);
3848 break; 3848 break;
3849 } 3849 }
3850 (void) StoreByte (state, instr, 3850 (void) StoreByte (state, instr,
3851 LHS + LSRegRHS); 3851 LHS + LSRegRHS);
3852 break; 3852 break;
3853 3853
3854 case 0x7d: /* Load Byte, No WriteBack, Pre Inc, Reg. */ 3854 case 0x7d: /* Load Byte, No WriteBack, Pre Inc, Reg. */
3855 if (BIT (4)) { 3855 if (BIT (4)) {
3856 ARMul_UndefInstr (state, instr); 3856 ARMul_UndefInstr (state, instr);
3857 break; 3857 break;
3858 } 3858 }
3859 (void) LoadByte (state, instr, LHS + LSRegRHS, 3859 (void) LoadByte (state, instr, LHS + LSRegRHS,
3860 LUNSIGNED); 3860 LUNSIGNED);
3861 break; 3861 break;
3862 3862
3863 case 0x7e: /* Store Byte, WriteBack, Pre Inc, Reg. */ 3863 case 0x7e: /* Store Byte, WriteBack, Pre Inc, Reg. */
3864 if (BIT (4)) { 3864 if (BIT (4)) {
3865 ARMul_UndefInstr (state, instr); 3865 ARMul_UndefInstr (state, instr);
3866 break; 3866 break;
3867 } 3867 }
3868 UNDEF_LSRBaseEQOffWb; 3868 UNDEF_LSRBaseEQOffWb;
3869 UNDEF_LSRBaseEQDestWb; 3869 UNDEF_LSRBaseEQDestWb;
3870 UNDEF_LSRPCBaseWb; 3870 UNDEF_LSRPCBaseWb;
3871 UNDEF_LSRPCOffWb; 3871 UNDEF_LSRPCOffWb;
3872 temp = LHS + LSRegRHS; 3872 temp = LHS + LSRegRHS;
3873 if (StoreByte (state, instr, temp)) 3873 if (StoreByte (state, instr, temp))
3874 LSBase = temp; 3874 LSBase = temp;
3875 break; 3875 break;
3876 3876
3877 case 0x7f: /* Load Byte, WriteBack, Pre Inc, Reg. */ 3877 case 0x7f: /* Load Byte, WriteBack, Pre Inc, Reg. */
3878 if (BIT (4)) { 3878 if (BIT (4)) {
3879 /* Check for the special breakpoint opcode. 3879 /* Check for the special breakpoint opcode.
3880 This value should correspond to the value defined 3880 This value should correspond to the value defined
3881 as ARM_BE_BREAKPOINT in gdb/arm/tm-arm.h. */ 3881 as ARM_BE_BREAKPOINT in gdb/arm/tm-arm.h. */
3882 if (BITS (0, 19) == 0xfdefe) { 3882 if (BITS (0, 19) == 0xfdefe) {
3883 if (!ARMul_OSHandleSWI 3883 if (!ARMul_OSHandleSWI
3884 (state, SWI_Breakpoint)) 3884 (state, SWI_Breakpoint))
3885 ARMul_Abort (state, 3885 ARMul_Abort (state,
3886 ARMul_SWIV); 3886 ARMul_SWIV);
3887 } 3887 }
3888 else 3888 else
3889 ARMul_UndefInstr (state, 3889 ARMul_UndefInstr (state,
3890 instr); 3890 instr);
3891 break; 3891 break;
3892 } 3892 }
3893 UNDEF_LSRBaseEQOffWb; 3893 UNDEF_LSRBaseEQOffWb;
3894 UNDEF_LSRBaseEQDestWb; 3894 UNDEF_LSRBaseEQDestWb;
3895 UNDEF_LSRPCBaseWb; 3895 UNDEF_LSRPCBaseWb;
3896 UNDEF_LSRPCOffWb; 3896 UNDEF_LSRPCOffWb;
3897 temp = LHS + LSRegRHS; 3897 temp = LHS + LSRegRHS;
3898 if (LoadByte (state, instr, temp, LUNSIGNED)) 3898 if (LoadByte (state, instr, temp, LUNSIGNED))
3899 LSBase = temp; 3899 LSBase = temp;
3900 break; 3900 break;
3901 3901
3902 3902
3903 /* Multiple Data Transfer Instructions. */ 3903 /* Multiple Data Transfer Instructions. */
3904 3904
3905 case 0x80: /* Store, No WriteBack, Post Dec. */ 3905 case 0x80: /* Store, No WriteBack, Post Dec. */
3906 STOREMULT (instr, LSBase - LSMNumRegs + 4L, 3906 STOREMULT (instr, LSBase - LSMNumRegs + 4L,
3907 0L); 3907 0L);
3908 break; 3908 break;
3909 3909
3910 case 0x81: /* Load, No WriteBack, Post Dec. */ 3910 case 0x81: /* Load, No WriteBack, Post Dec. */
3911 LOADMULT (instr, LSBase - LSMNumRegs + 4L, 3911 LOADMULT (instr, LSBase - LSMNumRegs + 4L,
3912 0L); 3912 0L);
3913 break; 3913 break;
3914 3914
3915 case 0x82: /* Store, WriteBack, Post Dec. */ 3915 case 0x82: /* Store, WriteBack, Post Dec. */
3916 temp = LSBase - LSMNumRegs; 3916 temp = LSBase - LSMNumRegs;
3917 STOREMULT (instr, temp + 4L, temp); 3917 STOREMULT (instr, temp + 4L, temp);
3918 break; 3918 break;
3919 3919
3920 case 0x83: /* Load, WriteBack, Post Dec. */ 3920 case 0x83: /* Load, WriteBack, Post Dec. */
3921 temp = LSBase - LSMNumRegs; 3921 temp = LSBase - LSMNumRegs;
3922 LOADMULT (instr, temp + 4L, temp); 3922 LOADMULT (instr, temp + 4L, temp);
3923 break; 3923 break;
3924 3924
3925 case 0x84: /* Store, Flags, No WriteBack, Post Dec. */ 3925 case 0x84: /* Store, Flags, No WriteBack, Post Dec. */
3926 STORESMULT (instr, LSBase - LSMNumRegs + 4L, 3926 STORESMULT (instr, LSBase - LSMNumRegs + 4L,
3927 0L); 3927 0L);
3928 break; 3928 break;
3929 3929
3930 case 0x85: /* Load, Flags, No WriteBack, Post Dec. */ 3930 case 0x85: /* Load, Flags, No WriteBack, Post Dec. */
3931 LOADSMULT (instr, LSBase - LSMNumRegs + 4L, 3931 LOADSMULT (instr, LSBase - LSMNumRegs + 4L,
3932 0L); 3932 0L);
3933 break; 3933 break;
3934 3934
3935 case 0x86: /* Store, Flags, WriteBack, Post Dec. */ 3935 case 0x86: /* Store, Flags, WriteBack, Post Dec. */
3936 temp = LSBase - LSMNumRegs; 3936 temp = LSBase - LSMNumRegs;
3937 STORESMULT (instr, temp + 4L, temp); 3937 STORESMULT (instr, temp + 4L, temp);
3938 break; 3938 break;
3939 3939
3940 case 0x87: /* Load, Flags, WriteBack, Post Dec. */ 3940 case 0x87: /* Load, Flags, WriteBack, Post Dec. */
3941 temp = LSBase - LSMNumRegs; 3941 temp = LSBase - LSMNumRegs;
3942 LOADSMULT (instr, temp + 4L, temp); 3942 LOADSMULT (instr, temp + 4L, temp);
3943 break; 3943 break;
3944 3944
3945 case 0x88: /* Store, No WriteBack, Post Inc. */ 3945 case 0x88: /* Store, No WriteBack, Post Inc. */
3946 STOREMULT (instr, LSBase, 0L); 3946 STOREMULT (instr, LSBase, 0L);
3947 break; 3947 break;
3948 3948
3949 case 0x89: /* Load, No WriteBack, Post Inc. */ 3949 case 0x89: /* Load, No WriteBack, Post Inc. */
3950 LOADMULT (instr, LSBase, 0L); 3950 LOADMULT (instr, LSBase, 0L);
3951 break; 3951 break;
3952 3952
3953 case 0x8a: /* Store, WriteBack, Post Inc. */ 3953 case 0x8a: /* Store, WriteBack, Post Inc. */
3954 temp = LSBase; 3954 temp = LSBase;
3955 STOREMULT (instr, temp, temp + LSMNumRegs); 3955 STOREMULT (instr, temp, temp + LSMNumRegs);
3956 break; 3956 break;
3957 3957
3958 case 0x8b: /* Load, WriteBack, Post Inc. */ 3958 case 0x8b: /* Load, WriteBack, Post Inc. */
3959 temp = LSBase; 3959 temp = LSBase;
3960 LOADMULT (instr, temp, temp + LSMNumRegs); 3960 LOADMULT (instr, temp, temp + LSMNumRegs);
3961 break; 3961 break;
3962 3962
3963 case 0x8c: /* Store, Flags, No WriteBack, Post Inc. */ 3963 case 0x8c: /* Store, Flags, No WriteBack, Post Inc. */
3964 STORESMULT (instr, LSBase, 0L); 3964 STORESMULT (instr, LSBase, 0L);
3965 break; 3965 break;
3966 3966
3967 case 0x8d: /* Load, Flags, No WriteBack, Post Inc. */ 3967 case 0x8d: /* Load, Flags, No WriteBack, Post Inc. */
3968 LOADSMULT (instr, LSBase, 0L); 3968 LOADSMULT (instr, LSBase, 0L);
3969 break; 3969 break;
3970 3970
3971 case 0x8e: /* Store, Flags, WriteBack, Post Inc. */ 3971 case 0x8e: /* Store, Flags, WriteBack, Post Inc. */
3972 temp = LSBase; 3972 temp = LSBase;
3973 STORESMULT (instr, temp, temp + LSMNumRegs); 3973 STORESMULT (instr, temp, temp + LSMNumRegs);
3974 break; 3974 break;
3975 3975
3976 case 0x8f: /* Load, Flags, WriteBack, Post Inc. */ 3976 case 0x8f: /* Load, Flags, WriteBack, Post Inc. */
3977 temp = LSBase; 3977 temp = LSBase;
3978 LOADSMULT (instr, temp, temp + LSMNumRegs); 3978 LOADSMULT (instr, temp, temp + LSMNumRegs);
3979 break; 3979 break;
3980 3980
3981 case 0x90: /* Store, No WriteBack, Pre Dec. */ 3981 case 0x90: /* Store, No WriteBack, Pre Dec. */
3982 STOREMULT (instr, LSBase - LSMNumRegs, 0L); 3982 STOREMULT (instr, LSBase - LSMNumRegs, 0L);
3983 break; 3983 break;
3984 3984
3985 case 0x91: /* Load, No WriteBack, Pre Dec. */ 3985 case 0x91: /* Load, No WriteBack, Pre Dec. */
3986 LOADMULT (instr, LSBase - LSMNumRegs, 0L); 3986 LOADMULT (instr, LSBase - LSMNumRegs, 0L);
3987 break; 3987 break;
3988 3988
3989 case 0x92: /* Store, WriteBack, Pre Dec. */ 3989 case 0x92: /* Store, WriteBack, Pre Dec. */
3990 temp = LSBase - LSMNumRegs; 3990 temp = LSBase - LSMNumRegs;
3991 STOREMULT (instr, temp, temp); 3991 STOREMULT (instr, temp, temp);
3992 break; 3992 break;
3993 3993
3994 case 0x93: /* Load, WriteBack, Pre Dec. */ 3994 case 0x93: /* Load, WriteBack, Pre Dec. */
3995 temp = LSBase - LSMNumRegs; 3995 temp = LSBase - LSMNumRegs;
3996 LOADMULT (instr, temp, temp); 3996 LOADMULT (instr, temp, temp);
3997 break; 3997 break;
3998 3998
3999 case 0x94: /* Store, Flags, No WriteBack, Pre Dec. */ 3999 case 0x94: /* Store, Flags, No WriteBack, Pre Dec. */
4000 STORESMULT (instr, LSBase - LSMNumRegs, 0L); 4000 STORESMULT (instr, LSBase - LSMNumRegs, 0L);
4001 break; 4001 break;
4002 4002
4003 case 0x95: /* Load, Flags, No WriteBack, Pre Dec. */ 4003 case 0x95: /* Load, Flags, No WriteBack, Pre Dec. */
4004 LOADSMULT (instr, LSBase - LSMNumRegs, 0L); 4004 LOADSMULT (instr, LSBase - LSMNumRegs, 0L);
4005 break; 4005 break;
4006 4006
4007 case 0x96: /* Store, Flags, WriteBack, Pre Dec. */ 4007 case 0x96: /* Store, Flags, WriteBack, Pre Dec. */
4008 temp = LSBase - LSMNumRegs; 4008 temp = LSBase - LSMNumRegs;
4009 STORESMULT (instr, temp, temp); 4009 STORESMULT (instr, temp, temp);
4010 break; 4010 break;
4011 4011
4012 case 0x97: /* Load, Flags, WriteBack, Pre Dec. */ 4012 case 0x97: /* Load, Flags, WriteBack, Pre Dec. */
4013 temp = LSBase - LSMNumRegs; 4013 temp = LSBase - LSMNumRegs;
4014 LOADSMULT (instr, temp, temp); 4014 LOADSMULT (instr, temp, temp);
4015 break; 4015 break;
4016 4016
4017 case 0x98: /* Store, No WriteBack, Pre Inc. */ 4017 case 0x98: /* Store, No WriteBack, Pre Inc. */
4018 STOREMULT (instr, LSBase + 4L, 0L); 4018 STOREMULT (instr, LSBase + 4L, 0L);
4019 break; 4019 break;
4020 4020
4021 case 0x99: /* Load, No WriteBack, Pre Inc. */ 4021 case 0x99: /* Load, No WriteBack, Pre Inc. */
4022 LOADMULT (instr, LSBase + 4L, 0L); 4022 LOADMULT (instr, LSBase + 4L, 0L);
4023 break; 4023 break;
4024 4024
4025 case 0x9a: /* Store, WriteBack, Pre Inc. */ 4025 case 0x9a: /* Store, WriteBack, Pre Inc. */
4026 temp = LSBase; 4026 temp = LSBase;
4027 STOREMULT (instr, temp + 4L, 4027 STOREMULT (instr, temp + 4L,
4028 temp + LSMNumRegs); 4028 temp + LSMNumRegs);
4029 break; 4029 break;
4030 4030
4031 case 0x9b: /* Load, WriteBack, Pre Inc. */ 4031 case 0x9b: /* Load, WriteBack, Pre Inc. */
4032 temp = LSBase; 4032 temp = LSBase;
4033 LOADMULT (instr, temp + 4L, 4033 LOADMULT (instr, temp + 4L,
4034 temp + LSMNumRegs); 4034 temp + LSMNumRegs);
4035 break; 4035 break;
4036 4036
4037 case 0x9c: /* Store, Flags, No WriteBack, Pre Inc. */ 4037 case 0x9c: /* Store, Flags, No WriteBack, Pre Inc. */
4038 STORESMULT (instr, LSBase + 4L, 0L); 4038 STORESMULT (instr, LSBase + 4L, 0L);
4039 break; 4039 break;
4040 4040
4041 case 0x9d: /* Load, Flags, No WriteBack, Pre Inc. */ 4041 case 0x9d: /* Load, Flags, No WriteBack, Pre Inc. */
4042 LOADSMULT (instr, LSBase + 4L, 0L); 4042 LOADSMULT (instr, LSBase + 4L, 0L);
4043 break; 4043 break;
4044 4044
4045 case 0x9e: /* Store, Flags, WriteBack, Pre Inc. */ 4045 case 0x9e: /* Store, Flags, WriteBack, Pre Inc. */
4046 temp = LSBase; 4046 temp = LSBase;
4047 STORESMULT (instr, temp + 4L, 4047 STORESMULT (instr, temp + 4L,
4048 temp + LSMNumRegs); 4048 temp + LSMNumRegs);
4049 break; 4049 break;
4050 4050
4051 case 0x9f: /* Load, Flags, WriteBack, Pre Inc. */ 4051 case 0x9f: /* Load, Flags, WriteBack, Pre Inc. */
4052 temp = LSBase; 4052 temp = LSBase;
4053 LOADSMULT (instr, temp + 4L, 4053 LOADSMULT (instr, temp + 4L,
4054 temp + LSMNumRegs); 4054 temp + LSMNumRegs);
4055 break; 4055 break;
4056 4056
4057 4057
4058 /* Branch forward. */ 4058 /* Branch forward. */
4059 case 0xa0: 4059 case 0xa0:
4060 case 0xa1: 4060 case 0xa1:
4061 case 0xa2: 4061 case 0xa2:
4062 case 0xa3: 4062 case 0xa3:
4063 case 0xa4: 4063 case 0xa4:
4064 case 0xa5: 4064 case 0xa5:
4065 case 0xa6: 4065 case 0xa6:
4066 case 0xa7: 4066 case 0xa7:
4067 state->Reg[15] = pc + 8 + POSBRANCH; 4067 state->Reg[15] = pc + 8 + POSBRANCH;
4068 FLUSHPIPE; 4068 FLUSHPIPE;
4069 break; 4069 break;
4070 4070
4071 4071
4072 /* Branch backward. */ 4072 /* Branch backward. */
4073 case 0xa8: 4073 case 0xa8:
4074 case 0xa9: 4074 case 0xa9:
4075 case 0xaa: 4075 case 0xaa:
4076 case 0xab: 4076 case 0xab:
4077 case 0xac: 4077 case 0xac:
4078 case 0xad: 4078 case 0xad:
4079 case 0xae: 4079 case 0xae:
4080 case 0xaf: 4080 case 0xaf:
4081 state->Reg[15] = pc + 8 + NEGBRANCH; 4081 state->Reg[15] = pc + 8 + NEGBRANCH;
4082 FLUSHPIPE; 4082 FLUSHPIPE;
4083 break; 4083 break;
4084 4084
4085 4085
4086 /* Branch and Link forward. */ 4086 /* Branch and Link forward. */
4087 case 0xb0: 4087 case 0xb0:
4088 case 0xb1: 4088 case 0xb1:
4089 case 0xb2: 4089 case 0xb2:
4090 case 0xb3: 4090 case 0xb3:
4091 case 0xb4: 4091 case 0xb4:
4092 case 0xb5: 4092 case 0xb5:
4093 case 0xb6: 4093 case 0xb6:
4094 case 0xb7: 4094 case 0xb7:
4095 /* Put PC into Link. */ 4095 /* Put PC into Link. */
4096#ifdef MODE32 4096#ifdef MODE32
4097 state->Reg[14] = pc + 4; 4097 state->Reg[14] = pc + 4;
4098#else 4098#else
4099 state->Reg[14] = 4099 state->Reg[14] =
4100 (pc + 4) | ECC | ER15INT | EMODE; 4100 (pc + 4) | ECC | ER15INT | EMODE;
4101#endif 4101#endif
4102 state->Reg[15] = pc + 8 + POSBRANCH; 4102 state->Reg[15] = pc + 8 + POSBRANCH;
4103 FLUSHPIPE; 4103 FLUSHPIPE;
4104 break; 4104 break;
4105 4105
4106 4106
4107 /* Branch and Link backward. */ 4107 /* Branch and Link backward. */
4108 case 0xb8: 4108 case 0xb8:
4109 case 0xb9: 4109 case 0xb9:
4110 case 0xba: 4110 case 0xba:
4111 case 0xbb: 4111 case 0xbb:
4112 case 0xbc: 4112 case 0xbc:
4113 case 0xbd: 4113 case 0xbd:
4114 case 0xbe: 4114 case 0xbe:
4115 case 0xbf: 4115 case 0xbf:
4116 /* Put PC into Link. */ 4116 /* Put PC into Link. */
4117#ifdef MODE32 4117#ifdef MODE32
4118 state->Reg[14] = pc + 4; 4118 state->Reg[14] = pc + 4;
4119#else 4119#else
4120 state->Reg[14] = 4120 state->Reg[14] =
4121 (pc + 4) | ECC | ER15INT | EMODE; 4121 (pc + 4) | ECC | ER15INT | EMODE;
4122#endif 4122#endif
4123 state->Reg[15] = pc + 8 + NEGBRANCH; 4123 state->Reg[15] = pc + 8 + NEGBRANCH;
4124 FLUSHPIPE; 4124 FLUSHPIPE;
4125 break; 4125 break;
4126 4126
4127 4127
4128 /* Co-Processor Data Transfers. */ 4128 /* Co-Processor Data Transfers. */
4129 case 0xc4: 4129 case 0xc4:
4130 if (state->is_v5) { 4130 if (state->is_v5) {
4131 /* Reading from R15 is UNPREDICTABLE. */ 4131 /* Reading from R15 is UNPREDICTABLE. */
4132 if (BITS (12, 15) == 15 4132 if (BITS (12, 15) == 15
4133 || BITS (16, 19) == 15) 4133 || BITS (16, 19) == 15)
4134 ARMul_UndefInstr (state, 4134 ARMul_UndefInstr (state,
4135 instr); 4135 instr);
4136 /* Is access to coprocessor 0 allowed ? */ 4136 /* Is access to coprocessor 0 allowed ? */
4137 else if (!CP_ACCESS_ALLOWED 4137 else if (!CP_ACCESS_ALLOWED
4138 (state, CPNum)) 4138 (state, CPNum))
4139 ARMul_UndefInstr (state, 4139 ARMul_UndefInstr (state,
4140 instr); 4140 instr);
4141 /* Special treatment for XScale coprocessors. */ 4141 /* Special treatment for XScale coprocessors. */
4142 else if (state->is_XScale) { 4142 else if (state->is_XScale) {
4143 /* Only opcode 0 is supported. */ 4143 /* Only opcode 0 is supported. */
4144 if (BITS (4, 7) != 0x00) 4144 if (BITS (4, 7) != 0x00)
4145 ARMul_UndefInstr 4145 ARMul_UndefInstr
4146 (state, 4146 (state,
4147 instr); 4147 instr);
4148 /* Only coporcessor 0 is supported. */ 4148 /* Only coporcessor 0 is supported. */
4149 else if (CPNum != 0x00) 4149 else if (CPNum != 0x00)
4150 ARMul_UndefInstr 4150 ARMul_UndefInstr
4151 (state, 4151 (state,
4152 instr); 4152 instr);
4153 /* Only accumulator 0 is supported. */ 4153 /* Only accumulator 0 is supported. */
4154 else if (BITS (0, 3) != 0x00) 4154 else if (BITS (0, 3) != 0x00)
4155 ARMul_UndefInstr 4155 ARMul_UndefInstr
4156 (state, 4156 (state,
4157 instr); 4157 instr);
4158 else { 4158 else {
4159 /* XScale MAR insn. Move two registers into accumulator. */ 4159 /* XScale MAR insn. Move two registers into accumulator. */
4160 state->Accumulator = 4160 state->Accumulator =
4161 state-> 4161 state->
4162 Reg[BITS 4162 Reg[BITS
4163 (12, 15)]; 4163 (12, 15)];
4164 state->Accumulator += 4164 state->Accumulator +=
4165 (ARMdword) 4165 (ARMdword)
4166 state-> 4166 state->
4167 Reg[BITS 4167 Reg[BITS
4168 (16, 4168 (16,
4169 19)] << 4169 19)] <<
4170 32; 4170 32;
4171 } 4171 }
4172 } 4172 }
4173 else 4173 else
4174 { 4174 {
4175 /* MCRR, ARMv5TE and up */ 4175 /* MCRR, ARMv5TE and up */
4176 ARMul_MCRR (state, instr, DEST, state->Reg[LHSReg]); 4176 ARMul_MCRR (state, instr, DEST, state->Reg[LHSReg]);
4177 break; 4177 break;
4178 } 4178 }
4179 } 4179 }
4180 /* Drop through. */ 4180 /* Drop through. */
4181 4181
4182 case 0xc0: /* Store , No WriteBack , Post Dec. */ 4182 case 0xc0: /* Store , No WriteBack , Post Dec. */
4183 ARMul_STC (state, instr, LHS); 4183 ARMul_STC (state, instr, LHS);
4184 break; 4184 break;
4185 4185
4186 case 0xc5: 4186 case 0xc5:
4187 if (state->is_v5) { 4187 if (state->is_v5) {
4188 /* Writes to R15 are UNPREDICATABLE. */ 4188 /* Writes to R15 are UNPREDICATABLE. */
4189 if (DESTReg == 15 || LHSReg == 15) 4189 if (DESTReg == 15 || LHSReg == 15)
4190 ARMul_UndefInstr (state, 4190 ARMul_UndefInstr (state,
4191 instr); 4191 instr);
4192 /* Is access to the coprocessor allowed ? */ 4192 /* Is access to the coprocessor allowed ? */
4193 else if (!CP_ACCESS_ALLOWED 4193 else if (!CP_ACCESS_ALLOWED
4194 (state, CPNum)) 4194 (state, CPNum))
4195 ARMul_UndefInstr (state, 4195 ARMul_UndefInstr (state,
4196 instr); 4196 instr);
4197 /* Special handling for XScale coprcoessors. */ 4197 /* Special handling for XScale coprcoessors. */
4198 else if (state->is_XScale) { 4198 else if (state->is_XScale) {
4199 /* Only opcode 0 is supported. */ 4199 /* Only opcode 0 is supported. */
4200 if (BITS (4, 7) != 0x00) 4200 if (BITS (4, 7) != 0x00)
4201 ARMul_UndefInstr 4201 ARMul_UndefInstr
4202 (state, 4202 (state,
4203 instr); 4203 instr);
4204 /* Only coprocessor 0 is supported. */ 4204 /* Only coprocessor 0 is supported. */
4205 else if (CPNum != 0x00) 4205 else if (CPNum != 0x00)
4206 ARMul_UndefInstr 4206 ARMul_UndefInstr
4207 (state, 4207 (state,
4208 instr); 4208 instr);
4209 /* Only accumulator 0 is supported. */ 4209 /* Only accumulator 0 is supported. */
4210 else if (BITS (0, 3) != 0x00) 4210 else if (BITS (0, 3) != 0x00)
4211 ARMul_UndefInstr 4211 ARMul_UndefInstr
4212 (state, 4212 (state,
4213 instr); 4213 instr);
4214 else { 4214 else {
4215 /* XScale MRA insn. Move accumulator into two registers. */ 4215 /* XScale MRA insn. Move accumulator into two registers. */
4216 ARMword t1 = 4216 ARMword t1 =
4217 (state-> 4217 (state->
4218 Accumulator 4218 Accumulator
4219 >> 32) & 255; 4219 >> 32) & 255;
4220 4220
4221 if (t1 & 128) 4221 if (t1 & 128)
4222 t1 -= 256; 4222 t1 -= 256;
4223 4223
4224 state->Reg[BITS 4224 state->Reg[BITS
4225 (12, 15)] = 4225 (12, 15)] =
4226 state-> 4226 state->
4227 Accumulator; 4227 Accumulator;
4228 state->Reg[BITS 4228 state->Reg[BITS
4229 (16, 19)] = 4229 (16, 19)] =
4230 t1; 4230 t1;
4231 break; 4231 break;
4232 } 4232 }
4233 } 4233 }
4234 else 4234 else
4235 { 4235 {
4236 /* MRRC, ARMv5TE and up */ 4236 /* MRRC, ARMv5TE and up */
4237 ARMul_MRRC (state, instr, &DEST, &(state->Reg[LHSReg])); 4237 ARMul_MRRC (state, instr, &DEST, &(state->Reg[LHSReg]));
4238 break; 4238 break;
4239 } 4239 }
4240 } 4240 }
4241 /* Drop through. */ 4241 /* Drop through. */
4242 4242
4243 case 0xc1: /* Load , No WriteBack , Post Dec. */ 4243 case 0xc1: /* Load , No WriteBack , Post Dec. */
4244 ARMul_LDC (state, instr, LHS); 4244 ARMul_LDC (state, instr, LHS);
4245 break; 4245 break;
4246 4246
4247 case 0xc2: 4247 case 0xc2:
4248 case 0xc6: /* Store , WriteBack , Post Dec. */ 4248 case 0xc6: /* Store , WriteBack , Post Dec. */
4249 lhs = LHS; 4249 lhs = LHS;
4250 state->Base = lhs - LSCOff; 4250 state->Base = lhs - LSCOff;
4251 ARMul_STC (state, instr, lhs); 4251 ARMul_STC (state, instr, lhs);
4252 break; 4252 break;
4253 4253
4254 case 0xc3: 4254 case 0xc3:
4255 case 0xc7: /* Load , WriteBack , Post Dec. */ 4255 case 0xc7: /* Load , WriteBack , Post Dec. */
4256 lhs = LHS; 4256 lhs = LHS;
4257 state->Base = lhs - LSCOff; 4257 state->Base = lhs - LSCOff;
4258 ARMul_LDC (state, instr, lhs); 4258 ARMul_LDC (state, instr, lhs);
4259 break; 4259 break;
4260 4260
4261 case 0xc8: 4261 case 0xc8:
4262 case 0xcc: /* Store , No WriteBack , Post Inc. */ 4262 case 0xcc: /* Store , No WriteBack , Post Inc. */
4263 ARMul_STC (state, instr, LHS); 4263 ARMul_STC (state, instr, LHS);
4264 break; 4264 break;
4265 4265
4266 case 0xc9: 4266 case 0xc9:
4267 case 0xcd: /* Load , No WriteBack , Post Inc. */ 4267 case 0xcd: /* Load , No WriteBack , Post Inc. */
4268 ARMul_LDC (state, instr, LHS); 4268 ARMul_LDC (state, instr, LHS);
4269 break; 4269 break;
4270 4270
4271 case 0xca: 4271 case 0xca:
4272 case 0xce: /* Store , WriteBack , Post Inc. */ 4272 case 0xce: /* Store , WriteBack , Post Inc. */
4273 lhs = LHS; 4273 lhs = LHS;
4274 state->Base = lhs + LSCOff; 4274 state->Base = lhs + LSCOff;
4275 ARMul_STC (state, instr, LHS); 4275 ARMul_STC (state, instr, LHS);
4276 break; 4276 break;
4277 4277
4278 case 0xcb: 4278 case 0xcb:
4279 case 0xcf: /* Load , WriteBack , Post Inc. */ 4279 case 0xcf: /* Load , WriteBack , Post Inc. */
4280 lhs = LHS; 4280 lhs = LHS;
4281 state->Base = lhs + LSCOff; 4281 state->Base = lhs + LSCOff;
4282 ARMul_LDC (state, instr, LHS); 4282 ARMul_LDC (state, instr, LHS);
4283 break; 4283 break;
4284 4284
4285 case 0xd0: 4285 case 0xd0:
4286 case 0xd4: /* Store , No WriteBack , Pre Dec. */ 4286 case 0xd4: /* Store , No WriteBack , Pre Dec. */
4287 ARMul_STC (state, instr, LHS - LSCOff); 4287 ARMul_STC (state, instr, LHS - LSCOff);
4288 break; 4288 break;
4289 4289
4290 case 0xd1: 4290 case 0xd1:
4291 case 0xd5: /* Load , No WriteBack , Pre Dec. */ 4291 case 0xd5: /* Load , No WriteBack , Pre Dec. */
4292 ARMul_LDC (state, instr, LHS - LSCOff); 4292 ARMul_LDC (state, instr, LHS - LSCOff);
4293 break; 4293 break;
4294 4294
4295 case 0xd2: 4295 case 0xd2:
4296 case 0xd6: /* Store , WriteBack , Pre Dec. */ 4296 case 0xd6: /* Store , WriteBack , Pre Dec. */
4297 lhs = LHS - LSCOff; 4297 lhs = LHS - LSCOff;
4298 state->Base = lhs; 4298 state->Base = lhs;
4299 ARMul_STC (state, instr, lhs); 4299 ARMul_STC (state, instr, lhs);
4300 break; 4300 break;
4301 4301
4302 case 0xd3: 4302 case 0xd3:
4303 case 0xd7: /* Load , WriteBack , Pre Dec. */ 4303 case 0xd7: /* Load , WriteBack , Pre Dec. */
4304 lhs = LHS - LSCOff; 4304 lhs = LHS - LSCOff;
4305 state->Base = lhs; 4305 state->Base = lhs;
4306 ARMul_LDC (state, instr, lhs); 4306 ARMul_LDC (state, instr, lhs);
4307 break; 4307 break;
4308 4308
4309 case 0xd8: 4309 case 0xd8:
4310 case 0xdc: /* Store , No WriteBack , Pre Inc. */ 4310 case 0xdc: /* Store , No WriteBack , Pre Inc. */
4311 ARMul_STC (state, instr, LHS + LSCOff); 4311 ARMul_STC (state, instr, LHS + LSCOff);
4312 break; 4312 break;
4313 4313
4314 case 0xd9: 4314 case 0xd9:
4315 case 0xdd: /* Load , No WriteBack , Pre Inc. */ 4315 case 0xdd: /* Load , No WriteBack , Pre Inc. */
4316 ARMul_LDC (state, instr, LHS + LSCOff); 4316 ARMul_LDC (state, instr, LHS + LSCOff);
4317 break; 4317 break;
4318 4318
4319 case 0xda: 4319 case 0xda:
4320 case 0xde: /* Store , WriteBack , Pre Inc. */ 4320 case 0xde: /* Store , WriteBack , Pre Inc. */
4321 lhs = LHS + LSCOff; 4321 lhs = LHS + LSCOff;
4322 state->Base = lhs; 4322 state->Base = lhs;
4323 ARMul_STC (state, instr, lhs); 4323 ARMul_STC (state, instr, lhs);
4324 break; 4324 break;
4325 4325
4326 case 0xdb: 4326 case 0xdb:
4327 case 0xdf: /* Load , WriteBack , Pre Inc. */ 4327 case 0xdf: /* Load , WriteBack , Pre Inc. */
4328 lhs = LHS + LSCOff; 4328 lhs = LHS + LSCOff;
4329 state->Base = lhs; 4329 state->Base = lhs;
4330 ARMul_LDC (state, instr, lhs); 4330 ARMul_LDC (state, instr, lhs);
4331 break; 4331 break;
4332 4332
4333 4333
4334 /* Co-Processor Register Transfers (MCR) and Data Ops. */ 4334 /* Co-Processor Register Transfers (MCR) and Data Ops. */
4335 4335
4336 case 0xe2: 4336 case 0xe2:
4337 if (!CP_ACCESS_ALLOWED (state, CPNum)) { 4337 if (!CP_ACCESS_ALLOWED (state, CPNum)) {
4338 ARMul_UndefInstr (state, instr); 4338 ARMul_UndefInstr (state, instr);
4339 break; 4339 break;
4340 } 4340 }
4341 if (state->is_XScale) 4341 if (state->is_XScale)
4342 switch (BITS (18, 19)) { 4342 switch (BITS (18, 19)) {
4343 case 0x0: 4343 case 0x0:
4344 if (BITS (4, 11) == 1 4344 if (BITS (4, 11) == 1
4345 && BITS (16, 17) == 0) { 4345 && BITS (16, 17) == 0) {
4346 /* XScale MIA instruction. Signed multiplication of 4346 /* XScale MIA instruction. Signed multiplication of
4347 two 32 bit values and addition to 40 bit accumulator. */ 4347 two 32 bit values and addition to 40 bit accumulator. */
4348 long long Rm = 4348 long long Rm =
4349 state-> 4349 state->
4350 Reg 4350 Reg
4351 [MULLHSReg]; 4351 [MULLHSReg];
4352 long long Rs = 4352 long long Rs =
4353 state-> 4353 state->
4354 Reg 4354 Reg
4355 [MULACCReg]; 4355 [MULACCReg];
4356 4356
4357 if (Rm & (1 << 31)) 4357 if (Rm & (1 << 31))
4358 Rm -= 1ULL << 4358 Rm -= 1ULL <<
4359 32; 4359 32;
4360 if (Rs & (1 << 31)) 4360 if (Rs & (1 << 31))
4361 Rs -= 1ULL << 4361 Rs -= 1ULL <<
4362 32; 4362 32;
4363 state->Accumulator += 4363 state->Accumulator +=
4364 Rm * Rs; 4364 Rm * Rs;
4365 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext; 4365 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext;
4366 } 4366 }
4367 break; 4367 break;
4368 4368
4369 case 0x2: 4369 case 0x2:
4370 if (BITS (4, 11) == 1 4370 if (BITS (4, 11) == 1
4371 && BITS (16, 17) == 0) { 4371 && BITS (16, 17) == 0) {
4372 /* XScale MIAPH instruction. */ 4372 /* XScale MIAPH instruction. */
4373 ARMword t1 = 4373 ARMword t1 =
4374 state-> 4374 state->
4375 Reg[MULLHSReg] 4375 Reg[MULLHSReg]
4376 >> 16; 4376 >> 16;
4377 ARMword t2 = 4377 ARMword t2 =
4378 state-> 4378 state->
4379 Reg[MULACCReg] 4379 Reg[MULACCReg]
4380 >> 16; 4380 >> 16;
4381 ARMword t3 = 4381 ARMword t3 =
4382 state-> 4382 state->
4383 Reg[MULLHSReg] 4383 Reg[MULLHSReg]
4384 & 0xffff; 4384 & 0xffff;
4385 ARMword t4 = 4385 ARMword t4 =
4386 state-> 4386 state->
4387 Reg[MULACCReg] 4387 Reg[MULACCReg]
4388 & 0xffff; 4388 & 0xffff;
4389 long long t5; 4389 long long t5;
4390 4390
4391 if (t1 & (1 << 15)) 4391 if (t1 & (1 << 15))
4392 t1 -= 1 << 16; 4392 t1 -= 1 << 16;
4393 if (t2 & (1 << 15)) 4393 if (t2 & (1 << 15))
4394 t2 -= 1 << 16; 4394 t2 -= 1 << 16;
4395 if (t3 & (1 << 15)) 4395 if (t3 & (1 << 15))
4396 t3 -= 1 << 16; 4396 t3 -= 1 << 16;
4397 if (t4 & (1 << 15)) 4397 if (t4 & (1 << 15))
4398 t4 -= 1 << 16; 4398 t4 -= 1 << 16;
4399 t1 *= t2; 4399 t1 *= t2;
4400 t5 = t1; 4400 t5 = t1;
4401 if (t5 & (1 << 31)) 4401 if (t5 & (1 << 31))
4402 t5 -= 1ULL << 4402 t5 -= 1ULL <<
4403 32; 4403 32;
4404 state->Accumulator += 4404 state->Accumulator +=
4405 t5; 4405 t5;
4406 t3 *= t4; 4406 t3 *= t4;
4407 t5 = t3; 4407 t5 = t3;
4408 if (t5 & (1 << 31)) 4408 if (t5 & (1 << 31))
4409 t5 -= 1ULL << 4409 t5 -= 1ULL <<
4410 32; 4410 32;
4411 state->Accumulator += 4411 state->Accumulator +=
4412 t5; 4412 t5;
4413 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext; 4413 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext;
4414 } 4414 }
4415 break; 4415 break;
4416 4416
4417 case 0x3: 4417 case 0x3:
4418 if (BITS (4, 11) == 1) { 4418 if (BITS (4, 11) == 1) {
4419 /* XScale MIAxy instruction. */ 4419 /* XScale MIAxy instruction. */
4420 ARMword t1; 4420 ARMword t1;
4421 ARMword t2; 4421 ARMword t2;
4422 long long t5; 4422 long long t5;
4423 4423
4424 if (BIT (17)) 4424 if (BIT (17))
4425 t1 = state-> 4425 t1 = state->
4426 Reg 4426 Reg
4427 [MULLHSReg] 4427 [MULLHSReg]
4428 >> 16; 4428 >> 16;
4429 else 4429 else
4430 t1 = state-> 4430 t1 = state->
4431 Reg 4431 Reg
4432 [MULLHSReg] 4432 [MULLHSReg]
4433 & 4433 &
4434 0xffff; 4434 0xffff;
4435 4435
4436 if (BIT (16)) 4436 if (BIT (16))
4437 t2 = state-> 4437 t2 = state->
4438 Reg 4438 Reg
4439 [MULACCReg] 4439 [MULACCReg]
4440 >> 16; 4440 >> 16;
4441 else 4441 else
4442 t2 = state-> 4442 t2 = state->
4443 Reg 4443 Reg
4444 [MULACCReg] 4444 [MULACCReg]
4445 & 4445 &
4446 0xffff; 4446 0xffff;
4447 4447
4448 if (t1 & (1 << 15)) 4448 if (t1 & (1 << 15))
4449 t1 -= 1 << 16; 4449 t1 -= 1 << 16;
4450 if (t2 & (1 << 15)) 4450 if (t2 & (1 << 15))
4451 t2 -= 1 << 16; 4451 t2 -= 1 << 16;
4452 t1 *= t2; 4452 t1 *= t2;
4453 t5 = t1; 4453 t5 = t1;
4454 if (t5 & (1 << 31)) 4454 if (t5 & (1 << 31))
4455 t5 -= 1ULL << 4455 t5 -= 1ULL <<
4456 32; 4456 32;
4457 state->Accumulator += 4457 state->Accumulator +=
4458 t5; 4458 t5;
4459 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext; 4459 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext;
4460 } 4460 }
4461 break; 4461 break;
4462 4462
4463 default: 4463 default:
4464 break; 4464 break;
4465 } 4465 }
4466 /* Drop through. */ 4466 /* Drop through. */
4467 4467
4468 case 0xe0: 4468 case 0xe0:
4469 case 0xe4: 4469 case 0xe4:
4470 case 0xe6: 4470 case 0xe6:
4471 case 0xe8: 4471 case 0xe8:
4472 case 0xea: 4472 case 0xea:
4473 case 0xec: 4473 case 0xec:
4474 case 0xee: 4474 case 0xee:
4475 if (BIT (4)) { 4475 if (BIT (4)) {
4476 /* MCR. */ 4476 /* MCR. */
4477 if (DESTReg == 15) { 4477 if (DESTReg == 15) {
4478 UNDEF_MCRPC; 4478 UNDEF_MCRPC;
4479#ifdef MODE32 4479#ifdef MODE32
4480 ARMul_MCR (state, instr, 4480 ARMul_MCR (state, instr,
4481 state->Reg[15] + 4481 state->Reg[15] +
4482 isize); 4482 isize);
4483#else 4483#else
4484 ARMul_MCR (state, instr, 4484 ARMul_MCR (state, instr,
4485 ECC | ER15INT | 4485 ECC | ER15INT |
4486 EMODE | 4486 EMODE |
4487 ((state->Reg[15] + 4487 ((state->Reg[15] +
4488 isize) & 4488 isize) &
4489 R15PCBITS)); 4489 R15PCBITS));
4490#endif 4490#endif
4491 } 4491 }
4492 else 4492 else
4493 ARMul_MCR (state, instr, 4493 ARMul_MCR (state, instr,
4494 DEST); 4494 DEST);
4495 } 4495 }
4496 else 4496 else
4497 /* CDP Part 1. */ 4497 /* CDP Part 1. */
4498 ARMul_CDP (state, instr); 4498 ARMul_CDP (state, instr);
4499 break; 4499 break;
4500 4500
4501 4501
4502 /* Co-Processor Register Transfers (MRC) and Data Ops. */ 4502 /* Co-Processor Register Transfers (MRC) and Data Ops. */
4503 case 0xe1: 4503 case 0xe1:
4504 case 0xe3: 4504 case 0xe3:
4505 case 0xe5: 4505 case 0xe5:
4506 case 0xe7: 4506 case 0xe7:
4507 case 0xe9: 4507 case 0xe9:
4508 case 0xeb: 4508 case 0xeb:
4509 case 0xed: 4509 case 0xed:
4510 case 0xef: 4510 case 0xef:
4511 if (BIT (4)) { 4511 if (BIT (4)) {
4512 /* MRC */ 4512 /* MRC */
4513 temp = ARMul_MRC (state, instr); 4513 temp = ARMul_MRC (state, instr);
4514 if (DESTReg == 15) { 4514 if (DESTReg == 15) {
4515 ASSIGNN ((temp & NBIT) != 0); 4515 ASSIGNN ((temp & NBIT) != 0);
4516 ASSIGNZ ((temp & ZBIT) != 0); 4516 ASSIGNZ ((temp & ZBIT) != 0);
4517 ASSIGNC ((temp & CBIT) != 0); 4517 ASSIGNC ((temp & CBIT) != 0);
4518 ASSIGNV ((temp & VBIT) != 0); 4518 ASSIGNV ((temp & VBIT) != 0);
4519 } 4519 }
4520 else 4520 else
4521 DEST = temp; 4521 DEST = temp;
4522 } 4522 }
4523 else 4523 else
4524 /* CDP Part 2. */ 4524 /* CDP Part 2. */
4525 ARMul_CDP (state, instr); 4525 ARMul_CDP (state, instr);
4526 break; 4526 break;
4527 4527
4528 4528
4529 /* SWI instruction. */ 4529 /* SWI instruction. */
4530 case 0xf0: 4530 case 0xf0:
4531 case 0xf1: 4531 case 0xf1:
4532 case 0xf2: 4532 case 0xf2:
4533 case 0xf3: 4533 case 0xf3:
4534 case 0xf4: 4534 case 0xf4:
4535 case 0xf5: 4535 case 0xf5:
4536 case 0xf6: 4536 case 0xf6:
4537 case 0xf7: 4537 case 0xf7:
4538 case 0xf8: 4538 case 0xf8:
4539 case 0xf9: 4539 case 0xf9:
4540 case 0xfa: 4540 case 0xfa:
4541 case 0xfb: 4541 case 0xfb:
4542 case 0xfc: 4542 case 0xfc:
4543 case 0xfd: 4543 case 0xfd:
4544 case 0xfe: 4544 case 0xfe:
4545 case 0xff: 4545 case 0xff:
4546 if (instr == ARMul_ABORTWORD 4546 if (instr == ARMul_ABORTWORD
4547 && state->AbortAddr == pc) { 4547 && state->AbortAddr == pc) {
4548 /* A prefetch abort. */ 4548 /* A prefetch abort. */
4549 XScale_set_fsr_far (state, 4549 XScale_set_fsr_far (state,
4550 ARMul_CP15_R5_MMU_EXCPT, 4550 ARMul_CP15_R5_MMU_EXCPT,
4551 pc); 4551 pc);
4552 ARMul_Abort (state, 4552 ARMul_Abort (state,
4553 ARMul_PrefetchAbortV); 4553 ARMul_PrefetchAbortV);
4554 break; 4554 break;
4555 } 4555 }
4556 //sky_pref_t* pref = get_skyeye_pref(); 4556 //sky_pref_t* pref = get_skyeye_pref();
4557 //if(pref->user_mode_sim){ 4557 //if(pref->user_mode_sim){
4558 // ARMul_OSHandleSWI (state, BITS (0, 23)); 4558 // ARMul_OSHandleSWI (state, BITS (0, 23));
4559 // break; 4559 // break;
4560 //} 4560 //}
4561 ARMul_Abort (state, ARMul_SWIV); 4561 ARMul_Abort (state, ARMul_SWIV);
4562 break; 4562 break;
4563 } 4563 }
4564 } 4564 }
4565 4565
4566#ifdef MODET 4566#ifdef MODET
4567 donext: 4567 donext:
4568#endif 4568#endif
4569 state->pc = pc; 4569 state->pc = pc;
4570#if 0 4570#if 0
4571 /* shenoubang */ 4571 /* shenoubang */
4572 instr_sum++; 4572 instr_sum++;
4573 int i, j; 4573 int i, j;
4574 i = j = 0; 4574 i = j = 0;
4575 if (instr_sum >= 7388648) { 4575 if (instr_sum >= 7388648) {
4576 //if (pc == 0xc0008ab4) { 4576 //if (pc == 0xc0008ab4) {
4577 // printf("instr_sum: %d\n", instr_sum); 4577 // printf("instr_sum: %d\n", instr_sum);
4578 // start_kernel : 0xc000895c 4578 // start_kernel : 0xc000895c
4579 printf("--------------------------------------------------\n"); 4579 printf("--------------------------------------------------\n");
4580 for (i = 0; i < 16; i++) { 4580 for (i = 0; i < 16; i++) {
4581 printf("[R%02d]:[0x%08x]\t", i, state->Reg[i]); 4581 printf("[R%02d]:[0x%08x]\t", i, state->Reg[i]);
4582 if ((i % 3) == 2) { 4582 if ((i % 3) == 2) {
4583 printf("\n"); 4583 printf("\n");
4584 } 4584 }
4585 } 4585 }
4586 printf("[cpr]:[0x%08x]\t[spr0]:[0x%08x]\n", state->Cpsr, state->Spsr[0]); 4586 printf("[cpr]:[0x%08x]\t[spr0]:[0x%08x]\n", state->Cpsr, state->Spsr[0]);
4587 for (j = 1; j < 7; j++) { 4587 for (j = 1; j < 7; j++) {
4588 printf("[spr%d]:[0x%08x]\t", j, state->Spsr[j]); 4588 printf("[spr%d]:[0x%08x]\t", j, state->Spsr[j]);
4589 if ((j % 4) == 3) { 4589 if ((j % 4) == 3) {
4590 printf("\n"); 4590 printf("\n");
4591 } 4591 }
4592 } 4592 }
4593 printf("\n[PC]:[0x%08x]\t[INST]:[0x%08x]\t[COUNT]:[%d]\n", pc, instr, instr_sum); 4593 printf("\n[PC]:[0x%08x]\t[INST]:[0x%08x]\t[COUNT]:[%d]\n", pc, instr, instr_sum);
4594 printf("--------------------------------------------------\n"); 4594 printf("--------------------------------------------------\n");
4595 } 4595 }
4596#endif 4596#endif
4597 4597
4598#if 0 4598#if 0
4599 fprintf(state->state_log, "PC:0x%x\n", pc); 4599 fprintf(state->state_log, "PC:0x%x\n", pc);
4600 for (reg_index = 0; reg_index < 16; reg_index ++) { 4600 for (reg_index = 0; reg_index < 16; reg_index ++) {
4601 if (state->Reg[reg_index] != mirror_register_file[reg_index]) { 4601 if (state->Reg[reg_index] != mirror_register_file[reg_index]) {
4602 fprintf(state->state_log, "R%d:0x%x\n", reg_index, state->Reg[reg_index]); 4602 fprintf(state->state_log, "R%d:0x%x\n", reg_index, state->Reg[reg_index]);
4603 mirror_register_file[reg_index] = state->Reg[reg_index]; 4603 mirror_register_file[reg_index] = state->Reg[reg_index];
4604 } 4604 }
4605 } 4605 }
4606 if (state->Cpsr != mirror_register_file[CPSR_REG]) { 4606 if (state->Cpsr != mirror_register_file[CPSR_REG]) {
4607 fprintf(state->state_log, "Cpsr:0x%x\n", state->Cpsr); 4607 fprintf(state->state_log, "Cpsr:0x%x\n", state->Cpsr);
4608 mirror_register_file[CPSR_REG] = state->Cpsr; 4608 mirror_register_file[CPSR_REG] = state->Cpsr;
4609 } 4609 }
4610 if (state->RegBank[SVCBANK][13] != mirror_register_file[R13_SVC]) { 4610 if (state->RegBank[SVCBANK][13] != mirror_register_file[R13_SVC]) {
4611 fprintf(state->state_log, "R13_SVC:0x%x\n", state->RegBank[SVCBANK][13]); 4611 fprintf(state->state_log, "R13_SVC:0x%x\n", state->RegBank[SVCBANK][13]);
4612 mirror_register_file[R13_SVC] = state->RegBank[SVCBANK][13]; 4612 mirror_register_file[R13_SVC] = state->RegBank[SVCBANK][13];
@@ -4691,67 +4691,67 @@ ARMul_Emulate26 (ARMul_State * state)
4691#endif 4691#endif
4692 4692
4693#ifdef NEED_UI_LOOP_HOOK 4693#ifdef NEED_UI_LOOP_HOOK
4694 if (ui_loop_hook != NULL && ui_loop_hook_counter-- < 0) { 4694 if (ui_loop_hook != NULL && ui_loop_hook_counter-- < 0) {
4695 ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL; 4695 ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL;
4696 ui_loop_hook (0); 4696 ui_loop_hook (0);
4697 } 4697 }
4698#endif /* NEED_UI_LOOP_HOOK */ 4698#endif /* NEED_UI_LOOP_HOOK */
4699 4699
4700 /*added energy_prof statement by ksh in 2004-11-26 */ 4700 /*added energy_prof statement by ksh in 2004-11-26 */
4701 //chy 2005-07-28 for standalone 4701 //chy 2005-07-28 for standalone
4702 //ARMul_do_energy(state,instr,pc); 4702 //ARMul_do_energy(state,instr,pc);
4703//teawater add for record reg value to ./reg.txt 2005.07.10--------------------- 4703//teawater add for record reg value to ./reg.txt 2005.07.10---------------------
4704 if (state->tea_break_ok && pc == state->tea_break_addr) { 4704 if (state->tea_break_ok && pc == state->tea_break_addr) {
4705 ARMul_Debug (state, 0, 0); 4705 ARMul_Debug (state, 0, 0);
4706 state->tea_break_ok = 0; 4706 state->tea_break_ok = 0;
4707 } 4707 }
4708 else { 4708 else {
4709 state->tea_break_ok = 1; 4709 state->tea_break_ok = 1;
4710 } 4710 }
4711//AJ2D-------------------------------------------------------------------------- 4711//AJ2D--------------------------------------------------------------------------
4712//chy 2006-04-14 for ctrl-c debug 4712//chy 2006-04-14 for ctrl-c debug
4713#if 0 4713#if 0
4714 if (debugmode) { 4714 if (debugmode) {
4715 if (instr != ARMul_ABORTWORD) { 4715 if (instr != ARMul_ABORTWORD) {
4716 remote_interrupt_test_time++; 4716 remote_interrupt_test_time++;
4717 //chy 2006-04-14 2000 should be changed in skyeye_conf ???!!! 4717 //chy 2006-04-14 2000 should be changed in skyeye_conf ???!!!
4718 if (remote_interrupt_test_time >= 2000) { 4718 if (remote_interrupt_test_time >= 2000) {
4719 remote_interrupt_test_time=0; 4719 remote_interrupt_test_time=0;
4720 if (remote_interrupt()) { 4720 if (remote_interrupt()) {
4721 //for test 4721 //for test
4722 //printf("SKYEYE: ICE_debug recv Ctrl_C\n"); 4722 //printf("SKYEYE: ICE_debug recv Ctrl_C\n");
4723 state->EndCondition = 0; 4723 state->EndCondition = 0;
4724 state->Emulate = STOP; 4724 state->Emulate = STOP;
4725 } 4725 }
4726 } 4726 }
4727 } 4727 }
4728 } 4728 }
4729#endif 4729#endif
4730 4730
4731 /* jump out every time */ 4731 /* jump out every time */
4732 //state->EndCondition = 0; 4732 //state->EndCondition = 0;
4733 //state->Emulate = STOP; 4733 //state->Emulate = STOP;
4734//chy 2006-04-12 for ICE debug 4734//chy 2006-04-12 for ICE debug
4735TEST_EMULATE: 4735TEST_EMULATE:
4736 if (state->Emulate == ONCE) 4736 if (state->Emulate == ONCE)
4737 state->Emulate = STOP; 4737 state->Emulate = STOP;
4738 //chy: 2003-08-23: should not use CHANGEMODE !!!! 4738 //chy: 2003-08-23: should not use CHANGEMODE !!!!
4739 /* If we have changed mode, allow the PC to advance before stopping. */ 4739 /* If we have changed mode, allow the PC to advance before stopping. */
4740 // else if (state->Emulate == CHANGEMODE) 4740 // else if (state->Emulate == CHANGEMODE)
4741 // continue; 4741 // continue;
4742 else if (state->Emulate != RUN) 4742 else if (state->Emulate != RUN)
4743 break; 4743 break;
4744 } 4744 }
4745 while (!state->stop_simulator); 4745 while (!state->stop_simulator);
4746 4746
4747 state->decoded = decoded; 4747 state->decoded = decoded;
4748 state->loaded = loaded; 4748 state->loaded = loaded;
4749 state->pc = pc; 4749 state->pc = pc;
4750 //chy 2006-04-12, for ICE debug 4750 //chy 2006-04-12, for ICE debug
4751 state->decoded_addr=decoded_addr; 4751 state->decoded_addr=decoded_addr;
4752 state->loaded_addr=loaded_addr; 4752 state->loaded_addr=loaded_addr;
4753 4753
4754 return pc; 4754 return pc;
4755} 4755}
4756 4756
4757//teawater add for arm2x86 2005.02.17------------------------------------------- 4757//teawater add for arm2x86 2005.02.17-------------------------------------------
@@ -4774,215 +4774,215 @@ static volatile uint32_t save_T2;
4774ARMword 4774ARMword
4775ARMul_Emulate32_dbct (ARMul_State * state) 4775ARMul_Emulate32_dbct (ARMul_State * state)
4776{ 4776{
4777 static int init = 0; 4777 static int init = 0;
4778 static FILE *fd; 4778 static FILE *fd;
4779 4779
4780 /*if (!init) { 4780 /*if (!init) {
4781 4781
4782 fd = fopen("./pc.txt", "w"); 4782 fd = fopen("./pc.txt", "w");
4783 if (!fd) { 4783 if (!fd) {
4784 exit(-1); 4784 exit(-1);
4785 } 4785 }
4786 init = 1; 4786 init = 1;
4787 } */ 4787 } */
4788 4788
4789 state->Reg[15] += INSN_SIZE; 4789 state->Reg[15] += INSN_SIZE;
4790 do { 4790 do {
4791 /*if (skyeye_config.log.logon>=1) { 4791 /*if (skyeye_config.log.logon>=1) {
4792 if (state->NumInstrs>=skyeye_config.log.start && state->NumInstrs<=skyeye_config.log.end) { 4792 if (state->NumInstrs>=skyeye_config.log.start && state->NumInstrs<=skyeye_config.log.end) {
4793 static int mybegin=0; 4793 static int mybegin=0;
4794 static int myinstrnum=0; 4794 static int myinstrnum=0;
4795 4795
4796 if (mybegin==0) mybegin=1; 4796 if (mybegin==0) mybegin=1;
4797 if (mybegin==1) { 4797 if (mybegin==1) {
4798 state->Reg[15] -= INSN_SIZE; 4798 state->Reg[15] -= INSN_SIZE;
4799 if (skyeye_config.log.logon>=1) fprintf(skyeye_logfd,"N %llx :p %x,i %x,",state->NumInstrs, (state->Reg[15] - INSN_SIZE), instr); 4799 if (skyeye_config.log.logon>=1) fprintf(skyeye_logfd,"N %llx :p %x,i %x,",state->NumInstrs, (state->Reg[15] - INSN_SIZE), instr);
4800 if (skyeye_config.log.logon>=2) SKYEYE_OUTREGS(skyeye_logfd); 4800 if (skyeye_config.log.logon>=2) SKYEYE_OUTREGS(skyeye_logfd);
4801 if (skyeye_config.log.logon>=3) SKYEYE_OUTMOREREGS(skyeye_logfd); 4801 if (skyeye_config.log.logon>=3) SKYEYE_OUTMOREREGS(skyeye_logfd);
4802 fprintf(skyeye_logfd,"\n"); 4802 fprintf(skyeye_logfd,"\n");
4803 if (skyeye_config.log.length>0) { 4803 if (skyeye_config.log.length>0) {
4804 myinstrnum++; 4804 myinstrnum++;
4805 if (myinstrnum>=skyeye_config.log.length) { 4805 if (myinstrnum>=skyeye_config.log.length) {
4806 myinstrnum=0; 4806 myinstrnum=0;
4807 fflush(skyeye_logfd); 4807 fflush(skyeye_logfd);
4808 fseek(skyeye_logfd,0L,SEEK_SET); 4808 fseek(skyeye_logfd,0L,SEEK_SET);
4809 } 4809 }
4810 } 4810 }
4811 state->Reg[15] += INSN_SIZE; 4811 state->Reg[15] += INSN_SIZE;
4812 } 4812 }
4813 } 4813 }
4814 } */ 4814 } */
4815 state->trap = 0; 4815 state->trap = 0;
4816 gen_func = 4816 gen_func =
4817 (void *) tb_find (state, state->Reg[15] - INSN_SIZE); 4817 (void *) tb_find (state, state->Reg[15] - INSN_SIZE);
4818 if (!gen_func) { 4818 if (!gen_func) {
4819 //fprintf(stderr, "SKYEYE: tb_find: Error in find the translate block.\n"); 4819 //fprintf(stderr, "SKYEYE: tb_find: Error in find the translate block.\n");
4820 //exit(-1); 4820 //exit(-1);
4821 //TRAP_INSN_ABORT 4821 //TRAP_INSN_ABORT
4822 //TEA_OUT(printf("\n------------\npc:%x\n", state->Reg[15] - INSN_SIZE)); 4822 //TEA_OUT(printf("\n------------\npc:%x\n", state->Reg[15] - INSN_SIZE));
4823 //TEA_OUT(printf("TRAP_INSN_ABORT\n")); 4823 //TEA_OUT(printf("TRAP_INSN_ABORT\n"));
4824//teawater add for xscale(arm v5) 2005.09.01------------------------------------ 4824//teawater add for xscale(arm v5) 2005.09.01------------------------------------
4825 /*XScale_set_fsr_far(state, ARMul_CP15_R5_MMU_EXCPT, state->Reg[15] - INSN_SIZE); 4825 /*XScale_set_fsr_far(state, ARMul_CP15_R5_MMU_EXCPT, state->Reg[15] - INSN_SIZE);
4826 state->Reg[15] += INSN_SIZE; 4826 state->Reg[15] += INSN_SIZE;
4827 ARMul_Abort(state, ARMul_PrefetchAbortV); 4827 ARMul_Abort(state, ARMul_PrefetchAbortV);
4828 state->Reg[15] += INSN_SIZE; 4828 state->Reg[15] += INSN_SIZE;
4829 goto next; */ 4829 goto next; */
4830 state->trap = TRAP_INSN_ABORT; 4830 state->trap = TRAP_INSN_ABORT;
4831 goto check; 4831 goto check;
4832//AJ2D-------------------------------------------------------------------------- 4832//AJ2D--------------------------------------------------------------------------
4833 } 4833 }
4834 4834
4835 save_st = (uint32_t) st; 4835 save_st = (uint32_t) st;
4836 save_T0 = T0; 4836 save_T0 = T0;
4837 save_T1 = T1; 4837 save_T1 = T1;
4838 save_T2 = T2; 4838 save_T2 = T2;
4839 tmp_st = (uint32_t) state; 4839 tmp_st = (uint32_t) state;
4840 wmb (); 4840 wmb ();
4841 st = (ARMul_State *) tmp_st; 4841 st = (ARMul_State *) tmp_st;
4842 gen_func (); 4842 gen_func ();
4843 st = (ARMul_State *) save_st; 4843 st = (ARMul_State *) save_st;
4844 T0 = save_T0; 4844 T0 = save_T0;
4845 T1 = save_T1; 4845 T1 = save_T1;
4846 T2 = save_T2; 4846 T2 = save_T2;
4847 4847
4848 /*if (state->trap != TRAP_OUT) { 4848 /*if (state->trap != TRAP_OUT) {
4849 state->tea_break_ok = 1; 4849 state->tea_break_ok = 1;
4850 } 4850 }
4851 if (state->trap <= TRAP_SET_R15) { 4851 if (state->trap <= TRAP_SET_R15) {
4852 goto next; 4852 goto next;
4853 } */ 4853 } */
4854 //TEA_OUT(printf("\n------------\npc:%x\n", state->Reg[15] - INSN_SIZE)); 4854 //TEA_OUT(printf("\n------------\npc:%x\n", state->Reg[15] - INSN_SIZE));
4855//teawater add check thumb 2005.07.21------------------------------------------- 4855//teawater add check thumb 2005.07.21-------------------------------------------
4856 /*if (TFLAG) { 4856 /*if (TFLAG) {
4857 state->Reg[15] -= 2; 4857 state->Reg[15] -= 2;
4858 return(state->Reg[15]); 4858 return(state->Reg[15]);
4859 } */ 4859 } */
4860//AJ2D-------------------------------------------------------------------------- 4860//AJ2D--------------------------------------------------------------------------
4861 4861
4862//teawater add for xscale(arm v5) 2005.09.01------------------------------------ 4862//teawater add for xscale(arm v5) 2005.09.01------------------------------------
4863 check: 4863 check:
4864//AJ2D-------------------------------------------------------------------------- 4864//AJ2D--------------------------------------------------------------------------
4865 switch (state->trap) { 4865 switch (state->trap) {
4866 case TRAP_RESET: 4866 case TRAP_RESET:
4867 { 4867 {
4868 //TEA_OUT(printf("TRAP_RESET\n")); 4868 //TEA_OUT(printf("TRAP_RESET\n"));
4869 ARMul_Abort (state, ARMul_ResetV); 4869 ARMul_Abort (state, ARMul_ResetV);
4870 state->Reg[15] += INSN_SIZE; 4870 state->Reg[15] += INSN_SIZE;
4871 } 4871 }
4872 break; 4872 break;
4873 case TRAP_UNPREDICTABLE: 4873 case TRAP_UNPREDICTABLE:
4874 { 4874 {
4875 ARMul_Debug (state, 0, 0); 4875 ARMul_Debug (state, 0, 0);
4876 } 4876 }
4877 break; 4877 break;
4878 case TRAP_INSN_UNDEF: 4878 case TRAP_INSN_UNDEF:
4879 { 4879 {
4880 //TEA_OUT(printf("TRAP_INSN_UNDEF\n")); 4880 //TEA_OUT(printf("TRAP_INSN_UNDEF\n"));
4881 state->Reg[15] += INSN_SIZE; 4881 state->Reg[15] += INSN_SIZE;
4882 ARMul_UndefInstr (state, 0); 4882 ARMul_UndefInstr (state, 0);
4883 state->Reg[15] += INSN_SIZE; 4883 state->Reg[15] += INSN_SIZE;
4884 } 4884 }
4885 break; 4885 break;
4886 case TRAP_SWI: 4886 case TRAP_SWI:
4887 { 4887 {
4888 //TEA_OUT(printf("TRAP_SWI\n")); 4888 //TEA_OUT(printf("TRAP_SWI\n"));
4889 state->Reg[15] += INSN_SIZE; 4889 state->Reg[15] += INSN_SIZE;
4890 ARMul_Abort (state, ARMul_SWIV); 4890 ARMul_Abort (state, ARMul_SWIV);
4891 state->Reg[15] += INSN_SIZE; 4891 state->Reg[15] += INSN_SIZE;
4892 } 4892 }
4893 break; 4893 break;
4894//teawater add for xscale(arm v5) 2005.09.01------------------------------------ 4894//teawater add for xscale(arm v5) 2005.09.01------------------------------------
4895 case TRAP_INSN_ABORT: 4895 case TRAP_INSN_ABORT:
4896 { 4896 {
4897 XScale_set_fsr_far (state, 4897 XScale_set_fsr_far (state,
4898 ARMul_CP15_R5_MMU_EXCPT, 4898 ARMul_CP15_R5_MMU_EXCPT,
4899 state->Reg[15] - 4899 state->Reg[15] -
4900 INSN_SIZE); 4900 INSN_SIZE);
4901 state->Reg[15] += INSN_SIZE; 4901 state->Reg[15] += INSN_SIZE;
4902 ARMul_Abort (state, ARMul_PrefetchAbortV); 4902 ARMul_Abort (state, ARMul_PrefetchAbortV);
4903 state->Reg[15] += INSN_SIZE; 4903 state->Reg[15] += INSN_SIZE;
4904 } 4904 }
4905 break; 4905 break;
4906//AJ2D-------------------------------------------------------------------------- 4906//AJ2D--------------------------------------------------------------------------
4907 case TRAP_DATA_ABORT: 4907 case TRAP_DATA_ABORT:
4908 { 4908 {
4909 //TEA_OUT(printf("TRAP_DATA_ABORT\n")); 4909 //TEA_OUT(printf("TRAP_DATA_ABORT\n"));
4910 state->Reg[15] += INSN_SIZE; 4910 state->Reg[15] += INSN_SIZE;
4911 ARMul_Abort (state, ARMul_DataAbortV); 4911 ARMul_Abort (state, ARMul_DataAbortV);
4912 state->Reg[15] += INSN_SIZE; 4912 state->Reg[15] += INSN_SIZE;
4913 } 4913 }
4914 break; 4914 break;
4915 case TRAP_IRQ: 4915 case TRAP_IRQ:
4916 { 4916 {
4917 //TEA_OUT(printf("TRAP_IRQ\n")); 4917 //TEA_OUT(printf("TRAP_IRQ\n"));
4918 state->Reg[15] += INSN_SIZE; 4918 state->Reg[15] += INSN_SIZE;
4919 ARMul_Abort (state, ARMul_IRQV); 4919 ARMul_Abort (state, ARMul_IRQV);
4920 state->Reg[15] += INSN_SIZE; 4920 state->Reg[15] += INSN_SIZE;
4921 } 4921 }
4922 break; 4922 break;
4923 case TRAP_FIQ: 4923 case TRAP_FIQ:
4924 { 4924 {
4925 //TEA_OUT(printf("TRAP_FIQ\n")); 4925 //TEA_OUT(printf("TRAP_FIQ\n"));
4926 state->Reg[15] += INSN_SIZE; 4926 state->Reg[15] += INSN_SIZE;
4927 ARMul_Abort (state, ARMul_FIQV); 4927 ARMul_Abort (state, ARMul_FIQV);
4928 state->Reg[15] += INSN_SIZE; 4928 state->Reg[15] += INSN_SIZE;
4929 } 4929 }
4930 break; 4930 break;
4931 case TRAP_SETS_R15: 4931 case TRAP_SETS_R15:
4932 { 4932 {
4933 //TEA_OUT(printf("TRAP_SETS_R15\n")); 4933 //TEA_OUT(printf("TRAP_SETS_R15\n"));
4934 /*if (state->Bank > 0) { 4934 /*if (state->Bank > 0) {
4935 state->Cpsr = state->Spsr[state->Bank]; 4935 state->Cpsr = state->Spsr[state->Bank];
4936 ARMul_CPSRAltered (state); 4936 ARMul_CPSRAltered (state);
4937 } */ 4937 } */
4938 WriteSR15 (state, state->Reg[15]); 4938 WriteSR15 (state, state->Reg[15]);
4939 } 4939 }
4940 break; 4940 break;
4941 case TRAP_SET_CPSR: 4941 case TRAP_SET_CPSR:
4942 { 4942 {
4943 //TEA_OUT(printf("TRAP_SET_CPSR\n")); 4943 //TEA_OUT(printf("TRAP_SET_CPSR\n"));
4944 //chy 2006-02-15 USERBANK=SYSTEMBANK=0 4944 //chy 2006-02-15 USERBANK=SYSTEMBANK=0
4945 //chy 2006-02-16 should use Mode to test 4945 //chy 2006-02-16 should use Mode to test
4946 //if (state->Bank > 0) { 4946 //if (state->Bank > 0) {
4947 if (state->Mode != USER26MODE && state->Mode != USER32MODE){ 4947 if (state->Mode != USER26MODE && state->Mode != USER32MODE){
4948 ARMul_CPSRAltered (state); 4948 ARMul_CPSRAltered (state);
4949 } 4949 }
4950 state->Reg[15] += INSN_SIZE; 4950 state->Reg[15] += INSN_SIZE;
4951 } 4951 }
4952 break; 4952 break;
4953 case TRAP_OUT: 4953 case TRAP_OUT:
4954 { 4954 {
4955 //TEA_OUT(printf("TRAP_OUT\n")); 4955 //TEA_OUT(printf("TRAP_OUT\n"));
4956 goto out; 4956 goto out;
4957 } 4957 }
4958 break; 4958 break;
4959 case TRAP_BREAKPOINT: 4959 case TRAP_BREAKPOINT:
4960 { 4960 {
4961 //TEA_OUT(printf("TRAP_BREAKPOINT\n")); 4961 //TEA_OUT(printf("TRAP_BREAKPOINT\n"));
4962 state->Reg[15] -= INSN_SIZE; 4962 state->Reg[15] -= INSN_SIZE;
4963 if (!ARMul_OSHandleSWI 4963 if (!ARMul_OSHandleSWI
4964 (state, SWI_Breakpoint)) { 4964 (state, SWI_Breakpoint)) {
4965 ARMul_Abort (state, ARMul_SWIV); 4965 ARMul_Abort (state, ARMul_SWIV);
4966 } 4966 }
4967 state->Reg[15] += INSN_SIZE; 4967 state->Reg[15] += INSN_SIZE;
4968 } 4968 }
4969 break; 4969 break;
4970 } 4970 }
4971 4971
4972 next: 4972 next:
4973 if (state->Emulate == ONCE) { 4973 if (state->Emulate == ONCE) {
4974 state->Emulate = STOP; 4974 state->Emulate = STOP;
4975 break; 4975 break;
4976 } 4976 }
4977 else if (state->Emulate != RUN) { 4977 else if (state->Emulate != RUN) {
4978 break; 4978 break;
4979 } 4979 }
4980 } 4980 }
4981 while (!state->stop_simulator); 4981 while (!state->stop_simulator);
4982 4982
4983 out: 4983 out:
4984 state->Reg[15] -= INSN_SIZE; 4984 state->Reg[15] -= INSN_SIZE;
4985 return (state->Reg[15]); 4985 return (state->Reg[15]);
4986} 4986}
4987#endif 4987#endif
4988//AJ2D-------------------------------------------------------------------------- 4988//AJ2D--------------------------------------------------------------------------
@@ -4996,87 +4996,87 @@ ARMul_Emulate32_dbct (ARMul_State * state)
4996static ARMword 4996static ARMword
4997GetDPRegRHS (ARMul_State * state, ARMword instr) 4997GetDPRegRHS (ARMul_State * state, ARMword instr)
4998{ 4998{
4999 ARMword shamt, base; 4999 ARMword shamt, base;
5000 5000
5001 base = RHSReg; 5001 base = RHSReg;
5002 if (BIT (4)) { 5002 if (BIT (4)) {
5003 /* Shift amount in a register. */ 5003 /* Shift amount in a register. */
5004 UNDEF_Shift; 5004 UNDEF_Shift;
5005 INCPC; 5005 INCPC;
5006#ifndef MODE32 5006#ifndef MODE32
5007 if (base == 15) 5007 if (base == 15)
5008 base = ECC | ER15INT | R15PC | EMODE; 5008 base = ECC | ER15INT | R15PC | EMODE;
5009 else 5009 else
5010#endif 5010#endif
5011 base = state->Reg[base]; 5011 base = state->Reg[base];
5012 ARMul_Icycles (state, 1, 0L); 5012 ARMul_Icycles (state, 1, 0L);
5013 shamt = state->Reg[BITS (8, 11)] & 0xff; 5013 shamt = state->Reg[BITS (8, 11)] & 0xff;
5014 switch ((int) BITS (5, 6)) { 5014 switch ((int) BITS (5, 6)) {
5015 case LSL: 5015 case LSL:
5016 if (shamt == 0) 5016 if (shamt == 0)
5017 return (base); 5017 return (base);
5018 else if (shamt >= 32) 5018 else if (shamt >= 32)
5019 return (0); 5019 return (0);
5020 else 5020 else
5021 return (base << shamt); 5021 return (base << shamt);
5022 case LSR: 5022 case LSR:
5023 if (shamt == 0) 5023 if (shamt == 0)
5024 return (base); 5024 return (base);
5025 else if (shamt >= 32) 5025 else if (shamt >= 32)
5026 return (0); 5026 return (0);
5027 else 5027 else
5028 return (base >> shamt); 5028 return (base >> shamt);
5029 case ASR: 5029 case ASR:
5030 if (shamt == 0) 5030 if (shamt == 0)
5031 return (base); 5031 return (base);
5032 else if (shamt >= 32) 5032 else if (shamt >= 32)
5033 return ((ARMword) ((int) base >> 31L)); 5033 return ((ARMword) ((int) base >> 31L));
5034 else 5034 else
5035 return ((ARMword) 5035 return ((ARMword)
5036 (( int) base >> (int) shamt)); 5036 (( int) base >> (int) shamt));
5037 case ROR: 5037 case ROR:
5038 shamt &= 0x1f; 5038 shamt &= 0x1f;
5039 if (shamt == 0) 5039 if (shamt == 0)
5040 return (base); 5040 return (base);
5041 else 5041 else
5042 return ((base << (32 - shamt)) | 5042 return ((base << (32 - shamt)) |
5043 (base >> shamt)); 5043 (base >> shamt));
5044 } 5044 }
5045 } 5045 }
5046 else { 5046 else {
5047 /* Shift amount is a constant. */ 5047 /* Shift amount is a constant. */
5048#ifndef MODE32 5048#ifndef MODE32
5049 if (base == 15) 5049 if (base == 15)
5050 base = ECC | ER15INT | R15PC | EMODE; 5050 base = ECC | ER15INT | R15PC | EMODE;
5051 else 5051 else
5052#endif 5052#endif
5053 base = state->Reg[base]; 5053 base = state->Reg[base];
5054 shamt = BITS (7, 11); 5054 shamt = BITS (7, 11);
5055 switch ((int) BITS (5, 6)) { 5055 switch ((int) BITS (5, 6)) {
5056 case LSL: 5056 case LSL:
5057 return (base << shamt); 5057 return (base << shamt);
5058 case LSR: 5058 case LSR:
5059 if (shamt == 0) 5059 if (shamt == 0)
5060 return (0); 5060 return (0);
5061 else 5061 else
5062 return (base >> shamt); 5062 return (base >> shamt);
5063 case ASR: 5063 case ASR:
5064 if (shamt == 0) 5064 if (shamt == 0)
5065 return ((ARMword) (( int) base >> 31L)); 5065 return ((ARMword) (( int) base >> 31L));
5066 else 5066 else
5067 return ((ARMword) 5067 return ((ARMword)
5068 (( int) base >> (int) shamt)); 5068 (( int) base >> (int) shamt));
5069 case ROR: 5069 case ROR:
5070 if (shamt == 0) 5070 if (shamt == 0)
5071 /* It's an RRX. */ 5071 /* It's an RRX. */
5072 return ((base >> 1) | (CFLAG << 31)); 5072 return ((base >> 1) | (CFLAG << 31));
5073 else 5073 else
5074 return ((base << (32 - shamt)) | 5074 return ((base << (32 - shamt)) |
5075 (base >> shamt)); 5075 (base >> shamt));
5076 } 5076 }
5077 } 5077 }
5078 5078
5079 return 0; 5079 return 0;
5080} 5080}
5081 5081
5082/* This routine evaluates most Logical Data Processing register RHS's 5082/* This routine evaluates most Logical Data Processing register RHS's
@@ -5087,132 +5087,132 @@ GetDPRegRHS (ARMul_State * state, ARMword instr)
5087static ARMword 5087static ARMword
5088GetDPSRegRHS (ARMul_State * state, ARMword instr) 5088GetDPSRegRHS (ARMul_State * state, ARMword instr)
5089{ 5089{
5090 ARMword shamt, base; 5090 ARMword shamt, base;
5091 5091
5092 base = RHSReg; 5092 base = RHSReg;
5093 if (BIT (4)) { 5093 if (BIT (4)) {
5094 /* Shift amount in a register. */ 5094 /* Shift amount in a register. */
5095 UNDEF_Shift; 5095 UNDEF_Shift;
5096 INCPC; 5096 INCPC;
5097#ifndef MODE32 5097#ifndef MODE32
5098 if (base == 15) 5098 if (base == 15)
5099 base = ECC | ER15INT | R15PC | EMODE; 5099 base = ECC | ER15INT | R15PC | EMODE;
5100 else 5100 else
5101#endif 5101#endif
5102 base = state->Reg[base]; 5102 base = state->Reg[base];
5103 ARMul_Icycles (state, 1, 0L); 5103 ARMul_Icycles (state, 1, 0L);
5104 shamt = state->Reg[BITS (8, 11)] & 0xff; 5104 shamt = state->Reg[BITS (8, 11)] & 0xff;
5105 switch ((int) BITS (5, 6)) { 5105 switch ((int) BITS (5, 6)) {
5106 case LSL: 5106 case LSL:
5107 if (shamt == 0) 5107 if (shamt == 0)
5108 return (base); 5108 return (base);
5109 else if (shamt == 32) { 5109 else if (shamt == 32) {
5110 ASSIGNC (base & 1); 5110 ASSIGNC (base & 1);
5111 return (0); 5111 return (0);
5112 } 5112 }
5113 else if (shamt > 32) { 5113 else if (shamt > 32) {
5114 CLEARC; 5114 CLEARC;
5115 return (0); 5115 return (0);
5116 } 5116 }
5117 else { 5117 else {
5118 ASSIGNC ((base >> (32 - shamt)) & 1); 5118 ASSIGNC ((base >> (32 - shamt)) & 1);
5119 return (base << shamt); 5119 return (base << shamt);
5120 } 5120 }
5121 case LSR: 5121 case LSR:
5122 if (shamt == 0) 5122 if (shamt == 0)
5123 return (base); 5123 return (base);
5124 else if (shamt == 32) { 5124 else if (shamt == 32) {
5125 ASSIGNC (base >> 31); 5125 ASSIGNC (base >> 31);
5126 return (0); 5126 return (0);
5127 } 5127 }
5128 else if (shamt > 32) { 5128 else if (shamt > 32) {
5129 CLEARC; 5129 CLEARC;
5130 return (0); 5130 return (0);
5131 } 5131 }
5132 else { 5132 else {
5133 ASSIGNC ((base >> (shamt - 1)) & 1); 5133 ASSIGNC ((base >> (shamt - 1)) & 1);
5134 return (base >> shamt); 5134 return (base >> shamt);
5135 } 5135 }
5136 case ASR: 5136 case ASR:
5137 if (shamt == 0) 5137 if (shamt == 0)
5138 return (base); 5138 return (base);
5139 else if (shamt >= 32) { 5139 else if (shamt >= 32) {
5140 ASSIGNC (base >> 31L); 5140 ASSIGNC (base >> 31L);
5141 return ((ARMword) (( int) base >> 31L)); 5141 return ((ARMword) (( int) base >> 31L));
5142 } 5142 }
5143 else { 5143 else {
5144 ASSIGNC ((ARMword) 5144 ASSIGNC ((ARMword)
5145 (( int) base >> 5145 (( int) base >>
5146 (int) (shamt - 1)) & 1); 5146 (int) (shamt - 1)) & 1);
5147 return ((ARMword) 5147 return ((ARMword)
5148 ((int) base >> (int) shamt)); 5148 ((int) base >> (int) shamt));
5149 } 5149 }
5150 case ROR: 5150 case ROR:
5151 if (shamt == 0) 5151 if (shamt == 0)
5152 return (base); 5152 return (base);
5153 shamt &= 0x1f; 5153 shamt &= 0x1f;
5154 if (shamt == 0) { 5154 if (shamt == 0) {
5155 ASSIGNC (base >> 31); 5155 ASSIGNC (base >> 31);
5156 return (base); 5156 return (base);
5157 } 5157 }
5158 else { 5158 else {
5159 ASSIGNC ((base >> (shamt - 1)) & 1); 5159 ASSIGNC ((base >> (shamt - 1)) & 1);
5160 return ((base << (32 - shamt)) | 5160 return ((base << (32 - shamt)) |
5161 (base >> shamt)); 5161 (base >> shamt));
5162 } 5162 }
5163 } 5163 }
5164 } 5164 }
5165 else { 5165 else {
5166 /* Shift amount is a constant. */ 5166 /* Shift amount is a constant. */
5167#ifndef MODE32 5167#ifndef MODE32
5168 if (base == 15) 5168 if (base == 15)
5169 base = ECC | ER15INT | R15PC | EMODE; 5169 base = ECC | ER15INT | R15PC | EMODE;
5170 else 5170 else
5171#endif 5171#endif
5172 base = state->Reg[base]; 5172 base = state->Reg[base];
5173 shamt = BITS (7, 11); 5173 shamt = BITS (7, 11);
5174 5174
5175 switch ((int) BITS (5, 6)) { 5175 switch ((int) BITS (5, 6)) {
5176 case LSL: 5176 case LSL:
5177 ASSIGNC ((base >> (32 - shamt)) & 1); 5177 ASSIGNC ((base >> (32 - shamt)) & 1);
5178 return (base << shamt); 5178 return (base << shamt);
5179 case LSR: 5179 case LSR:
5180 if (shamt == 0) { 5180 if (shamt == 0) {
5181 ASSIGNC (base >> 31); 5181 ASSIGNC (base >> 31);
5182 return (0); 5182 return (0);
5183 } 5183 }
5184 else { 5184 else {
5185 ASSIGNC ((base >> (shamt - 1)) & 1); 5185 ASSIGNC ((base >> (shamt - 1)) & 1);
5186 return (base >> shamt); 5186 return (base >> shamt);
5187 } 5187 }
5188 case ASR: 5188 case ASR:
5189 if (shamt == 0) { 5189 if (shamt == 0) {
5190 ASSIGNC (base >> 31L); 5190 ASSIGNC (base >> 31L);
5191 return ((ARMword) ((int) base >> 31L)); 5191 return ((ARMword) ((int) base >> 31L));
5192 } 5192 }
5193 else { 5193 else {
5194 ASSIGNC ((ARMword) 5194 ASSIGNC ((ARMword)
5195 ((int) base >> 5195 ((int) base >>
5196 (int) (shamt - 1)) & 1); 5196 (int) (shamt - 1)) & 1);
5197 return ((ARMword) 5197 return ((ARMword)
5198 (( int) base >> (int) shamt)); 5198 (( int) base >> (int) shamt));
5199 } 5199 }
5200 case ROR: 5200 case ROR:
5201 if (shamt == 0) { 5201 if (shamt == 0) {
5202 /* It's an RRX. */ 5202 /* It's an RRX. */
5203 shamt = CFLAG; 5203 shamt = CFLAG;
5204 ASSIGNC (base & 1); 5204 ASSIGNC (base & 1);
5205 return ((base >> 1) | (shamt << 31)); 5205 return ((base >> 1) | (shamt << 31));
5206 } 5206 }
5207 else { 5207 else {
5208 ASSIGNC ((base >> (shamt - 1)) & 1); 5208 ASSIGNC ((base >> (shamt - 1)) & 1);
5209 return ((base << (32 - shamt)) | 5209 return ((base << (32 - shamt)) |
5210 (base >> shamt)); 5210 (base >> shamt));
5211 } 5211 }
5212 } 5212 }
5213 } 5213 }
5214 5214
5215 return 0; 5215 return 0;
5216} 5216}
5217 5217
5218/* This routine handles writes to register 15 when the S bit is not set. */ 5218/* This routine handles writes to register 15 when the S bit is not set. */
@@ -5220,26 +5220,26 @@ GetDPSRegRHS (ARMul_State * state, ARMword instr)
5220static void 5220static void
5221WriteR15 (ARMul_State * state, ARMword src) 5221WriteR15 (ARMul_State * state, ARMword src)
5222{ 5222{
5223 /* The ARM documentation states that the two least significant bits 5223 /* The ARM documentation states that the two least significant bits
5224 are discarded when setting PC, except in the cases handled by 5224 are discarded when setting PC, except in the cases handled by
5225 WriteR15Branch() below. It's probably an oversight: in THUMB 5225 WriteR15Branch() below. It's probably an oversight: in THUMB
5226 mode, the second least significant bit should probably not be 5226 mode, the second least significant bit should probably not be
5227 discarded. */ 5227 discarded. */
5228#ifdef MODET 5228#ifdef MODET
5229 if (TFLAG) 5229 if (TFLAG)
5230 src &= 0xfffffffe; 5230 src &= 0xfffffffe;
5231 else 5231 else
5232#endif 5232#endif
5233 src &= 0xfffffffc; 5233 src &= 0xfffffffc;
5234 5234
5235#ifdef MODE32 5235#ifdef MODE32
5236 state->Reg[15] = src & PCBITS; 5236 state->Reg[15] = src & PCBITS;
5237#else 5237#else
5238 state->Reg[15] = (src & R15PCBITS) | ECC | ER15INT | EMODE; 5238 state->Reg[15] = (src & R15PCBITS) | ECC | ER15INT | EMODE;
5239 ARMul_R15Altered (state); 5239 ARMul_R15Altered (state);
5240#endif 5240#endif
5241 5241
5242 FLUSHPIPE; 5242 FLUSHPIPE;
5243} 5243}
5244 5244
5245/* This routine handles writes to register 15 when the S bit is set. */ 5245/* This routine handles writes to register 15 when the S bit is set. */
@@ -5248,35 +5248,35 @@ static void
5248WriteSR15 (ARMul_State * state, ARMword src) 5248WriteSR15 (ARMul_State * state, ARMword src)
5249{ 5249{
5250#ifdef MODE32 5250#ifdef MODE32
5251 if (state->Bank > 0) { 5251 if (state->Bank > 0) {
5252 state->Cpsr = state->Spsr[state->Bank]; 5252 state->Cpsr = state->Spsr[state->Bank];
5253 ARMul_CPSRAltered (state); 5253 ARMul_CPSRAltered (state);
5254 } 5254 }
5255#ifdef MODET 5255#ifdef MODET
5256 if (TFLAG) 5256 if (TFLAG)
5257 src &= 0xfffffffe; 5257 src &= 0xfffffffe;
5258 else 5258 else
5259#endif 5259#endif
5260 src &= 0xfffffffc; 5260 src &= 0xfffffffc;
5261 state->Reg[15] = src & PCBITS; 5261 state->Reg[15] = src & PCBITS;
5262#else 5262#else
5263#ifdef MODET 5263#ifdef MODET
5264 if (TFLAG) 5264 if (TFLAG)
5265 /* ARMul_R15Altered would have to support it. */ 5265 /* ARMul_R15Altered would have to support it. */
5266 abort (); 5266 abort ();
5267 else 5267 else
5268#endif 5268#endif
5269 src &= 0xfffffffc; 5269 src &= 0xfffffffc;
5270 5270
5271 if (state->Bank == USERBANK) 5271 if (state->Bank == USERBANK)
5272 state->Reg[15] = 5272 state->Reg[15] =
5273 (src & (CCBITS | R15PCBITS)) | ER15INT | EMODE; 5273 (src & (CCBITS | R15PCBITS)) | ER15INT | EMODE;
5274 else 5274 else
5275 state->Reg[15] = src; 5275 state->Reg[15] = src;
5276 5276
5277 ARMul_R15Altered (state); 5277 ARMul_R15Altered (state);
5278#endif 5278#endif
5279 FLUSHPIPE; 5279 FLUSHPIPE;
5280} 5280}
5281 5281
5282/* In machines capable of running in Thumb mode, BX, BLX, LDR and LDM 5282/* In machines capable of running in Thumb mode, BX, BLX, LDR and LDM
@@ -5286,19 +5286,19 @@ static void
5286WriteR15Branch (ARMul_State * state, ARMword src) 5286WriteR15Branch (ARMul_State * state, ARMword src)
5287{ 5287{
5288#ifdef MODET 5288#ifdef MODET
5289 if (src & 1) { 5289 if (src & 1) {
5290 /* Thumb bit. */ 5290 /* Thumb bit. */
5291 SETT; 5291 SETT;
5292 state->Reg[15] = src & 0xfffffffe; 5292 state->Reg[15] = src & 0xfffffffe;
5293 } 5293 }
5294 else { 5294 else {
5295 CLEART; 5295 CLEART;
5296 state->Reg[15] = src & 0xfffffffc; 5296 state->Reg[15] = src & 0xfffffffc;
5297 } 5297 }
5298 state->Cpsr = ARMul_GetCPSR (state); 5298 state->Cpsr = ARMul_GetCPSR (state);
5299 FLUSHPIPE; 5299 FLUSHPIPE;
5300#else 5300#else
5301 WriteR15 (state, src); 5301 WriteR15 (state, src);
5302#endif 5302#endif
5303} 5303}
5304 5304
@@ -5309,41 +5309,41 @@ WriteR15Branch (ARMul_State * state, ARMword src)
5309static ARMword 5309static ARMword
5310GetLSRegRHS (ARMul_State * state, ARMword instr) 5310GetLSRegRHS (ARMul_State * state, ARMword instr)
5311{ 5311{
5312 ARMword shamt, base; 5312 ARMword shamt, base;
5313 5313
5314 base = RHSReg; 5314 base = RHSReg;
5315#ifndef MODE32 5315#ifndef MODE32
5316 if (base == 15) 5316 if (base == 15)
5317 /* Now forbidden, but ... */ 5317 /* Now forbidden, but ... */
5318 base = ECC | ER15INT | R15PC | EMODE; 5318 base = ECC | ER15INT | R15PC | EMODE;
5319 else 5319 else
5320#endif 5320#endif
5321 base = state->Reg[base]; 5321 base = state->Reg[base];
5322 5322
5323 shamt = BITS (7, 11); 5323 shamt = BITS (7, 11);
5324 switch ((int) BITS (5, 6)) { 5324 switch ((int) BITS (5, 6)) {
5325 case LSL: 5325 case LSL:
5326 return (base << shamt); 5326 return (base << shamt);
5327 case LSR: 5327 case LSR:
5328 if (shamt == 0) 5328 if (shamt == 0)
5329 return (0); 5329 return (0);
5330 else 5330 else
5331 return (base >> shamt); 5331 return (base >> shamt);
5332 case ASR: 5332 case ASR:
5333 if (shamt == 0) 5333 if (shamt == 0)
5334 return ((ARMword) (( int) base >> 31L)); 5334 return ((ARMword) (( int) base >> 31L));
5335 else 5335 else
5336 return ((ARMword) (( int) base >> (int) shamt)); 5336 return ((ARMword) (( int) base >> (int) shamt));
5337 case ROR: 5337 case ROR:
5338 if (shamt == 0) 5338 if (shamt == 0)
5339 /* It's an RRX. */ 5339 /* It's an RRX. */
5340 return ((base >> 1) | (CFLAG << 31)); 5340 return ((base >> 1) | (CFLAG << 31));
5341 else 5341 else
5342 return ((base << (32 - shamt)) | (base >> shamt)); 5342 return ((base << (32 - shamt)) | (base >> shamt));
5343 default: 5343 default:
5344 break; 5344 break;
5345 } 5345 }
5346 return 0; 5346 return 0;
5347} 5347}
5348 5348
5349/* This routine evaluates the ARM7T halfword and signed transfer RHS's. */ 5349/* This routine evaluates the ARM7T halfword and signed transfer RHS's. */
@@ -5351,62 +5351,62 @@ GetLSRegRHS (ARMul_State * state, ARMword instr)
5351static ARMword 5351static ARMword
5352GetLS7RHS (ARMul_State * state, ARMword instr) 5352GetLS7RHS (ARMul_State * state, ARMword instr)
5353{ 5353{
5354 if (BIT (22) == 0) { 5354 if (BIT (22) == 0) {
5355 /* Register. */ 5355 /* Register. */
5356#ifndef MODE32 5356#ifndef MODE32
5357 if (RHSReg == 15) 5357 if (RHSReg == 15)
5358 /* Now forbidden, but ... */ 5358 /* Now forbidden, but ... */
5359 return ECC | ER15INT | R15PC | EMODE; 5359 return ECC | ER15INT | R15PC | EMODE;
5360#endif 5360#endif
5361 return state->Reg[RHSReg]; 5361 return state->Reg[RHSReg];
5362 } 5362 }
5363 5363
5364 /* Immediate. */ 5364 /* Immediate. */
5365 return BITS (0, 3) | (BITS (8, 11) << 4); 5365 return BITS (0, 3) | (BITS (8, 11) << 4);
5366} 5366}
5367 5367
5368/* This function does the work of loading a word for a LDR instruction. */ 5368/* This function does the work of loading a word for a LDR instruction. */
5369#define MEM_LOAD_LOG(description) if (skyeye_config.log.memlogon >= 1) { \ 5369#define MEM_LOAD_LOG(description) if (skyeye_config.log.memlogon >= 1) { \
5370 fprintf(skyeye_logfd, \ 5370 fprintf(skyeye_logfd, \
5371 "m LOAD %s: N %llx :p %x :i %x :a %x :d %x\n", \ 5371 "m LOAD %s: N %llx :p %x :i %x :a %x :d %x\n", \
5372 description, state->NumInstrs, state->pc, instr, \ 5372 description, state->NumInstrs, state->pc, instr, \
5373 address, dest); \ 5373 address, dest); \
5374 } 5374 }
5375 5375
5376#define MEM_STORE_LOG(description) if (skyeye_config.log.memlogon >= 1) { \ 5376#define MEM_STORE_LOG(description) if (skyeye_config.log.memlogon >= 1) { \
5377 fprintf(skyeye_logfd, \ 5377 fprintf(skyeye_logfd, \
5378 "m STORE %s: N %llx :p %x :i %x :a %x :d %x\n", \ 5378 "m STORE %s: N %llx :p %x :i %x :a %x :d %x\n", \
5379 description, state->NumInstrs, state->pc, instr, \ 5379 description, state->NumInstrs, state->pc, instr, \
5380 address, DEST); \ 5380 address, DEST); \
5381 } 5381 }
5382 5382
5383 5383
5384 5384
5385static unsigned 5385static unsigned
5386LoadWord (ARMul_State * state, ARMword instr, ARMword address) 5386LoadWord (ARMul_State * state, ARMword instr, ARMword address)
5387{ 5387{
5388 ARMword dest; 5388 ARMword dest;
5389 5389
5390 BUSUSEDINCPCS; 5390 BUSUSEDINCPCS;
5391#ifndef MODE32 5391#ifndef MODE32
5392 if (ADDREXCEPT (address)) 5392 if (ADDREXCEPT (address))
5393 INTERNALABORT (address); 5393 INTERNALABORT (address);
5394#endif 5394#endif
5395 5395
5396 dest = ARMul_LoadWordN (state, address); 5396 dest = ARMul_LoadWordN (state, address);
5397 5397
5398 if (state->Aborted) { 5398 if (state->Aborted) {
5399 TAKEABORT; 5399 TAKEABORT;
5400 return state->lateabtSig; 5400 return state->lateabtSig;
5401 } 5401 }
5402 if (address & 3) 5402 if (address & 3)
5403 dest = ARMul_Align (state, address, dest); 5403 dest = ARMul_Align (state, address, dest);
5404 WRITEDESTB (dest); 5404 WRITEDESTB (dest);
5405 ARMul_Icycles (state, 1, 0L); 5405 ARMul_Icycles (state, 1, 0L);
5406 5406
5407 //MEM_LOAD_LOG("WORD"); 5407 //MEM_LOAD_LOG("WORD");
5408 5408
5409 return (DESTReg != LHSReg); 5409 return (DESTReg != LHSReg);
5410} 5410}
5411 5411
5412#ifdef MODET 5412#ifdef MODET
@@ -5414,31 +5414,31 @@ LoadWord (ARMul_State * state, ARMword instr, ARMword address)
5414 5414
5415static unsigned 5415static unsigned
5416LoadHalfWord (ARMul_State * state, ARMword instr, ARMword address, 5416LoadHalfWord (ARMul_State * state, ARMword instr, ARMword address,
5417 int signextend) 5417 int signextend)
5418{ 5418{
5419 ARMword dest; 5419 ARMword dest;
5420 5420
5421 BUSUSEDINCPCS; 5421 BUSUSEDINCPCS;
5422#ifndef MODE32 5422#ifndef MODE32
5423 if (ADDREXCEPT (address)) 5423 if (ADDREXCEPT (address))
5424 INTERNALABORT (address); 5424 INTERNALABORT (address);
5425#endif 5425#endif
5426 dest = ARMul_LoadHalfWord (state, address); 5426 dest = ARMul_LoadHalfWord (state, address);
5427 if (state->Aborted) { 5427 if (state->Aborted) {
5428 TAKEABORT; 5428 TAKEABORT;
5429 return state->lateabtSig; 5429 return state->lateabtSig;
5430 } 5430 }
5431 UNDEF_LSRBPC; 5431 UNDEF_LSRBPC;
5432 if (signextend) 5432 if (signextend)
5433 if (dest & 1 << (16 - 1)) 5433 if (dest & 1 << (16 - 1))
5434 dest = (dest & ((1 << 16) - 1)) - (1 << 16); 5434 dest = (dest & ((1 << 16) - 1)) - (1 << 16);
5435 5435
5436 WRITEDEST (dest); 5436 WRITEDEST (dest);
5437 ARMul_Icycles (state, 1, 0L); 5437 ARMul_Icycles (state, 1, 0L);
5438 5438
5439 //MEM_LOAD_LOG("HALFWORD"); 5439 //MEM_LOAD_LOG("HALFWORD");
5440 5440
5441 return (DESTReg != LHSReg); 5441 return (DESTReg != LHSReg);
5442} 5442}
5443 5443
5444#endif /* MODET */ 5444#endif /* MODET */
@@ -5448,29 +5448,29 @@ LoadHalfWord (ARMul_State * state, ARMword instr, ARMword address,
5448static unsigned 5448static unsigned
5449LoadByte (ARMul_State * state, ARMword instr, ARMword address, int signextend) 5449LoadByte (ARMul_State * state, ARMword instr, ARMword address, int signextend)
5450{ 5450{
5451 ARMword dest; 5451 ARMword dest;
5452 5452
5453 BUSUSEDINCPCS; 5453 BUSUSEDINCPCS;
5454#ifndef MODE32 5454#ifndef MODE32
5455 if (ADDREXCEPT (address)) 5455 if (ADDREXCEPT (address))
5456 INTERNALABORT (address); 5456 INTERNALABORT (address);
5457#endif 5457#endif
5458 dest = ARMul_LoadByte (state, address); 5458 dest = ARMul_LoadByte (state, address);
5459 if (state->Aborted) { 5459 if (state->Aborted) {
5460 TAKEABORT; 5460 TAKEABORT;
5461 return state->lateabtSig; 5461 return state->lateabtSig;
5462 } 5462 }
5463 UNDEF_LSRBPC; 5463 UNDEF_LSRBPC;
5464 if (signextend) 5464 if (signextend)
5465 if (dest & 1 << (8 - 1)) 5465 if (dest & 1 << (8 - 1))
5466 dest = (dest & ((1 << 8) - 1)) - (1 << 8); 5466 dest = (dest & ((1 << 8) - 1)) - (1 << 8);
5467 5467
5468 WRITEDEST (dest); 5468 WRITEDEST (dest);
5469 ARMul_Icycles (state, 1, 0L); 5469 ARMul_Icycles (state, 1, 0L);
5470 5470
5471 //MEM_LOAD_LOG("BYTE"); 5471 //MEM_LOAD_LOG("BYTE");
5472 5472
5473 return (DESTReg != LHSReg); 5473 return (DESTReg != LHSReg);
5474} 5474}
5475 5475
5476/* This function does the work of loading two words for a LDRD instruction. */ 5476/* This function does the work of loading two words for a LDRD instruction. */
@@ -5478,101 +5478,101 @@ LoadByte (ARMul_State * state, ARMword instr, ARMword address, int signextend)
5478static void 5478static void
5479Handle_Load_Double (ARMul_State * state, ARMword instr) 5479Handle_Load_Double (ARMul_State * state, ARMword instr)
5480{ 5480{
5481 ARMword dest_reg; 5481 ARMword dest_reg;
5482 ARMword addr_reg; 5482 ARMword addr_reg;
5483 ARMword write_back = BIT (21); 5483 ARMword write_back = BIT (21);
5484 ARMword immediate = BIT (22); 5484 ARMword immediate = BIT (22);
5485 ARMword add_to_base = BIT (23); 5485 ARMword add_to_base = BIT (23);
5486 ARMword pre_indexed = BIT (24); 5486 ARMword pre_indexed = BIT (24);
5487 ARMword offset; 5487 ARMword offset;
5488 ARMword addr; 5488 ARMword addr;
5489 ARMword sum; 5489 ARMword sum;
5490 ARMword base; 5490 ARMword base;
5491 ARMword value1; 5491 ARMword value1;
5492 ARMword value2; 5492 ARMword value2;
5493 5493
5494 BUSUSEDINCPCS; 5494 BUSUSEDINCPCS;
5495 5495
5496 /* If the writeback bit is set, the pre-index bit must be clear. */ 5496 /* If the writeback bit is set, the pre-index bit must be clear. */
5497 if (write_back && !pre_indexed) { 5497 if (write_back && !pre_indexed) {
5498 ARMul_UndefInstr (state, instr); 5498 ARMul_UndefInstr (state, instr);
5499 return; 5499 return;
5500 } 5500 }
5501 5501
5502 /* Extract the base address register. */ 5502 /* Extract the base address register. */
5503 addr_reg = LHSReg; 5503 addr_reg = LHSReg;
5504 5504
5505 /* Extract the destination register and check it. */ 5505 /* Extract the destination register and check it. */
5506 dest_reg = DESTReg; 5506 dest_reg = DESTReg;
5507 5507
5508 /* Destination register must be even. */ 5508 /* Destination register must be even. */
5509 if ((dest_reg & 1) 5509 if ((dest_reg & 1)
5510 /* Destination register cannot be LR. */ 5510 /* Destination register cannot be LR. */
5511 || (dest_reg == 14)) { 5511 || (dest_reg == 14)) {
5512 ARMul_UndefInstr (state, instr); 5512 ARMul_UndefInstr (state, instr);
5513 return; 5513 return;
5514 } 5514 }
5515 5515
5516 /* Compute the base address. */ 5516 /* Compute the base address. */
5517 base = state->Reg[addr_reg]; 5517 base = state->Reg[addr_reg];
5518 5518
5519 /* Compute the offset. */ 5519 /* Compute the offset. */
5520 offset = immediate ? ((BITS (8, 11) << 4) | BITS (0, 3)) : state-> 5520 offset = immediate ? ((BITS (8, 11) << 4) | BITS (0, 3)) : state->
5521 Reg[RHSReg]; 5521 Reg[RHSReg];
5522 5522
5523 /* Compute the sum of the two. */ 5523 /* Compute the sum of the two. */
5524 if (add_to_base) 5524 if (add_to_base)
5525 sum = base + offset; 5525 sum = base + offset;
5526 else 5526 else
5527 sum = base - offset; 5527 sum = base - offset;
5528 5528
5529 /* If this is a pre-indexed mode use the sum. */ 5529 /* If this is a pre-indexed mode use the sum. */
5530 if (pre_indexed) 5530 if (pre_indexed)
5531 addr = sum; 5531 addr = sum;
5532 else 5532 else
5533 addr = base; 5533 addr = base;
5534 5534
5535 /* The address must be aligned on a 8 byte boundary. */ 5535 /* The address must be aligned on a 8 byte boundary. */
5536 if (addr & 0x7) { 5536 if (addr & 0x7) {
5537#ifdef ABORTS 5537#ifdef ABORTS
5538 ARMul_DATAABORT (addr); 5538 ARMul_DATAABORT (addr);
5539#else 5539#else
5540 ARMul_UndefInstr (state, instr); 5540 ARMul_UndefInstr (state, instr);
5541#endif 5541#endif
5542 return; 5542 return;
5543 } 5543 }
5544 5544
5545 /* For pre indexed or post indexed addressing modes, 5545 /* For pre indexed or post indexed addressing modes,
5546 check that the destination registers do not overlap 5546 check that the destination registers do not overlap
5547 the address registers. */ 5547 the address registers. */
5548 if ((!pre_indexed || write_back) 5548 if ((!pre_indexed || write_back)
5549 && (addr_reg == dest_reg || addr_reg == dest_reg + 1)) { 5549 && (addr_reg == dest_reg || addr_reg == dest_reg + 1)) {
5550 ARMul_UndefInstr (state, instr); 5550 ARMul_UndefInstr (state, instr);
5551 return; 5551 return;
5552 } 5552 }
5553 5553
5554 /* Load the words. */ 5554 /* Load the words. */
5555 value1 = ARMul_LoadWordN (state, addr); 5555 value1 = ARMul_LoadWordN (state, addr);
5556 value2 = ARMul_LoadWordN (state, addr + 4); 5556 value2 = ARMul_LoadWordN (state, addr + 4);
5557 5557
5558 /* Check for data aborts. */ 5558 /* Check for data aborts. */
5559 if (state->Aborted) { 5559 if (state->Aborted) {
5560 TAKEABORT; 5560 TAKEABORT;
5561 return; 5561 return;
5562 } 5562 }
5563 5563
5564 ARMul_Icycles (state, 2, 0L); 5564 ARMul_Icycles (state, 2, 0L);
5565 5565
5566 /* Store the values. */ 5566 /* Store the values. */
5567 state->Reg[dest_reg] = value1; 5567 state->Reg[dest_reg] = value1;
5568 state->Reg[dest_reg + 1] = value2; 5568 state->Reg[dest_reg + 1] = value2;
5569 5569
5570 /* Do the post addressing and writeback. */ 5570 /* Do the post addressing and writeback. */
5571 if (!pre_indexed) 5571 if (!pre_indexed)
5572 addr = sum; 5572 addr = sum;
5573 5573
5574 if (!pre_indexed || write_back) 5574 if (!pre_indexed || write_back)
5575 state->Reg[addr_reg] = addr; 5575 state->Reg[addr_reg] = addr;
5576} 5576}
5577 5577
5578/* This function does the work of storing two words for a STRD instruction. */ 5578/* This function does the work of storing two words for a STRD instruction. */
@@ -5580,96 +5580,96 @@ Handle_Load_Double (ARMul_State * state, ARMword instr)
5580static void 5580static void
5581Handle_Store_Double (ARMul_State * state, ARMword instr) 5581Handle_Store_Double (ARMul_State * state, ARMword instr)
5582{ 5582{
5583 ARMword src_reg; 5583 ARMword src_reg;
5584 ARMword addr_reg; 5584 ARMword addr_reg;
5585 ARMword write_back = BIT (21); 5585 ARMword write_back = BIT (21);
5586 ARMword immediate = BIT (22); 5586 ARMword immediate = BIT (22);
5587 ARMword add_to_base = BIT (23); 5587 ARMword add_to_base = BIT (23);
5588 ARMword pre_indexed = BIT (24); 5588 ARMword pre_indexed = BIT (24);
5589 ARMword offset; 5589 ARMword offset;
5590 ARMword addr; 5590 ARMword addr;
5591 ARMword sum; 5591 ARMword sum;
5592 ARMword base; 5592 ARMword base;
5593 5593
5594 BUSUSEDINCPCS; 5594 BUSUSEDINCPCS;
5595 5595
5596 /* If the writeback bit is set, the pre-index bit must be clear. */ 5596 /* If the writeback bit is set, the pre-index bit must be clear. */
5597 if (write_back && !pre_indexed) { 5597 if (write_back && !pre_indexed) {
5598 ARMul_UndefInstr (state, instr); 5598 ARMul_UndefInstr (state, instr);
5599 return; 5599 return;
5600 } 5600 }
5601 5601
5602 /* Extract the base address register. */ 5602 /* Extract the base address register. */
5603 addr_reg = LHSReg; 5603 addr_reg = LHSReg;
5604 5604
5605 /* Base register cannot be PC. */ 5605 /* Base register cannot be PC. */
5606 if (addr_reg == 15) { 5606 if (addr_reg == 15) {
5607 ARMul_UndefInstr (state, instr); 5607 ARMul_UndefInstr (state, instr);
5608 return; 5608 return;
5609 } 5609 }
5610 5610
5611 /* Extract the source register. */ 5611 /* Extract the source register. */
5612 src_reg = DESTReg; 5612 src_reg = DESTReg;
5613 5613
5614 /* Source register must be even. */ 5614 /* Source register must be even. */
5615 if (src_reg & 1) { 5615 if (src_reg & 1) {
5616 ARMul_UndefInstr (state, instr); 5616 ARMul_UndefInstr (state, instr);
5617 return; 5617 return;
5618 } 5618 }
5619 5619
5620 /* Compute the base address. */ 5620 /* Compute the base address. */
5621 base = state->Reg[addr_reg]; 5621 base = state->Reg[addr_reg];
5622 5622
5623 /* Compute the offset. */ 5623 /* Compute the offset. */
5624 offset = immediate ? ((BITS (8, 11) << 4) | BITS (0, 3)) : state-> 5624 offset = immediate ? ((BITS (8, 11) << 4) | BITS (0, 3)) : state->
5625 Reg[RHSReg]; 5625 Reg[RHSReg];
5626 5626
5627 /* Compute the sum of the two. */ 5627 /* Compute the sum of the two. */
5628 if (add_to_base) 5628 if (add_to_base)
5629 sum = base + offset; 5629 sum = base + offset;
5630 else 5630 else
5631 sum = base - offset; 5631 sum = base - offset;
5632 5632
5633 /* If this is a pre-indexed mode use the sum. */ 5633 /* If this is a pre-indexed mode use the sum. */
5634 if (pre_indexed) 5634 if (pre_indexed)
5635 addr = sum; 5635 addr = sum;
5636 else 5636 else
5637 addr = base; 5637 addr = base;
5638 5638
5639 /* The address must be aligned on a 8 byte boundary. */ 5639 /* The address must be aligned on a 8 byte boundary. */
5640 if (addr & 0x7) { 5640 if (addr & 0x7) {
5641#ifdef ABORTS 5641#ifdef ABORTS
5642 ARMul_DATAABORT (addr); 5642 ARMul_DATAABORT (addr);
5643#else 5643#else
5644 ARMul_UndefInstr (state, instr); 5644 ARMul_UndefInstr (state, instr);
5645#endif 5645#endif
5646 return; 5646 return;
5647 } 5647 }
5648 5648
5649 /* For pre indexed or post indexed addressing modes, 5649 /* For pre indexed or post indexed addressing modes,
5650 check that the destination registers do not overlap 5650 check that the destination registers do not overlap
5651 the address registers. */ 5651 the address registers. */
5652 if ((!pre_indexed || write_back) 5652 if ((!pre_indexed || write_back)
5653 && (addr_reg == src_reg || addr_reg == src_reg + 1)) { 5653 && (addr_reg == src_reg || addr_reg == src_reg + 1)) {
5654 ARMul_UndefInstr (state, instr); 5654 ARMul_UndefInstr (state, instr);
5655 return; 5655 return;
5656 } 5656 }
5657 5657
5658 /* Load the words. */ 5658 /* Load the words. */
5659 ARMul_StoreWordN (state, addr, state->Reg[src_reg]); 5659 ARMul_StoreWordN (state, addr, state->Reg[src_reg]);
5660 ARMul_StoreWordN (state, addr + 4, state->Reg[src_reg + 1]); 5660 ARMul_StoreWordN (state, addr + 4, state->Reg[src_reg + 1]);
5661 5661
5662 if (state->Aborted) { 5662 if (state->Aborted) {
5663 TAKEABORT; 5663 TAKEABORT;
5664 return; 5664 return;
5665 } 5665 }
5666 5666
5667 /* Do the post addressing and writeback. */ 5667 /* Do the post addressing and writeback. */
5668 if (!pre_indexed) 5668 if (!pre_indexed)
5669 addr = sum; 5669 addr = sum;
5670 5670
5671 if (!pre_indexed || write_back) 5671 if (!pre_indexed || write_back)
5672 state->Reg[addr_reg] = addr; 5672 state->Reg[addr_reg] = addr;
5673} 5673}
5674 5674
5675/* This function does the work of storing a word from a STR instruction. */ 5675/* This function does the work of storing a word from a STR instruction. */
@@ -5677,29 +5677,29 @@ Handle_Store_Double (ARMul_State * state, ARMword instr)
5677static unsigned 5677static unsigned
5678StoreWord (ARMul_State * state, ARMword instr, ARMword address) 5678StoreWord (ARMul_State * state, ARMword instr, ARMword address)
5679{ 5679{
5680 //MEM_STORE_LOG("WORD"); 5680 //MEM_STORE_LOG("WORD");
5681 5681
5682 BUSUSEDINCPCN; 5682 BUSUSEDINCPCN;
5683#ifndef MODE32 5683#ifndef MODE32
5684 if (DESTReg == 15) 5684 if (DESTReg == 15)
5685 state->Reg[15] = ECC | ER15INT | R15PC | EMODE; 5685 state->Reg[15] = ECC | ER15INT | R15PC | EMODE;
5686#endif 5686#endif
5687#ifdef MODE32 5687#ifdef MODE32
5688 ARMul_StoreWordN (state, address, DEST); 5688 ARMul_StoreWordN (state, address, DEST);
5689#else 5689#else
5690 if (VECTORACCESS (address) || ADDREXCEPT (address)) { 5690 if (VECTORACCESS (address) || ADDREXCEPT (address)) {
5691 INTERNALABORT (address); 5691 INTERNALABORT (address);
5692 (void) ARMul_LoadWordN (state, address); 5692 (void) ARMul_LoadWordN (state, address);
5693 } 5693 }
5694 else 5694 else
5695 ARMul_StoreWordN (state, address, DEST); 5695 ARMul_StoreWordN (state, address, DEST);
5696#endif 5696#endif
5697 if (state->Aborted) { 5697 if (state->Aborted) {
5698 TAKEABORT; 5698 TAKEABORT;
5699 return state->lateabtSig; 5699 return state->lateabtSig;
5700 } 5700 }
5701 5701
5702 return TRUE; 5702 return TRUE;
5703} 5703}
5704 5704
5705#ifdef MODET 5705#ifdef MODET
@@ -5708,31 +5708,31 @@ StoreWord (ARMul_State * state, ARMword instr, ARMword address)
5708static unsigned 5708static unsigned
5709StoreHalfWord (ARMul_State * state, ARMword instr, ARMword address) 5709StoreHalfWord (ARMul_State * state, ARMword instr, ARMword address)
5710{ 5710{
5711 //MEM_STORE_LOG("HALFWORD"); 5711 //MEM_STORE_LOG("HALFWORD");
5712 5712
5713 BUSUSEDINCPCN; 5713 BUSUSEDINCPCN;
5714 5714
5715#ifndef MODE32 5715#ifndef MODE32
5716 if (DESTReg == 15) 5716 if (DESTReg == 15)
5717 state->Reg[15] = ECC | ER15INT | R15PC | EMODE; 5717 state->Reg[15] = ECC | ER15INT | R15PC | EMODE;
5718#endif 5718#endif
5719 5719
5720#ifdef MODE32 5720#ifdef MODE32
5721 ARMul_StoreHalfWord (state, address, DEST); 5721 ARMul_StoreHalfWord (state, address, DEST);
5722#else 5722#else
5723 if (VECTORACCESS (address) || ADDREXCEPT (address)) { 5723 if (VECTORACCESS (address) || ADDREXCEPT (address)) {
5724 INTERNALABORT (address); 5724 INTERNALABORT (address);
5725 (void) ARMul_LoadHalfWord (state, address); 5725 (void) ARMul_LoadHalfWord (state, address);
5726 } 5726 }
5727 else 5727 else
5728 ARMul_StoreHalfWord (state, address, DEST); 5728 ARMul_StoreHalfWord (state, address, DEST);
5729#endif 5729#endif
5730 5730
5731 if (state->Aborted) { 5731 if (state->Aborted) {
5732 TAKEABORT; 5732 TAKEABORT;
5733 return state->lateabtSig; 5733 return state->lateabtSig;
5734 } 5734 }
5735 return TRUE; 5735 return TRUE;
5736} 5736}
5737 5737
5738#endif /* MODET */ 5738#endif /* MODET */
@@ -5742,29 +5742,29 @@ StoreHalfWord (ARMul_State * state, ARMword instr, ARMword address)
5742static unsigned 5742static unsigned
5743StoreByte (ARMul_State * state, ARMword instr, ARMword address) 5743StoreByte (ARMul_State * state, ARMword instr, ARMword address)
5744{ 5744{
5745 //MEM_STORE_LOG("BYTE"); 5745 //MEM_STORE_LOG("BYTE");
5746 5746
5747 BUSUSEDINCPCN; 5747 BUSUSEDINCPCN;
5748#ifndef MODE32 5748#ifndef MODE32
5749 if (DESTReg == 15) 5749 if (DESTReg == 15)
5750 state->Reg[15] = ECC | ER15INT | R15PC | EMODE; 5750 state->Reg[15] = ECC | ER15INT | R15PC | EMODE;
5751#endif 5751#endif
5752#ifdef MODE32 5752#ifdef MODE32
5753 ARMul_StoreByte (state, address, DEST); 5753 ARMul_StoreByte (state, address, DEST);
5754#else 5754#else
5755 if (VECTORACCESS (address) || ADDREXCEPT (address)) { 5755 if (VECTORACCESS (address) || ADDREXCEPT (address)) {
5756 INTERNALABORT (address); 5756 INTERNALABORT (address);
5757 (void) ARMul_LoadByte (state, address); 5757 (void) ARMul_LoadByte (state, address);
5758 } 5758 }
5759 else 5759 else
5760 ARMul_StoreByte (state, address, DEST); 5760 ARMul_StoreByte (state, address, DEST);
5761#endif 5761#endif
5762 if (state->Aborted) { 5762 if (state->Aborted) {
5763 TAKEABORT; 5763 TAKEABORT;
5764 return state->lateabtSig; 5764 return state->lateabtSig;
5765 } 5765 }
5766 //UNDEF_LSRBPC; 5766 //UNDEF_LSRBPC;
5767 return TRUE; 5767 return TRUE;
5768} 5768}
5769 5769
5770/* This function does the work of loading the registers listed in an LDM 5770/* This function does the work of loading the registers listed in an LDM
@@ -5775,60 +5775,60 @@ StoreByte (ARMul_State * state, ARMword instr, ARMword address)
5775static void 5775static void
5776LoadMult (ARMul_State * state, ARMword instr, ARMword address, ARMword WBBase) 5776LoadMult (ARMul_State * state, ARMword instr, ARMword address, ARMword WBBase)
5777{ 5777{
5778 ARMword dest, temp; 5778 ARMword dest, temp;
5779 5779
5780 //UNDEF_LSMNoRegs; 5780 //UNDEF_LSMNoRegs;
5781 //UNDEF_LSMPCBase; 5781 //UNDEF_LSMPCBase;
5782 //UNDEF_LSMBaseInListWb; 5782 //UNDEF_LSMBaseInListWb;
5783 BUSUSEDINCPCS; 5783 BUSUSEDINCPCS;
5784#ifndef MODE32 5784#ifndef MODE32
5785 if (ADDREXCEPT (address)) 5785 if (ADDREXCEPT (address))
5786 INTERNALABORT (address); 5786 INTERNALABORT (address);
5787#endif 5787#endif
5788/*chy 2004-05-23 may write twice 5788/*chy 2004-05-23 may write twice
5789 if (BIT (21) && LHSReg != 15) 5789 if (BIT (21) && LHSReg != 15)
5790 LSBase = WBBase; 5790 LSBase = WBBase;
5791*/ 5791*/
5792 /* N cycle first. */ 5792 /* N cycle first. */
5793 for (temp = 0; !BIT (temp); temp++); 5793 for (temp = 0; !BIT (temp); temp++);
5794 5794
5795 dest = ARMul_LoadWordN (state, address); 5795 dest = ARMul_LoadWordN (state, address);
5796 5796
5797 if (!state->abortSig && !state->Aborted) 5797 if (!state->abortSig && !state->Aborted)
5798 state->Reg[temp++] = dest; 5798 state->Reg[temp++] = dest;
5799 else if (!state->Aborted) { 5799 else if (!state->Aborted) {
5800 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); 5800 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address);
5801 state->Aborted = ARMul_DataAbortV; 5801 state->Aborted = ARMul_DataAbortV;
5802 } 5802 }
5803/*chy 2004-05-23 chy goto end*/ 5803/*chy 2004-05-23 chy goto end*/
5804 if (state->Aborted) 5804 if (state->Aborted)
5805 goto L_ldm_makeabort; 5805 goto L_ldm_makeabort;
5806 /* S cycles from here on. */ 5806 /* S cycles from here on. */
5807 for (; temp < 16; temp++) 5807 for (; temp < 16; temp++)
5808 if (BIT (temp)) { 5808 if (BIT (temp)) {
5809 /* Load this register. */ 5809 /* Load this register. */
5810 address += 4; 5810 address += 4;
5811 dest = ARMul_LoadWordS (state, address); 5811 dest = ARMul_LoadWordS (state, address);
5812 5812
5813 if (!state->abortSig && !state->Aborted) 5813 if (!state->abortSig && !state->Aborted)
5814 state->Reg[temp] = dest; 5814 state->Reg[temp] = dest;
5815 else if (!state->Aborted) { 5815 else if (!state->Aborted) {
5816 XScale_set_fsr_far (state, 5816 XScale_set_fsr_far (state,
5817 ARMul_CP15_R5_ST_ALIGN, 5817 ARMul_CP15_R5_ST_ALIGN,
5818 address); 5818 address);
5819 state->Aborted = ARMul_DataAbortV; 5819 state->Aborted = ARMul_DataAbortV;
5820 } 5820 }
5821 /*chy 2004-05-23 chy goto end */ 5821 /*chy 2004-05-23 chy goto end */
5822 if (state->Aborted) 5822 if (state->Aborted)
5823 goto L_ldm_makeabort; 5823 goto L_ldm_makeabort;
5824 5824
5825 } 5825 }
5826 5826
5827 if (BIT (15) && !state->Aborted) 5827 if (BIT (15) && !state->Aborted)
5828 /* PC is in the reg list. */ 5828 /* PC is in the reg list. */
5829 WriteR15Branch (state, PC); 5829 WriteR15Branch (state, PC);
5830 5830
5831 /* To write back the final register. */ 5831 /* To write back the final register. */
5832/* ARMul_Icycles (state, 1, 0L);*/ 5832/* ARMul_Icycles (state, 1, 0L);*/
5833/*chy 2004-05-23, see below 5833/*chy 2004-05-23, see below
5834 if (state->Aborted) 5834 if (state->Aborted)
@@ -5841,31 +5841,31 @@ LoadMult (ARMul_State * state, ARMword instr, ARMword address, ARMword WBBase)
5841*/ 5841*/
5842/*chy 2004-05-23 should compare the Abort Models*/ 5842/*chy 2004-05-23 should compare the Abort Models*/
5843 L_ldm_makeabort: 5843 L_ldm_makeabort:
5844 /* To write back the final register. */ 5844 /* To write back the final register. */
5845 ARMul_Icycles (state, 1, 0L); 5845 ARMul_Icycles (state, 1, 0L);
5846 5846
5847 /* chy 2005-11-24, bug found by benjl@cse.unsw.edu.au, etc */ 5847 /* chy 2005-11-24, bug found by benjl@cse.unsw.edu.au, etc */
5848 /* 5848 /*
5849 if (state->Aborted) 5849 if (state->Aborted)
5850 { 5850 {
5851 if (BIT (21) && LHSReg != 15) 5851 if (BIT (21) && LHSReg != 15)
5852 if (!(state->abortSig && state->Aborted && state->lateabtSig == LOW)) 5852 if (!(state->abortSig && state->Aborted && state->lateabtSig == LOW))
5853 LSBase = WBBase; 5853 LSBase = WBBase;
5854 TAKEABORT; 5854 TAKEABORT;
5855 }else if (BIT (21) && LHSReg != 15) 5855 }else if (BIT (21) && LHSReg != 15)
5856 LSBase = WBBase; 5856 LSBase = WBBase;
5857 */ 5857 */
5858 if (state->Aborted) { 5858 if (state->Aborted) {
5859 if (BIT (21) && LHSReg != 15) { 5859 if (BIT (21) && LHSReg != 15) {
5860 if (!(state->abortSig)) { 5860 if (!(state->abortSig)) {
5861 } 5861 }
5862 } 5862 }
5863 TAKEABORT; 5863 TAKEABORT;
5864 } 5864 }
5865 else if (BIT (21) && LHSReg != 15) { 5865 else if (BIT (21) && LHSReg != 15) {
5866 LSBase = WBBase; 5866 LSBase = WBBase;
5867 } 5867 }
5868 /* chy 2005-11-24, over */ 5868 /* chy 2005-11-24, over */
5869 5869
5870} 5870}
5871 5871
@@ -5876,114 +5876,114 @@ LoadMult (ARMul_State * state, ARMword instr, ARMword address, ARMword WBBase)
5876 5876
5877static void 5877static void
5878LoadSMult (ARMul_State * state, 5878LoadSMult (ARMul_State * state,
5879 ARMword instr, ARMword address, ARMword WBBase) 5879 ARMword instr, ARMword address, ARMword WBBase)
5880{ 5880{
5881 ARMword dest, temp; 5881 ARMword dest, temp;
5882 5882
5883 //UNDEF_LSMNoRegs; 5883 //UNDEF_LSMNoRegs;
5884 //UNDEF_LSMPCBase; 5884 //UNDEF_LSMPCBase;
5885 //UNDEF_LSMBaseInListWb; 5885 //UNDEF_LSMBaseInListWb;
5886 5886
5887 BUSUSEDINCPCS; 5887 BUSUSEDINCPCS;
5888 5888
5889#ifndef MODE32 5889#ifndef MODE32
5890 if (ADDREXCEPT (address)) 5890 if (ADDREXCEPT (address))
5891 INTERNALABORT (address); 5891 INTERNALABORT (address);
5892#endif 5892#endif
5893/* chy 2004-05-23, may write twice 5893/* chy 2004-05-23, may write twice
5894 if (BIT (21) && LHSReg != 15) 5894 if (BIT (21) && LHSReg != 15)
5895 LSBase = WBBase; 5895 LSBase = WBBase;
5896*/ 5896*/
5897 if (!BIT (15) && state->Bank != USERBANK) { 5897 if (!BIT (15) && state->Bank != USERBANK) {
5898 /* Temporary reg bank switch. */ 5898 /* Temporary reg bank switch. */
5899 (void) ARMul_SwitchMode (state, state->Mode, USER26MODE); 5899 (void) ARMul_SwitchMode (state, state->Mode, USER26MODE);
5900 UNDEF_LSMUserBankWb; 5900 UNDEF_LSMUserBankWb;
5901 } 5901 }
5902 5902
5903 /* N cycle first. */ 5903 /* N cycle first. */
5904 for (temp = 0; !BIT (temp); temp++); 5904 for (temp = 0; !BIT (temp); temp++);
5905 5905
5906 dest = ARMul_LoadWordN (state, address); 5906 dest = ARMul_LoadWordN (state, address);
5907 5907
5908 if (!state->abortSig) 5908 if (!state->abortSig)
5909 state->Reg[temp++] = dest; 5909 state->Reg[temp++] = dest;
5910 else if (!state->Aborted) { 5910 else if (!state->Aborted) {
5911 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); 5911 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address);
5912 state->Aborted = ARMul_DataAbortV; 5912 state->Aborted = ARMul_DataAbortV;
5913 } 5913 }
5914 5914
5915/*chy 2004-05-23 chy goto end*/ 5915/*chy 2004-05-23 chy goto end*/
5916 if (state->Aborted) 5916 if (state->Aborted)
5917 goto L_ldm_s_makeabort; 5917 goto L_ldm_s_makeabort;
5918 /* S cycles from here on. */ 5918 /* S cycles from here on. */
5919 for (; temp < 16; temp++) 5919 for (; temp < 16; temp++)
5920 if (BIT (temp)) { 5920 if (BIT (temp)) {
5921 /* Load this register. */ 5921 /* Load this register. */
5922 address += 4; 5922 address += 4;
5923 dest = ARMul_LoadWordS (state, address); 5923 dest = ARMul_LoadWordS (state, address);
5924 5924
5925 if (!state->abortSig && !state->Aborted) 5925 if (!state->abortSig && !state->Aborted)
5926 state->Reg[temp] = dest; 5926 state->Reg[temp] = dest;
5927 else if (!state->Aborted) { 5927 else if (!state->Aborted) {
5928 XScale_set_fsr_far (state, 5928 XScale_set_fsr_far (state,
5929 ARMul_CP15_R5_ST_ALIGN, 5929 ARMul_CP15_R5_ST_ALIGN,
5930 address); 5930 address);
5931 state->Aborted = ARMul_DataAbortV; 5931 state->Aborted = ARMul_DataAbortV;
5932 } 5932 }
5933 /*chy 2004-05-23 chy goto end */ 5933 /*chy 2004-05-23 chy goto end */
5934 if (state->Aborted) 5934 if (state->Aborted)
5935 goto L_ldm_s_makeabort; 5935 goto L_ldm_s_makeabort;
5936 } 5936 }
5937 5937
5938/*chy 2004-05-23 label of ldm_s_makeabort*/ 5938/*chy 2004-05-23 label of ldm_s_makeabort*/
5939 L_ldm_s_makeabort: 5939 L_ldm_s_makeabort:
5940/*chy 2004-06-06 LSBase process should be here, not in the end of this function. Because ARMul_CPSRAltered maybe change R13(SP) R14(lr). If not, simulate INSTR ldmia sp!,[....pc]^ error.*/ 5940/*chy 2004-06-06 LSBase process should be here, not in the end of this function. Because ARMul_CPSRAltered maybe change R13(SP) R14(lr). If not, simulate INSTR ldmia sp!,[....pc]^ error.*/
5941/*chy 2004-05-23 should compare the Abort Models*/ 5941/*chy 2004-05-23 should compare the Abort Models*/
5942 if (state->Aborted) { 5942 if (state->Aborted) {
5943 if (BIT (21) && LHSReg != 15) 5943 if (BIT (21) && LHSReg != 15)
5944 if (! 5944 if (!
5945 (state->abortSig && state->Aborted 5945 (state->abortSig && state->Aborted
5946 && state->lateabtSig == LOW)) 5946 && state->lateabtSig == LOW))
5947 LSBase = WBBase; 5947 LSBase = WBBase;
5948 TAKEABORT; 5948 TAKEABORT;
5949 } 5949 }
5950 else if (BIT (21) && LHSReg != 15) 5950 else if (BIT (21) && LHSReg != 15)
5951 LSBase = WBBase; 5951 LSBase = WBBase;
5952 5952
5953 if (BIT (15) && !state->Aborted) { 5953 if (BIT (15) && !state->Aborted) {
5954 /* PC is in the reg list. */ 5954 /* PC is in the reg list. */
5955#ifdef MODE32 5955#ifdef MODE32
5956 //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode 5956 //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode
5957 if (state->Mode != USER26MODE && state->Mode != USER32MODE ){ 5957 if (state->Mode != USER26MODE && state->Mode != USER32MODE ){
5958 state->Cpsr = GETSPSR (state->Bank); 5958 state->Cpsr = GETSPSR (state->Bank);
5959 ARMul_CPSRAltered (state); 5959 ARMul_CPSRAltered (state);
5960 } 5960 }
5961 5961
5962 WriteR15 (state, PC); 5962 WriteR15 (state, PC);
5963#else 5963#else
5964 //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode 5964 //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode
5965 if (state->Mode == USER26MODE || state->Mode == USER32MODE ) { 5965 if (state->Mode == USER26MODE || state->Mode == USER32MODE ) {
5966 /* Protect bits in user mode. */ 5966 /* Protect bits in user mode. */
5967 ASSIGNN ((state->Reg[15] & NBIT) != 0); 5967 ASSIGNN ((state->Reg[15] & NBIT) != 0);
5968 ASSIGNZ ((state->Reg[15] & ZBIT) != 0); 5968 ASSIGNZ ((state->Reg[15] & ZBIT) != 0);
5969 ASSIGNC ((state->Reg[15] & CBIT) != 0); 5969 ASSIGNC ((state->Reg[15] & CBIT) != 0);
5970 ASSIGNV ((state->Reg[15] & VBIT) != 0); 5970 ASSIGNV ((state->Reg[15] & VBIT) != 0);
5971 } 5971 }
5972 else 5972 else
5973 ARMul_R15Altered (state); 5973 ARMul_R15Altered (state);
5974 5974
5975 FLUSHPIPE; 5975 FLUSHPIPE;
5976#endif 5976#endif
5977 } 5977 }
5978 5978
5979 //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode 5979 //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode
5980 if (!BIT (15) && state->Mode != USER26MODE 5980 if (!BIT (15) && state->Mode != USER26MODE
5981 && state->Mode != USER32MODE ) 5981 && state->Mode != USER32MODE )
5982 /* Restore the correct bank. */ 5982 /* Restore the correct bank. */
5983 (void) ARMul_SwitchMode (state, USER26MODE, state->Mode); 5983 (void) ARMul_SwitchMode (state, USER26MODE, state->Mode);
5984 5984
5985 /* To write back the final register. */ 5985 /* To write back the final register. */
5986 ARMul_Icycles (state, 1, 0L); 5986 ARMul_Icycles (state, 1, 0L);
5987/* chy 2004-05-23, see below 5987/* chy 2004-05-23, see below
5988 if (state->Aborted) 5988 if (state->Aborted)
5989 { 5989 {
@@ -6002,91 +6002,91 @@ LoadSMult (ARMul_State * state,
6002 6002
6003static void 6003static void
6004StoreMult (ARMul_State * state, 6004StoreMult (ARMul_State * state,
6005 ARMword instr, ARMword address, ARMword WBBase) 6005 ARMword instr, ARMword address, ARMword WBBase)
6006{ 6006{
6007 ARMword temp; 6007 ARMword temp;
6008 6008
6009 UNDEF_LSMNoRegs; 6009 UNDEF_LSMNoRegs;
6010 UNDEF_LSMPCBase; 6010 UNDEF_LSMPCBase;
6011 UNDEF_LSMBaseInListWb; 6011 UNDEF_LSMBaseInListWb;
6012 6012
6013 if (!TFLAG) 6013 if (!TFLAG)
6014 /* N-cycle, increment the PC and update the NextInstr state. */ 6014 /* N-cycle, increment the PC and update the NextInstr state. */
6015 BUSUSEDINCPCN; 6015 BUSUSEDINCPCN;
6016 6016
6017#ifndef MODE32 6017#ifndef MODE32
6018 if (VECTORACCESS (address) || ADDREXCEPT (address)) 6018 if (VECTORACCESS (address) || ADDREXCEPT (address))
6019 INTERNALABORT (address); 6019 INTERNALABORT (address);
6020 6020
6021 if (BIT (15)) 6021 if (BIT (15))
6022 PATCHR15; 6022 PATCHR15;
6023#endif 6023#endif
6024 6024
6025 /* N cycle first. */ 6025 /* N cycle first. */
6026 for (temp = 0; !BIT (temp); temp++); 6026 for (temp = 0; !BIT (temp); temp++);
6027 6027
6028#ifdef MODE32 6028#ifdef MODE32
6029 ARMul_StoreWordN (state, address, state->Reg[temp++]); 6029 ARMul_StoreWordN (state, address, state->Reg[temp++]);
6030#else 6030#else
6031 if (state->Aborted) { 6031 if (state->Aborted) {
6032 (void) ARMul_LoadWordN (state, address); 6032 (void) ARMul_LoadWordN (state, address);
6033 6033
6034 /* Fake the Stores as Loads. */ 6034 /* Fake the Stores as Loads. */
6035 for (; temp < 16; temp++) 6035 for (; temp < 16; temp++)
6036 if (BIT (temp)) { 6036 if (BIT (temp)) {
6037 /* Save this register. */ 6037 /* Save this register. */
6038 address += 4; 6038 address += 4;
6039 (void) ARMul_LoadWordS (state, address); 6039 (void) ARMul_LoadWordS (state, address);
6040 } 6040 }
6041 6041
6042 if (BIT (21) && LHSReg != 15) 6042 if (BIT (21) && LHSReg != 15)
6043 LSBase = WBBase; 6043 LSBase = WBBase;
6044 TAKEABORT; 6044 TAKEABORT;
6045 return; 6045 return;
6046 } 6046 }
6047 else 6047 else
6048 ARMul_StoreWordN (state, address, state->Reg[temp++]); 6048 ARMul_StoreWordN (state, address, state->Reg[temp++]);
6049#endif 6049#endif
6050 6050
6051 if (state->abortSig && !state->Aborted) { 6051 if (state->abortSig && !state->Aborted) {
6052 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); 6052 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address);
6053 state->Aborted = ARMul_DataAbortV; 6053 state->Aborted = ARMul_DataAbortV;
6054 } 6054 }
6055 6055
6056//chy 2004-05-23, needn't store other when aborted 6056//chy 2004-05-23, needn't store other when aborted
6057 if (state->Aborted) 6057 if (state->Aborted)
6058 goto L_stm_takeabort; 6058 goto L_stm_takeabort;
6059 6059
6060 /* S cycles from here on. */ 6060 /* S cycles from here on. */
6061 for (; temp < 16; temp++) 6061 for (; temp < 16; temp++)
6062 if (BIT (temp)) { 6062 if (BIT (temp)) {
6063 /* Save this register. */ 6063 /* Save this register. */
6064 address += 4; 6064 address += 4;
6065 6065
6066 ARMul_StoreWordS (state, address, state->Reg[temp]); 6066 ARMul_StoreWordS (state, address, state->Reg[temp]);
6067 6067
6068 if (state->abortSig && !state->Aborted) { 6068 if (state->abortSig && !state->Aborted) {
6069 XScale_set_fsr_far (state, 6069 XScale_set_fsr_far (state,
6070 ARMul_CP15_R5_ST_ALIGN, 6070 ARMul_CP15_R5_ST_ALIGN,
6071 address); 6071 address);
6072 state->Aborted = ARMul_DataAbortV; 6072 state->Aborted = ARMul_DataAbortV;
6073 } 6073 }
6074 //chy 2004-05-23, needn't store other when aborted 6074 //chy 2004-05-23, needn't store other when aborted
6075 if (state->Aborted) 6075 if (state->Aborted)
6076 goto L_stm_takeabort; 6076 goto L_stm_takeabort;
6077 6077
6078 } 6078 }
6079 6079
6080//chy 2004-05-23,should compare the Abort Models 6080//chy 2004-05-23,should compare the Abort Models
6081 L_stm_takeabort: 6081 L_stm_takeabort:
6082 if (BIT (21) && LHSReg != 15) { 6082 if (BIT (21) && LHSReg != 15) {
6083 if (! 6083 if (!
6084 (state->abortSig && state->Aborted 6084 (state->abortSig && state->Aborted
6085 && state->lateabtSig == LOW)) 6085 && state->lateabtSig == LOW))
6086 LSBase = WBBase; 6086 LSBase = WBBase;
6087 } 6087 }
6088 if (state->Aborted) 6088 if (state->Aborted)
6089 TAKEABORT; 6089 TAKEABORT;
6090} 6090}
6091 6091
6092/* This function does the work of storing the registers listed in an STM 6092/* This function does the work of storing the registers listed in an STM
@@ -6096,101 +6096,101 @@ StoreMult (ARMul_State * state,
6096 6096
6097static void 6097static void
6098StoreSMult (ARMul_State * state, 6098StoreSMult (ARMul_State * state,
6099 ARMword instr, ARMword address, ARMword WBBase) 6099 ARMword instr, ARMword address, ARMword WBBase)
6100{ 6100{
6101 ARMword temp; 6101 ARMword temp;
6102 6102
6103 UNDEF_LSMNoRegs; 6103 UNDEF_LSMNoRegs;
6104 UNDEF_LSMPCBase; 6104 UNDEF_LSMPCBase;
6105 UNDEF_LSMBaseInListWb; 6105 UNDEF_LSMBaseInListWb;
6106 6106
6107 BUSUSEDINCPCN; 6107 BUSUSEDINCPCN;
6108 6108
6109#ifndef MODE32 6109#ifndef MODE32
6110 if (VECTORACCESS (address) || ADDREXCEPT (address)) 6110 if (VECTORACCESS (address) || ADDREXCEPT (address))
6111 INTERNALABORT (address); 6111 INTERNALABORT (address);
6112 6112
6113 if (BIT (15)) 6113 if (BIT (15))
6114 PATCHR15; 6114 PATCHR15;
6115#endif 6115#endif
6116 6116
6117 if (state->Bank != USERBANK) { 6117 if (state->Bank != USERBANK) {
6118 /* Force User Bank. */ 6118 /* Force User Bank. */
6119 (void) ARMul_SwitchMode (state, state->Mode, USER26MODE); 6119 (void) ARMul_SwitchMode (state, state->Mode, USER26MODE);
6120 UNDEF_LSMUserBankWb; 6120 UNDEF_LSMUserBankWb;
6121 } 6121 }
6122 6122
6123 for (temp = 0; !BIT (temp); temp++); /* N cycle first. */ 6123 for (temp = 0; !BIT (temp); temp++); /* N cycle first. */
6124 6124
6125#ifdef MODE32 6125#ifdef MODE32
6126 ARMul_StoreWordN (state, address, state->Reg[temp++]); 6126 ARMul_StoreWordN (state, address, state->Reg[temp++]);
6127#else 6127#else
6128 if (state->Aborted) { 6128 if (state->Aborted) {
6129 (void) ARMul_LoadWordN (state, address); 6129 (void) ARMul_LoadWordN (state, address);
6130 6130
6131 for (; temp < 16; temp++) 6131 for (; temp < 16; temp++)
6132 /* Fake the Stores as Loads. */ 6132 /* Fake the Stores as Loads. */
6133 if (BIT (temp)) { 6133 if (BIT (temp)) {
6134 /* Save this register. */ 6134 /* Save this register. */
6135 address += 4; 6135 address += 4;
6136 6136
6137 (void) ARMul_LoadWordS (state, address); 6137 (void) ARMul_LoadWordS (state, address);
6138 } 6138 }
6139 6139
6140 if (BIT (21) && LHSReg != 15) 6140 if (BIT (21) && LHSReg != 15)
6141 LSBase = WBBase; 6141 LSBase = WBBase;
6142 6142
6143 TAKEABORT; 6143 TAKEABORT;
6144 return; 6144 return;
6145 } 6145 }
6146 else 6146 else
6147 ARMul_StoreWordN (state, address, state->Reg[temp++]); 6147 ARMul_StoreWordN (state, address, state->Reg[temp++]);
6148#endif 6148#endif
6149 6149
6150 if (state->abortSig && !state->Aborted) { 6150 if (state->abortSig && !state->Aborted) {
6151 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); 6151 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address);
6152 state->Aborted = ARMul_DataAbortV; 6152 state->Aborted = ARMul_DataAbortV;
6153 } 6153 }
6154 6154
6155//chy 2004-05-23, needn't store other when aborted 6155//chy 2004-05-23, needn't store other when aborted
6156 if (state->Aborted) 6156 if (state->Aborted)
6157 goto L_stm_s_takeabort; 6157 goto L_stm_s_takeabort;
6158 /* S cycles from here on. */ 6158 /* S cycles from here on. */
6159 for (; temp < 16; temp++) 6159 for (; temp < 16; temp++)
6160 if (BIT (temp)) { 6160 if (BIT (temp)) {
6161 /* Save this register. */ 6161 /* Save this register. */
6162 address += 4; 6162 address += 4;
6163 6163
6164 ARMul_StoreWordS (state, address, state->Reg[temp]); 6164 ARMul_StoreWordS (state, address, state->Reg[temp]);
6165 6165
6166 if (state->abortSig && !state->Aborted) { 6166 if (state->abortSig && !state->Aborted) {
6167 XScale_set_fsr_far (state, 6167 XScale_set_fsr_far (state,
6168 ARMul_CP15_R5_ST_ALIGN, 6168 ARMul_CP15_R5_ST_ALIGN,
6169 address); 6169 address);
6170 state->Aborted = ARMul_DataAbortV; 6170 state->Aborted = ARMul_DataAbortV;
6171 } 6171 }
6172 //chy 2004-05-23, needn't store other when aborted 6172 //chy 2004-05-23, needn't store other when aborted
6173 if (state->Aborted) 6173 if (state->Aborted)
6174 goto L_stm_s_takeabort; 6174 goto L_stm_s_takeabort;
6175 } 6175 }
6176 6176
6177 //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode 6177 //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode
6178 if (state->Mode != USER26MODE && state->Mode != USER32MODE ) 6178 if (state->Mode != USER26MODE && state->Mode != USER32MODE )
6179 /* Restore the correct bank. */ 6179 /* Restore the correct bank. */
6180 (void) ARMul_SwitchMode (state, USER26MODE, state->Mode); 6180 (void) ARMul_SwitchMode (state, USER26MODE, state->Mode);
6181 6181
6182 6182
6183//chy 2004-05-23,should compare the Abort Models 6183//chy 2004-05-23,should compare the Abort Models
6184 L_stm_s_takeabort: 6184 L_stm_s_takeabort:
6185 if (BIT (21) && LHSReg != 15) { 6185 if (BIT (21) && LHSReg != 15) {
6186 if (! 6186 if (!
6187 (state->abortSig && state->Aborted 6187 (state->abortSig && state->Aborted
6188 && state->lateabtSig == LOW)) 6188 && state->lateabtSig == LOW))
6189 LSBase = WBBase; 6189 LSBase = WBBase;
6190 } 6190 }
6191 6191
6192 if (state->Aborted) 6192 if (state->Aborted)
6193 TAKEABORT; 6193 TAKEABORT;
6194} 6194}
6195 6195
6196/* This function does the work of adding two 32bit values 6196/* This function does the work of adding two 32bit values
@@ -6199,18 +6199,18 @@ StoreSMult (ARMul_State * state,
6199static ARMword 6199static ARMword
6200Add32 (ARMword a1, ARMword a2, int *carry) 6200Add32 (ARMword a1, ARMword a2, int *carry)
6201{ 6201{
6202 ARMword result = (a1 + a2); 6202 ARMword result = (a1 + a2);
6203 unsigned int uresult = (unsigned int) result; 6203 unsigned int uresult = (unsigned int) result;
6204 unsigned int ua1 = (unsigned int) a1; 6204 unsigned int ua1 = (unsigned int) a1;
6205 6205
6206 /* If (result == RdLo) and (state->Reg[nRdLo] == 0), 6206 /* If (result == RdLo) and (state->Reg[nRdLo] == 0),
6207 or (result > RdLo) then we have no carry. */ 6207 or (result > RdLo) then we have no carry. */
6208 if ((uresult == ua1) ? (a2 != 0) : (uresult < ua1)) 6208 if ((uresult == ua1) ? (a2 != 0) : (uresult < ua1))
6209 *carry = 1; 6209 *carry = 1;
6210 else 6210 else
6211 *carry = 0; 6211 *carry = 0;
6212 6212
6213 return result; 6213 return result;
6214} 6214}
6215 6215
6216/* This function does the work of multiplying 6216/* This function does the work of multiplying
@@ -6219,97 +6219,97 @@ Add32 (ARMword a1, ARMword a2, int *carry)
6219static unsigned 6219static unsigned
6220Multiply64 (ARMul_State * state, ARMword instr, int msigned, int scc) 6220Multiply64 (ARMul_State * state, ARMword instr, int msigned, int scc)
6221{ 6221{
6222 /* Operand register numbers. */ 6222 /* Operand register numbers. */
6223 int nRdHi, nRdLo, nRs, nRm; 6223 int nRdHi, nRdLo, nRs, nRm;
6224 ARMword RdHi = 0, RdLo = 0, Rm; 6224 ARMword RdHi = 0, RdLo = 0, Rm;
6225 /* Cycle count. */ 6225 /* Cycle count. */
6226 int scount; 6226 int scount;
6227 6227
6228 nRdHi = BITS (16, 19); 6228 nRdHi = BITS (16, 19);
6229 nRdLo = BITS (12, 15); 6229 nRdLo = BITS (12, 15);
6230 nRs = BITS (8, 11); 6230 nRs = BITS (8, 11);
6231 nRm = BITS (0, 3); 6231 nRm = BITS (0, 3);
6232 6232
6233 /* Needed to calculate the cycle count. */ 6233 /* Needed to calculate the cycle count. */
6234 Rm = state->Reg[nRm]; 6234 Rm = state->Reg[nRm];
6235 6235
6236 /* Check for illegal operand combinations first. */ 6236 /* Check for illegal operand combinations first. */
6237 if (nRdHi != 15 6237 if (nRdHi != 15
6238 && nRdLo != 15 6238 && nRdLo != 15
6239 && nRs != 15 6239 && nRs != 15
6240 //&& nRm != 15 && nRdHi != nRdLo && nRdHi != nRm && nRdLo != nRm) { 6240 //&& nRm != 15 && nRdHi != nRdLo && nRdHi != nRm && nRdLo != nRm) {
6241 && nRm != 15 && nRdHi != nRdLo ) { 6241 && nRm != 15 && nRdHi != nRdLo ) {
6242 /* Intermediate results. */ 6242 /* Intermediate results. */
6243 ARMword lo, mid1, mid2, hi; 6243 ARMword lo, mid1, mid2, hi;
6244 int carry; 6244 int carry;
6245 ARMword Rs = state->Reg[nRs]; 6245 ARMword Rs = state->Reg[nRs];
6246 int sign = 0; 6246 int sign = 0;
6247 6247
6248 if (msigned) { 6248 if (msigned) {
6249 /* Compute sign of result and adjust operands if necessary. */ 6249 /* Compute sign of result and adjust operands if necessary. */
6250 sign = (Rm ^ Rs) & 0x80000000; 6250 sign = (Rm ^ Rs) & 0x80000000;
6251 6251
6252 if (((signed int) Rm) < 0) 6252 if (((signed int) Rm) < 0)
6253 Rm = -Rm; 6253 Rm = -Rm;
6254 6254
6255 if (((signed int) Rs) < 0) 6255 if (((signed int) Rs) < 0)
6256 Rs = -Rs; 6256 Rs = -Rs;
6257 } 6257 }
6258 6258
6259 /* We can split the 32x32 into four 16x16 operations. This 6259 /* We can split the 32x32 into four 16x16 operations. This
6260 ensures that we do not lose precision on 32bit only hosts. */ 6260 ensures that we do not lose precision on 32bit only hosts. */
6261 lo = ((Rs & 0xFFFF) * (Rm & 0xFFFF)); 6261 lo = ((Rs & 0xFFFF) * (Rm & 0xFFFF));
6262 mid1 = ((Rs & 0xFFFF) * ((Rm >> 16) & 0xFFFF)); 6262 mid1 = ((Rs & 0xFFFF) * ((Rm >> 16) & 0xFFFF));
6263 mid2 = (((Rs >> 16) & 0xFFFF) * (Rm & 0xFFFF)); 6263 mid2 = (((Rs >> 16) & 0xFFFF) * (Rm & 0xFFFF));
6264 hi = (((Rs >> 16) & 0xFFFF) * ((Rm >> 16) & 0xFFFF)); 6264 hi = (((Rs >> 16) & 0xFFFF) * ((Rm >> 16) & 0xFFFF));
6265 6265
6266 /* We now need to add all of these results together, taking 6266 /* We now need to add all of these results together, taking
6267 care to propogate the carries from the additions. */ 6267 care to propogate the carries from the additions. */
6268 RdLo = Add32 (lo, (mid1 << 16), &carry); 6268 RdLo = Add32 (lo, (mid1 << 16), &carry);
6269 RdHi = carry; 6269 RdHi = carry;
6270 RdLo = Add32 (RdLo, (mid2 << 16), &carry); 6270 RdLo = Add32 (RdLo, (mid2 << 16), &carry);
6271 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + 6271 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) +
6272 ((mid2 >> 16) & 0xFFFF) + hi); 6272 ((mid2 >> 16) & 0xFFFF) + hi);
6273 6273
6274 if (sign) { 6274 if (sign) {
6275 /* Negate result if necessary. */ 6275 /* Negate result if necessary. */
6276 RdLo = ~RdLo; 6276 RdLo = ~RdLo;
6277 RdHi = ~RdHi; 6277 RdHi = ~RdHi;
6278 if (RdLo == 0xFFFFFFFF) { 6278 if (RdLo == 0xFFFFFFFF) {
6279 RdLo = 0; 6279 RdLo = 0;
6280 RdHi += 1; 6280 RdHi += 1;
6281 } 6281 }
6282 else 6282 else
6283 RdLo += 1; 6283 RdLo += 1;
6284 } 6284 }
6285 6285
6286 state->Reg[nRdLo] = RdLo; 6286 state->Reg[nRdLo] = RdLo;
6287 state->Reg[nRdHi] = RdHi; 6287 state->Reg[nRdHi] = RdHi;
6288 } 6288 }
6289 else{ 6289 else{
6290 fprintf (stderr, "sim: MULTIPLY64 - INVALID ARGUMENTS, instr=0x%x\n", instr); 6290 fprintf (stderr, "sim: MULTIPLY64 - INVALID ARGUMENTS, instr=0x%x\n", instr);
6291 } 6291 }
6292 if (scc) 6292 if (scc)
6293 /* Ensure that both RdHi and RdLo are used to compute Z, 6293 /* Ensure that both RdHi and RdLo are used to compute Z,
6294 but don't let RdLo's sign bit make it to N. */ 6294 but don't let RdLo's sign bit make it to N. */
6295 ARMul_NegZero (state, RdHi | (RdLo >> 16) | (RdLo & 0xFFFF)); 6295 ARMul_NegZero (state, RdHi | (RdLo >> 16) | (RdLo & 0xFFFF));
6296 6296
6297 /* The cycle count depends on whether the instruction is a signed or 6297 /* The cycle count depends on whether the instruction is a signed or
6298 unsigned multiply, and what bits are clear in the multiplier. */ 6298 unsigned multiply, and what bits are clear in the multiplier. */
6299 if (msigned && (Rm & ((unsigned) 1 << 31))) 6299 if (msigned && (Rm & ((unsigned) 1 << 31)))
6300 /* Invert the bits to make the check against zero. */ 6300 /* Invert the bits to make the check against zero. */
6301 Rm = ~Rm; 6301 Rm = ~Rm;
6302 6302
6303 if ((Rm & 0xFFFFFF00) == 0) 6303 if ((Rm & 0xFFFFFF00) == 0)
6304 scount = 1; 6304 scount = 1;
6305 else if ((Rm & 0xFFFF0000) == 0) 6305 else if ((Rm & 0xFFFF0000) == 0)
6306 scount = 2; 6306 scount = 2;
6307 else if ((Rm & 0xFF000000) == 0) 6307 else if ((Rm & 0xFF000000) == 0)
6308 scount = 3; 6308 scount = 3;
6309 else 6309 else
6310 scount = 4; 6310 scount = 4;
6311 6311
6312 return 2 + scount; 6312 return 2 + scount;
6313} 6313}
6314 6314
6315/* This function does the work of multiplying two 32bit 6315/* This function does the work of multiplying two 32bit
@@ -6318,32 +6318,32 @@ Multiply64 (ARMul_State * state, ARMword instr, int msigned, int scc)
6318static unsigned 6318static unsigned
6319MultiplyAdd64 (ARMul_State * state, ARMword instr, int msigned, int scc) 6319MultiplyAdd64 (ARMul_State * state, ARMword instr, int msigned, int scc)
6320{ 6320{
6321 unsigned scount; 6321 unsigned scount;
6322 ARMword RdLo, RdHi; 6322 ARMword RdLo, RdHi;
6323 int nRdHi, nRdLo; 6323 int nRdHi, nRdLo;
6324 int carry = 0; 6324 int carry = 0;
6325 6325
6326 nRdHi = BITS (16, 19); 6326 nRdHi = BITS (16, 19);
6327 nRdLo = BITS (12, 15); 6327 nRdLo = BITS (12, 15);
6328 6328
6329 RdHi = state->Reg[nRdHi]; 6329 RdHi = state->Reg[nRdHi];
6330 RdLo = state->Reg[nRdLo]; 6330 RdLo = state->Reg[nRdLo];
6331 6331
6332 scount = Multiply64 (state, instr, msigned, LDEFAULT); 6332 scount = Multiply64 (state, instr, msigned, LDEFAULT);
6333 6333
6334 RdLo = Add32 (RdLo, state->Reg[nRdLo], &carry); 6334 RdLo = Add32 (RdLo, state->Reg[nRdLo], &carry);
6335 RdHi = (RdHi + state->Reg[nRdHi]) + carry; 6335 RdHi = (RdHi + state->Reg[nRdHi]) + carry;
6336 6336
6337 state->Reg[nRdLo] = RdLo; 6337 state->Reg[nRdLo] = RdLo;
6338 state->Reg[nRdHi] = RdHi; 6338 state->Reg[nRdHi] = RdHi;
6339 6339
6340 if (scc) 6340 if (scc)
6341 /* Ensure that both RdHi and RdLo are used to compute Z, 6341 /* Ensure that both RdHi and RdLo are used to compute Z,
6342 but don't let RdLo's sign bit make it to N. */ 6342 but don't let RdLo's sign bit make it to N. */
6343 ARMul_NegZero (state, RdHi | (RdLo >> 16) | (RdLo & 0xFFFF)); 6343 ARMul_NegZero (state, RdHi | (RdLo >> 16) | (RdLo & 0xFFFF));
6344 6344
6345 /* Extra cycle for addition. */ 6345 /* Extra cycle for addition. */
6346 return scount + 1; 6346 return scount + 1;
6347} 6347}
6348 6348
6349/* Attempt to emulate an ARMv6 instruction. 6349/* Attempt to emulate an ARMv6 instruction.
@@ -6392,231 +6392,231 @@ handle_v6_insn (ARMul_State * state, ARMword instr)
6392 6392
6393/* add new instr for arm v6. */ 6393/* add new instr for arm v6. */
6394 ARMword lhs, temp; 6394 ARMword lhs, temp;
6395 case 0x18: /* ORR reg */ 6395 case 0x18: /* ORR reg */
6396 { 6396 {
6397 /* dyf add armv6 instr strex 2010.9.17 */ 6397 /* dyf add armv6 instr strex 2010.9.17 */
6398 if (BITS (4, 7) == 0x9) { 6398 if (BITS (4, 7) == 0x9) {
6399 lhs = LHS; 6399 lhs = LHS;
6400 ARMul_StoreWordS(state, lhs, RHS); 6400 ARMul_StoreWordS(state, lhs, RHS);
6401 //StoreWord(state, lhs, RHS) 6401 //StoreWord(state, lhs, RHS)
6402 if (state->Aborted) { 6402 if (state->Aborted) {
6403 TAKEABORT; 6403 TAKEABORT;
6404 } 6404 }
6405 6405
6406 return 1; 6406 return 1;
6407 } 6407 }
6408 break; 6408 break;
6409 } 6409 }
6410 6410
6411 case 0x19: /* orrs reg */ 6411 case 0x19: /* orrs reg */
6412 { 6412 {
6413 /* dyf add armv6 instr ldrex */ 6413 /* dyf add armv6 instr ldrex */
6414 if (BITS (4, 7) == 0x9) { 6414 if (BITS (4, 7) == 0x9) {
6415 lhs = LHS; 6415 lhs = LHS;
6416 LoadWord (state, instr, lhs); 6416 LoadWord (state, instr, lhs);
6417 return 1; 6417 return 1;
6418 } 6418 }
6419 break; 6419 break;
6420 } 6420 }
6421 6421
6422 case 0x1c: /* BIC reg */ 6422 case 0x1c: /* BIC reg */
6423 { 6423 {
6424 /* dyf add for STREXB */ 6424 /* dyf add for STREXB */
6425 if (BITS (4, 7) == 0x9) { 6425 if (BITS (4, 7) == 0x9) {
6426 lhs = LHS; 6426 lhs = LHS;
6427 ARMul_StoreByte (state, lhs, RHS); 6427 ARMul_StoreByte (state, lhs, RHS);
6428 BUSUSEDINCPCN; 6428 BUSUSEDINCPCN;
6429 if (state->Aborted) { 6429 if (state->Aborted) {
6430 TAKEABORT; 6430 TAKEABORT;
6431 } 6431 }
6432 6432
6433 //printf("In %s, strexb not implemented\n", __FUNCTION__); 6433 //printf("In %s, strexb not implemented\n", __FUNCTION__);
6434 UNDEF_LSRBPC; 6434 UNDEF_LSRBPC;
6435 /* WRITESDEST (dest); */ 6435 /* WRITESDEST (dest); */
6436 return 1; 6436 return 1;
6437 } 6437 }
6438 break; 6438 break;
6439 } 6439 }
6440 6440
6441 case 0x1d: /* BICS reg */ 6441 case 0x1d: /* BICS reg */
6442 { 6442 {
6443 if ((BITS (4, 7)) == 0x9) { 6443 if ((BITS (4, 7)) == 0x9) {
6444 /* ldrexb */ 6444 /* ldrexb */
6445 temp = LHS; 6445 temp = LHS;
6446 LoadByte (state, instr, temp, LUNSIGNED); 6446 LoadByte (state, instr, temp, LUNSIGNED);
6447 //state->Reg[BITS(12, 15)] = ARMul_LoadByte(state, state->Reg[BITS(16, 19)]); 6447 //state->Reg[BITS(12, 15)] = ARMul_LoadByte(state, state->Reg[BITS(16, 19)]);
6448 //printf("ldrexb\n"); 6448 //printf("ldrexb\n");
6449 //printf("instr is %x rm is %d\n", instr, BITS(16, 19)); 6449 //printf("instr is %x rm is %d\n", instr, BITS(16, 19));
6450 //exit(-1); 6450 //exit(-1);
6451 6451
6452 //printf("In %s, ldrexb not implemented\n", __FUNCTION__); 6452 //printf("In %s, ldrexb not implemented\n", __FUNCTION__);
6453 return 1; 6453 return 1;
6454 } 6454 }
6455 break; 6455 break;
6456 } 6456 }
6457/* add end */ 6457/* add end */
6458 6458
6459 case 0x6a: 6459 case 0x6a:
6460 { 6460 {
6461 ARMword Rm; 6461 ARMword Rm;
6462 int ror = -1; 6462 int ror = -1;
6463 6463
6464 switch (BITS (4, 11)) 6464 switch (BITS (4, 11))
6465 { 6465 {
6466 case 0x07: ror = 0; break; 6466 case 0x07: ror = 0; break;
6467 case 0x47: ror = 8; break; 6467 case 0x47: ror = 8; break;
6468 case 0x87: ror = 16; break; 6468 case 0x87: ror = 16; break;
6469 case 0xc7: ror = 24; break; 6469 case 0xc7: ror = 24; break;
6470 6470
6471 case 0x01: 6471 case 0x01:
6472 case 0xf3: 6472 case 0xf3:
6473 printf ("Unhandled v6 insn: ssat\n"); 6473 printf ("Unhandled v6 insn: ssat\n");
6474 return 0; 6474 return 0;
6475 default: 6475 default:
6476 break; 6476 break;
6477 } 6477 }
6478 6478
6479 if (ror == -1) 6479 if (ror == -1)
6480 { 6480 {
6481 if (BITS (4, 6) == 0x7) 6481 if (BITS (4, 6) == 0x7)
6482 { 6482 {
6483 printf ("Unhandled v6 insn: ssat\n"); 6483 printf ("Unhandled v6 insn: ssat\n");
6484 return 0; 6484 return 0;
6485 } 6485 }
6486 break; 6486 break;
6487 } 6487 }
6488 6488
6489 Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFF); 6489 Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFF);
6490 if (Rm & 0x80) 6490 if (Rm & 0x80)
6491 Rm |= 0xffffff00; 6491 Rm |= 0xffffff00;
6492 6492
6493 if (BITS (16, 19) == 0xf) 6493 if (BITS (16, 19) == 0xf)
6494 /* SXTB */ 6494 /* SXTB */
6495 state->Reg[BITS (12, 15)] = Rm; 6495 state->Reg[BITS (12, 15)] = Rm;
6496 else 6496 else
6497 /* SXTAB */ 6497 /* SXTAB */
6498 state->Reg[BITS (12, 15)] += Rm; 6498 state->Reg[BITS (12, 15)] += Rm;
6499 } 6499 }
6500 return 1; 6500 return 1;
6501 6501
6502 case 0x6b: 6502 case 0x6b:
6503 { 6503 {
6504 ARMword Rm; 6504 ARMword Rm;
6505 int ror = -1; 6505 int ror = -1;
6506 6506
6507 switch (BITS (4, 11)) 6507 switch (BITS (4, 11))
6508 { 6508 {
6509 case 0x07: ror = 0; break; 6509 case 0x07: ror = 0; break;
6510 case 0x47: ror = 8; break; 6510 case 0x47: ror = 8; break;
6511 case 0x87: ror = 16; break; 6511 case 0x87: ror = 16; break;
6512 case 0xc7: ror = 24; break; 6512 case 0xc7: ror = 24; break;
6513 6513
6514 case 0xf3: 6514 case 0xf3:
6515 DEST = ((RHS & 0xFF) << 24) | ((RHS & 0xFF00)) << 8 | ((RHS & 0xFF0000) >> 8) | ((RHS & 0xFF000000) >> 24); 6515 DEST = ((RHS & 0xFF) << 24) | ((RHS & 0xFF00)) << 8 | ((RHS & 0xFF0000) >> 8) | ((RHS & 0xFF000000) >> 24);
6516 return 1; 6516 return 1;
6517 case 0xfb: 6517 case 0xfb:
6518 DEST = ((RHS & 0xFF) << 8) | ((RHS & 0xFF00)) >> 8 | ((RHS & 0xFF0000) << 8) | ((RHS & 0xFF000000) >> 8); 6518 DEST = ((RHS & 0xFF) << 8) | ((RHS & 0xFF00)) >> 8 | ((RHS & 0xFF0000) << 8) | ((RHS & 0xFF000000) >> 8);
6519 return 1; 6519 return 1;
6520 default: 6520 default:
6521 break; 6521 break;
6522 } 6522 }
6523 6523
6524 if (ror == -1) 6524 if (ror == -1)
6525 break; 6525 break;
6526 6526
6527 Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFFFF); 6527 Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFFFF);
6528 if (Rm & 0x8000) 6528 if (Rm & 0x8000)
6529 Rm |= 0xffff0000; 6529 Rm |= 0xffff0000;
6530 6530
6531 if (BITS (16, 19) == 0xf) 6531 if (BITS (16, 19) == 0xf)
6532 /* SXTH */ 6532 /* SXTH */
6533 state->Reg[BITS (12, 15)] = Rm; 6533 state->Reg[BITS (12, 15)] = Rm;
6534 else 6534 else
6535 /* SXTAH */ 6535 /* SXTAH */
6536 state->Reg[BITS (12, 15)] = state->Reg[BITS (16, 19)] + Rm; 6536 state->Reg[BITS (12, 15)] = state->Reg[BITS (16, 19)] + Rm;
6537 } 6537 }
6538 return 1; 6538 return 1;
6539 6539
6540 case 0x6e: 6540 case 0x6e:
6541 { 6541 {
6542 ARMword Rm; 6542 ARMword Rm;
6543 int ror = -1; 6543 int ror = -1;
6544 6544
6545 switch (BITS (4, 11)) 6545 switch (BITS (4, 11))
6546 { 6546 {
6547 case 0x07: ror = 0; break; 6547 case 0x07: ror = 0; break;
6548 case 0x47: ror = 8; break; 6548 case 0x47: ror = 8; break;
6549 case 0x87: ror = 16; break; 6549 case 0x87: ror = 16; break;
6550 case 0xc7: ror = 24; break; 6550 case 0xc7: ror = 24; break;
6551 6551
6552 case 0x01: 6552 case 0x01:
6553 case 0xf3: 6553 case 0xf3:
6554 printf ("Unhandled v6 insn: usat\n"); 6554 printf ("Unhandled v6 insn: usat\n");
6555 return 0; 6555 return 0;
6556 default: 6556 default:
6557 break; 6557 break;
6558 } 6558 }
6559 6559
6560 if (ror == -1) 6560 if (ror == -1)
6561 { 6561 {
6562 if (BITS (4, 6) == 0x7) 6562 if (BITS (4, 6) == 0x7)
6563 { 6563 {
6564 printf ("Unhandled v6 insn: usat\n"); 6564 printf ("Unhandled v6 insn: usat\n");
6565 return 0; 6565 return 0;
6566 } 6566 }
6567 break; 6567 break;
6568 } 6568 }
6569 6569
6570 Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFF); 6570 Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFF);
6571 6571
6572 if (BITS (16, 19) == 0xf) 6572 if (BITS (16, 19) == 0xf)
6573 /* UXTB */ 6573 /* UXTB */
6574 state->Reg[BITS (12, 15)] = Rm; 6574 state->Reg[BITS (12, 15)] = Rm;
6575 else 6575 else
6576 /* UXTAB */ 6576 /* UXTAB */
6577 state->Reg[BITS (12, 15)] = state->Reg[BITS (16, 19)] + Rm; 6577 state->Reg[BITS (12, 15)] = state->Reg[BITS (16, 19)] + Rm;
6578 } 6578 }
6579 return 1; 6579 return 1;
6580 6580
6581 case 0x6f: 6581 case 0x6f:
6582 { 6582 {
6583 ARMword Rm; 6583 ARMword Rm;
6584 int ror = -1; 6584 int ror = -1;
6585 6585
6586 switch (BITS (4, 11)) 6586 switch (BITS (4, 11))
6587 { 6587 {
6588 case 0x07: ror = 0; break; 6588 case 0x07: ror = 0; break;
6589 case 0x47: ror = 8; break; 6589 case 0x47: ror = 8; break;
6590 case 0x87: ror = 16; break; 6590 case 0x87: ror = 16; break;
6591 case 0xc7: ror = 24; break; 6591 case 0xc7: ror = 24; break;
6592 6592
6593 case 0xfb: 6593 case 0xfb:
6594 printf ("Unhandled v6 insn: revsh\n"); 6594 printf ("Unhandled v6 insn: revsh\n");
6595 return 0; 6595 return 0;
6596 default: 6596 default:
6597 break; 6597 break;
6598 } 6598 }
6599 6599
6600 if (ror == -1) 6600 if (ror == -1)
6601 break; 6601 break;
6602 6602
6603 Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFFFF); 6603 Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFFFF);
6604 6604
6605 /* UXT */ 6605 /* UXT */
6606 /* state->Reg[BITS (12, 15)] = Rm; */ 6606 /* state->Reg[BITS (12, 15)] = Rm; */
6607 /* dyf add */ 6607 /* dyf add */
6608 if (BITS (16, 19) == 0xf) { 6608 if (BITS (16, 19) == 0xf) {
6609 state->Reg[BITS (12, 15)] = (Rm >> (8 * BITS(10, 11))) & 0x0000FFFF; 6609 state->Reg[BITS (12, 15)] = (Rm >> (8 * BITS(10, 11))) & 0x0000FFFF;
6610 } else { 6610 } else {
6611 /* UXTAH */ 6611 /* UXTAH */
6612 /* state->Reg[BITS (12, 15)] = state->Reg [BITS (16, 19)] + Rm; */ 6612 /* state->Reg[BITS (12, 15)] = state->Reg [BITS (16, 19)] + Rm; */
6613// printf("rd is %x rn is %x rm is %x rotate is %x\n", state->Reg[BITS (12, 15)], state->Reg[BITS (16, 19)] 6613// printf("rd is %x rn is %x rm is %x rotate is %x\n", state->Reg[BITS (12, 15)], state->Reg[BITS (16, 19)]
6614// , Rm, BITS(10, 11)); 6614// , Rm, BITS(10, 11));
6615// printf("icounter is %lld\n", state->NumInstrs); 6615// printf("icounter is %lld\n", state->NumInstrs);
6616 state->Reg[BITS (12, 15)] = (state->Reg[BITS (16, 19)] >> (8 * (BITS(10, 11)))) + Rm; 6616 state->Reg[BITS (12, 15)] = (state->Reg[BITS (16, 19)] >> (8 * (BITS(10, 11)))) + Rm;
6617// printf("rd is %x\n", state->Reg[BITS (12, 15)]); 6617// printf("rd is %x\n", state->Reg[BITS (12, 15)]);
6618// exit(-1); 6618// exit(-1);
6619 } 6619 }
6620 } 6620 }
6621 return 1; 6621 return 1;
6622 6622
diff --git a/src/core/src/arm/mmu/arm1176jzf_s_mmu.cpp b/src/core/src/arm/mmu/arm1176jzf_s_mmu.cpp
index d45925c53..a6a4aeffd 100644
--- a/src/core/src/arm/mmu/arm1176jzf_s_mmu.cpp
+++ b/src/core/src/arm/mmu/arm1176jzf_s_mmu.cpp
@@ -33,76 +33,76 @@
33#define ASID 255 33#define ASID 255
34static uint32_t tlb_entry_array[TLB_SIZE][ASID]; 34static uint32_t tlb_entry_array[TLB_SIZE][ASID];
35static inline void invalidate_all_tlb(ARMul_State *state){ 35static inline void invalidate_all_tlb(ARMul_State *state){
36 memset(&tlb_entry_array[0], 0xFF, sizeof(uint32_t) * TLB_SIZE * ASID); 36 memset(&tlb_entry_array[0], 0xFF, sizeof(uint32_t) * TLB_SIZE * ASID);
37} 37}
38static inline void invalidate_by_mva(ARMul_State *state, ARMword va){ 38static inline void invalidate_by_mva(ARMul_State *state, ARMword va){
39 memset(&tlb_entry_array[va >> 12][va & 0xFF], 0xFF, sizeof(uint32_t)); 39 memset(&tlb_entry_array[va >> 12][va & 0xFF], 0xFF, sizeof(uint32_t));
40 return; 40 return;
41} 41}
42static inline void invalidate_by_asid(ARMul_State *state, ARMword asid){ 42static inline void invalidate_by_asid(ARMul_State *state, ARMword asid){
43 int i; 43 int i;
44 for(i = 0; i < TLB_SIZE; i++) 44 for(i = 0; i < TLB_SIZE; i++)
45 memset(&tlb_entry_array[i][asid & 0xFF], 0xFF, sizeof(uint32_t)); 45 memset(&tlb_entry_array[i][asid & 0xFF], 0xFF, sizeof(uint32_t));
46 return; 46 return;
47} 47}
48 48
49static uint32_t get_phys_page(ARMul_State* state, ARMword va){ 49static uint32_t get_phys_page(ARMul_State* state, ARMword va){
50 uint32_t phys_page = tlb_entry_array[va >> 12][state->mmu.context_id & 0xFF]; 50 uint32_t phys_page = tlb_entry_array[va >> 12][state->mmu.context_id & 0xFF];
51 //printf("In %s, for va=0x%x, page=0x%x\n", __func__, va, phys_page); 51 //printf("In %s, for va=0x%x, page=0x%x\n", __func__, va, phys_page);
52 return phys_page; 52 return phys_page;
53} 53}
54 54
55static inline void insert_tlb(ARMul_State* state, ARMword va, ARMword pa){ 55static inline void insert_tlb(ARMul_State* state, ARMword va, ARMword pa){
56 //printf("In %s, insert va=0x%x, pa=0x%x\n", __FUNCTION__, va, pa); 56 //printf("In %s, insert va=0x%x, pa=0x%x\n", __FUNCTION__, va, pa);
57 //printf("In %s, insert va=0x%x, va>>12=0x%x, pa=0x%x, pa>>12=0x%x\n", __FUNCTION__, va, va >> 12, pa, pa >> 12); 57 //printf("In %s, insert va=0x%x, va>>12=0x%x, pa=0x%x, pa>>12=0x%x\n", __FUNCTION__, va, va >> 12, pa, pa >> 12);
58 tlb_entry_array[va >> 12][state->mmu.context_id & 0xFF] = pa >> 12; 58 tlb_entry_array[va >> 12][state->mmu.context_id & 0xFF] = pa >> 12;
59 59
60 return; 60 return;
61} 61}
62#endif 62#endif
63#define BANK0_START 0x50000000 63#define BANK0_START 0x50000000
64static void* mem_ptr = NULL; 64static void* mem_ptr = NULL;
65 65
66static int exclusive_detect(ARMul_State* state, ARMword addr){ 66static int exclusive_detect(ARMul_State* state, ARMword addr){
67 #if 0 67 #if 0
68 for(int i = 0; i < 128; i++){ 68 for(int i = 0; i < 128; i++){
69 if(state->exclusive_tag_array[i] == addr) 69 if(state->exclusive_tag_array[i] == addr)
70 return 0; 70 return 0;
71 } 71 }
72 #endif 72 #endif
73 if(state->exclusive_tag_array[0] == addr) 73 if(state->exclusive_tag_array[0] == addr)
74 return 0; 74 return 0;
75 else 75 else
76 return -1; 76 return -1;
77} 77}
78 78
79static void add_exclusive_addr(ARMul_State* state, ARMword addr){ 79static void add_exclusive_addr(ARMul_State* state, ARMword addr){
80 #if 0 80 #if 0
81 for(int i = 0; i < 128; i++){ 81 for(int i = 0; i < 128; i++){
82 if(state->exclusive_tag_array[i] == 0xffffffff){ 82 if(state->exclusive_tag_array[i] == 0xffffffff){
83 state->exclusive_tag_array[i] = addr; 83 state->exclusive_tag_array[i] = addr;
84 //printf("In %s, add addr 0x%x\n", __func__, addr); 84 //printf("In %s, add addr 0x%x\n", __func__, addr);
85 return; 85 return;
86 } 86 }
87 } 87 }
88 printf("In %s ,can not monitor the addr, out of array\n", __FUNCTION__); 88 printf("In %s ,can not monitor the addr, out of array\n", __FUNCTION__);
89 #endif 89 #endif
90 state->exclusive_tag_array[0] = addr; 90 state->exclusive_tag_array[0] = addr;
91 return; 91 return;
92} 92}
93 93
94static void remove_exclusive(ARMul_State* state, ARMword addr){ 94static void remove_exclusive(ARMul_State* state, ARMword addr){
95 #if 0 95 #if 0
96 int i; 96 int i;
97 for(i = 0; i < 128; i++){ 97 for(i = 0; i < 128; i++){
98 if(state->exclusive_tag_array[i] == addr){ 98 if(state->exclusive_tag_array[i] == addr){
99 state->exclusive_tag_array[i] = 0xffffffff; 99 state->exclusive_tag_array[i] = 0xffffffff;
100 //printf("In %s, remove addr 0x%x\n", __func__, addr); 100 //printf("In %s, remove addr 0x%x\n", __func__, addr);
101 return; 101 return;
102 } 102 }
103 } 103 }
104 #endif 104 #endif
105 state->exclusive_tag_array[0] = 0xFFFFFFFF; 105 state->exclusive_tag_array[0] = 0xFFFFFFFF;
106} 106}
107 107
108/* This function encodes table 8-2 Interpreting AP bits, 108/* This function encodes table 8-2 Interpreting AP bits,
@@ -110,100 +110,100 @@ static void remove_exclusive(ARMul_State* state, ARMword addr){
110static int 110static int
111check_perms (ARMul_State *state, int ap, int read) 111check_perms (ARMul_State *state, int ap, int read)
112{ 112{
113 int s, r, user; 113 int s, r, user;
114 114
115 s = state->mmu.control & CONTROL_SYSTEM; 115 s = state->mmu.control & CONTROL_SYSTEM;
116 r = state->mmu.control & CONTROL_ROM; 116 r = state->mmu.control & CONTROL_ROM;
117 /* chy 2006-02-15 , should consider system mode, don't conside 26bit mode */ 117 /* chy 2006-02-15 , should consider system mode, don't conside 26bit mode */
118// printf("ap is %x, user is %x, s is %x, read is %x\n", ap, user, s, read); 118// printf("ap is %x, user is %x, s is %x, read is %x\n", ap, user, s, read);
119// printf("mode is %x\n", state->Mode); 119// printf("mode is %x\n", state->Mode);
120 user = (state->Mode == USER32MODE) || (state->Mode == USER26MODE) || (state->Mode == SYSTEM32MODE); 120 user = (state->Mode == USER32MODE) || (state->Mode == USER26MODE) || (state->Mode == SYSTEM32MODE);
121 121
122 switch (ap) { 122 switch (ap) {
123 case 0: 123 case 0:
124 return read && ((s && !user) || r); 124 return read && ((s && !user) || r);
125 case 1: 125 case 1:
126 return !user; 126 return !user;
127 case 2: 127 case 2:
128 return read || !user; 128 return read || !user;
129 case 3: 129 case 3:
130 return 1; 130 return 1;
131 } 131 }
132 return 0; 132 return 0;
133} 133}
134 134
135#if 0 135#if 0
136fault_t 136fault_t
137check_access (ARMul_State *state, ARMword virt_addr, tlb_entry_t *tlb, 137check_access (ARMul_State *state, ARMword virt_addr, tlb_entry_t *tlb,
138 int read) 138 int read)
139{ 139{
140 int access; 140 int access;
141 141
142 state->mmu.last_domain = tlb->domain; 142 state->mmu.last_domain = tlb->domain;
143 access = (state->mmu.domain_access_control >> (tlb->domain * 2)) & 3; 143 access = (state->mmu.domain_access_control >> (tlb->domain * 2)) & 3;
144 if ((access == 0) || (access == 2)) { 144 if ((access == 0) || (access == 2)) {
145 /* It's unclear from the documentation whether this 145 /* It's unclear from the documentation whether this
146 should always raise a section domain fault, or if 146 should always raise a section domain fault, or if
147 it should be a page domain fault in the case of an 147 it should be a page domain fault in the case of an
148 L1 that describes a page table. In the ARM710T 148 L1 that describes a page table. In the ARM710T
149 datasheets, "Figure 8-9: Sequence for checking faults" 149 datasheets, "Figure 8-9: Sequence for checking faults"
150 seems to indicate the former, while "Table 8-4: Priority 150 seems to indicate the former, while "Table 8-4: Priority
151 encoding of fault status" gives a value for FS[3210] in 151 encoding of fault status" gives a value for FS[3210] in
152 the event of a domain fault for a page. Hmm. */ 152 the event of a domain fault for a page. Hmm. */
153 return SECTION_DOMAIN_FAULT; 153 return SECTION_DOMAIN_FAULT;
154 } 154 }
155 if (access == 1) { 155 if (access == 1) {
156 /* client access - check perms */ 156 /* client access - check perms */
157 int subpage, ap; 157 int subpage, ap;
158#if 0 158#if 0
159 switch (tlb->mapping) { 159 switch (tlb->mapping) {
160 /*ks 2004-05-09 160 /*ks 2004-05-09
161 * only for XScale 161 * only for XScale
162 * Extend Small Page(ESP) Format 162 * Extend Small Page(ESP) Format
163 * 31-12 bits the base addr of ESP 163 * 31-12 bits the base addr of ESP
164 * 11-10 bits SBZ 164 * 11-10 bits SBZ
165 * 9-6 bits TEX 165 * 9-6 bits TEX
166 * 5-4 bits AP 166 * 5-4 bits AP
167 * 3 bit C 167 * 3 bit C
168 * 2 bit B 168 * 2 bit B
169 * 1-0 bits 11 169 * 1-0 bits 11
170 * */ 170 * */
171 case TLB_ESMALLPAGE: /* xj */ 171 case TLB_ESMALLPAGE: /* xj */
172 subpage = 0; 172 subpage = 0;
173 /* printf("TLB_ESMALLPAGE virt_addr=0x%x \n",virt_addr ); */ 173 /* printf("TLB_ESMALLPAGE virt_addr=0x%x \n",virt_addr ); */
174 break; 174 break;
175 175
176 case TLB_TINYPAGE: 176 case TLB_TINYPAGE:
177 subpage = 0; 177 subpage = 0;
178 /* printf("TLB_TINYPAGE virt_addr=0x%x \n",virt_addr ); */ 178 /* printf("TLB_TINYPAGE virt_addr=0x%x \n",virt_addr ); */
179 break; 179 break;
180 180
181 case TLB_SMALLPAGE: 181 case TLB_SMALLPAGE:
182 subpage = (virt_addr >> 10) & 3; 182 subpage = (virt_addr >> 10) & 3;
183 break; 183 break;
184 case TLB_LARGEPAGE: 184 case TLB_LARGEPAGE:
185 subpage = (virt_addr >> 14) & 3; 185 subpage = (virt_addr >> 14) & 3;
186 break; 186 break;
187 case TLB_SECTION: 187 case TLB_SECTION:
188 subpage = 3; 188 subpage = 3;
189 break; 189 break;
190 default: 190 default:
191 assert (0); 191 assert (0);
192 subpage = 0; /* cleans a warning */ 192 subpage = 0; /* cleans a warning */
193 } 193 }
194 ap = (tlb->perms >> (subpage * 2 + 4)) & 3; 194 ap = (tlb->perms >> (subpage * 2 + 4)) & 3;
195 if (!check_perms (state, ap, read)) { 195 if (!check_perms (state, ap, read)) {
196 if (tlb->mapping == TLB_SECTION) { 196 if (tlb->mapping == TLB_SECTION) {
197 return SECTION_PERMISSION_FAULT; 197 return SECTION_PERMISSION_FAULT;
198 } else { 198 } else {
199 return SUBPAGE_PERMISSION_FAULT; 199 return SUBPAGE_PERMISSION_FAULT;
200 } 200 }
201 } 201 }
202#endif 202#endif
203 } else { /* access == 3 */ 203 } else { /* access == 3 */
204 /* manager access - don't check perms */ 204 /* manager access - don't check perms */
205 } 205 }
206 return NO_FAULT; 206 return NO_FAULT;
207} 207}
208#endif 208#endif
209 209
@@ -218,18 +218,18 @@ mmu_translate (ARMul_State *state, ARMword virt_addr, ARMword *phys_addr)
218fault_t 218fault_t
219mmu_translate (ARMul_State *state, ARMword virt_addr, ARMword *phys_addr, int *ap, int *sop) 219mmu_translate (ARMul_State *state, ARMword virt_addr, ARMword *phys_addr, int *ap, int *sop)
220{ 220{
221 { 221 {
222 /* walk the translation tables */ 222 /* walk the translation tables */
223 ARMword l1addr, l1desc; 223 ARMword l1addr, l1desc;
224 if (state->mmu.translation_table_ctrl && virt_addr << state->mmu.translation_table_ctrl >> (32 - state->mmu.translation_table_ctrl - 1)) { 224 if (state->mmu.translation_table_ctrl && virt_addr << state->mmu.translation_table_ctrl >> (32 - state->mmu.translation_table_ctrl - 1)) {
225 l1addr = state->mmu.translation_table_base1; 225 l1addr = state->mmu.translation_table_base1;
226 l1addr = (((l1addr >> 14) << 14) | (virt_addr >> 18)) & ~3; 226 l1addr = (((l1addr >> 14) << 14) | (virt_addr >> 18)) & ~3;
227 } else { 227 } else {
228 l1addr = state->mmu.translation_table_base0; 228 l1addr = state->mmu.translation_table_base0;
229 l1addr = (((l1addr >> (14 - state->mmu.translation_table_ctrl)) << (14 - state->mmu.translation_table_ctrl)) | (virt_addr << state->mmu.translation_table_ctrl) >> (18 + state->mmu.translation_table_ctrl)) & ~3; 229 l1addr = (((l1addr >> (14 - state->mmu.translation_table_ctrl)) << (14 - state->mmu.translation_table_ctrl)) | (virt_addr << state->mmu.translation_table_ctrl) >> (18 + state->mmu.translation_table_ctrl)) & ~3;
230 } 230 }
231 231
232 /* l1desc = mem_read_word (state, l1addr); */ 232 /* l1desc = mem_read_word (state, l1addr); */
233 if (state->space.conf_obj != NULL) 233 if (state->space.conf_obj != NULL)
234 state->space.read(state->space.conf_obj, l1addr, &l1desc, 4); 234 state->space.read(state->space.conf_obj, l1addr, &l1desc, 4);
235 else 235 else
@@ -244,55 +244,55 @@ mmu_translate (ARMul_State *state, ARMword virt_addr, ARMword *phys_addr, int *a
244 // exit(-1); 244 // exit(-1);
245 } 245 }
246 #endif 246 #endif
247 switch (l1desc & 3) { 247 switch (l1desc & 3) {
248 case 0: 248 case 0:
249 case 3: 249 case 3:
250 /* 250 /*
251 * according to Figure 3-9 Sequence for checking faults in arm manual, 251 * according to Figure 3-9 Sequence for checking faults in arm manual,
252 * section translation fault should be returned here. 252 * section translation fault should be returned here.
253 */ 253 */
254 { 254 {
255 return SECTION_TRANSLATION_FAULT; 255 return SECTION_TRANSLATION_FAULT;
256 } 256 }
257 case 1: 257 case 1:
258 /* coarse page table */ 258 /* coarse page table */
259 { 259 {
260 ARMword l2addr, l2desc; 260 ARMword l2addr, l2desc;
261 261
262 262
263 l2addr = l1desc & 0xFFFFFC00; 263 l2addr = l1desc & 0xFFFFFC00;
264 l2addr = (l2addr | 264 l2addr = (l2addr |
265 ((virt_addr & 0x000FF000) >> 10)) & 265 ((virt_addr & 0x000FF000) >> 10)) &
266 ~3; 266 ~3;
267 if(state->space.conf_obj != NULL) 267 if(state->space.conf_obj != NULL)
268 state->space.read(state->space.conf_obj, l2addr, &l2desc, 4); 268 state->space.read(state->space.conf_obj, l2addr, &l2desc, 4);
269 else 269 else
270 l2desc = Memory::Read32(l2addr); //mem_read_raw(32, l2addr, &l2desc); 270 l2desc = Memory::Read32(l2addr); //mem_read_raw(32, l2addr, &l2desc);
271 271
272 /* chy 2003-09-02 for xscale */ 272 /* chy 2003-09-02 for xscale */
273 *ap = (l2desc >> 4) & 0x3; 273 *ap = (l2desc >> 4) & 0x3;
274 *sop = 1; /* page */ 274 *sop = 1; /* page */
275 275
276 switch (l2desc & 3) { 276 switch (l2desc & 3) {
277 case 0: 277 case 0:
278 return PAGE_TRANSLATION_FAULT; 278 return PAGE_TRANSLATION_FAULT;
279 break; 279 break;
280 case 1: 280 case 1:
281 *phys_addr = (l2desc & 0xFFFF0000) | (virt_addr & 0x0000FFFF); 281 *phys_addr = (l2desc & 0xFFFF0000) | (virt_addr & 0x0000FFFF);
282 break; 282 break;
283 case 2: 283 case 2:
284 case 3: 284 case 3:
285 *phys_addr = (l2desc & 0xFFFFF000) | (virt_addr & 0x00000FFF); 285 *phys_addr = (l2desc & 0xFFFFF000) | (virt_addr & 0x00000FFF);
286 break; 286 break;
287 287
288 } 288 }
289 } 289 }
290 break; 290 break;
291 case 2: 291 case 2:
292 /* section */ 292 /* section */
293 293
294 *ap = (l1desc >> 10) & 3; 294 *ap = (l1desc >> 10) & 3;
295 *sop = 0; /* section */ 295 *sop = 0; /* section */
296 #if 0 296 #if 0
297 if (virt_addr == 0xc000d2bc) { 297 if (virt_addr == 0xc000d2bc) {
298 printf("mmu_control is %x\n", state->mmu.translation_table_ctrl); 298 printf("mmu_control is %x\n", state->mmu.translation_table_ctrl);
@@ -307,35 +307,35 @@ mmu_translate (ARMul_State *state, ARMword virt_addr, ARMword *phys_addr, int *a
307 #endif 307 #endif
308 308
309 if (l1desc & 0x30000) 309 if (l1desc & 0x30000)
310 *phys_addr = (l1desc & 0xFF000000) | (virt_addr & 0x00FFFFFF); 310 *phys_addr = (l1desc & 0xFF000000) | (virt_addr & 0x00FFFFFF);
311 else 311 else
312 *phys_addr = (l1desc & 0xFFF00000) | (virt_addr & 0x000FFFFF); 312 *phys_addr = (l1desc & 0xFFF00000) | (virt_addr & 0x000FFFFF);
313 break; 313 break;
314 } 314 }
315 } 315 }
316 return NO_FAULT; 316 return NO_FAULT;
317} 317}
318 318
319 319
320static fault_t arm1176jzf_s_mmu_write (ARMul_State *state, ARMword va, 320static fault_t arm1176jzf_s_mmu_write (ARMul_State *state, ARMword va,
321 ARMword data, ARMword datatype); 321 ARMword data, ARMword datatype);
322static fault_t arm1176jzf_s_mmu_read (ARMul_State *state, ARMword va, 322static fault_t arm1176jzf_s_mmu_read (ARMul_State *state, ARMword va,
323 ARMword *data, ARMword datatype); 323 ARMword *data, ARMword datatype);
324 324
325int 325int
326arm1176jzf_s_mmu_init (ARMul_State *state) 326arm1176jzf_s_mmu_init (ARMul_State *state)
327{ 327{
328 state->mmu.control = 0x50078; 328 state->mmu.control = 0x50078;
329 state->mmu.translation_table_base = 0xDEADC0DE; 329 state->mmu.translation_table_base = 0xDEADC0DE;
330 state->mmu.domain_access_control = 0xDEADC0DE; 330 state->mmu.domain_access_control = 0xDEADC0DE;
331 state->mmu.fault_status = 0; 331 state->mmu.fault_status = 0;
332 state->mmu.fault_address = 0; 332 state->mmu.fault_address = 0;
333 state->mmu.process_id = 0; 333 state->mmu.process_id = 0;
334 state->mmu.context_id = 0; 334 state->mmu.context_id = 0;
335 state->mmu.thread_uro_id = 0; 335 state->mmu.thread_uro_id = 0;
336 //invalidate_all_tlb(state); 336 //invalidate_all_tlb(state);
337 337
338 return No_exp; 338 return No_exp;
339} 339}
340 340
341void 341void
@@ -347,163 +347,163 @@ arm1176jzf_s_mmu_exit (ARMul_State *state)
347static fault_t 347static fault_t
348arm1176jzf_s_mmu_load_instr (ARMul_State *state, ARMword va, ARMword *instr) 348arm1176jzf_s_mmu_load_instr (ARMul_State *state, ARMword va, ARMword *instr)
349{ 349{
350 fault_t fault; 350 fault_t fault;
351 int c; /* cache bit */ 351 int c; /* cache bit */
352 ARMword pa; /* physical addr */ 352 ARMword pa; /* physical addr */
353 ARMword perm; /* physical addr access permissions */ 353 ARMword perm; /* physical addr access permissions */
354 int ap, sop; 354 int ap, sop;
355 355
356 static int debug_count = 0; /* used for debug */ 356 static int debug_count = 0; /* used for debug */
357 357
358 DEBUG_LOG(ARM11, "va = %x\n", va); 358 DEBUG_LOG(ARM11, "va = %x\n", va);
359 359
360 va = mmu_pid_va_map (va); 360 va = mmu_pid_va_map (va);
361 if (MMU_Enabled) { 361 if (MMU_Enabled) {
362// printf("MMU enabled.\n"); 362// printf("MMU enabled.\n");
363// sleep(1); 363// sleep(1);
364 /* align check */ 364 /* align check */
365 if ((va & (WORD_SIZE - 1)) && MMU_Aligned) { 365 if ((va & (WORD_SIZE - 1)) && MMU_Aligned) {
366 DEBUG_LOG(ARM11, "align\n"); 366 DEBUG_LOG(ARM11, "align\n");
367 return ALIGNMENT_FAULT; 367 return ALIGNMENT_FAULT;
368 } else 368 } else
369 va &= ~(WORD_SIZE - 1); 369 va &= ~(WORD_SIZE - 1);
370 370
371 /* translate tlb */ 371 /* translate tlb */
372 fault = mmu_translate (state, va, &pa, &ap, &sop); 372 fault = mmu_translate (state, va, &pa, &ap, &sop);
373 if (fault) { 373 if (fault) {
374 DEBUG_LOG(ARM11, "translate\n"); 374 DEBUG_LOG(ARM11, "translate\n");
375 printf("va=0x%x, icounter=%lld, fault=%d\n", va, state->NumInstrs, fault); 375 printf("va=0x%x, icounter=%lld, fault=%d\n", va, state->NumInstrs, fault);
376 return fault; 376 return fault;
377 } 377 }
378 378
379 379
380 /* no tlb, only check permission */ 380 /* no tlb, only check permission */
381 if (!check_perms(state, ap, 1)) { 381 if (!check_perms(state, ap, 1)) {
382 if (sop == 0) { 382 if (sop == 0) {
383 return SECTION_PERMISSION_FAULT; 383 return SECTION_PERMISSION_FAULT;
384 } else { 384 } else {
385 return SUBPAGE_PERMISSION_FAULT; 385 return SUBPAGE_PERMISSION_FAULT;
386 } 386 }
387 } 387 }
388 388
389#if 0 389#if 0
390 /*check access */ 390 /*check access */
391 fault = check_access (state, va, tlb, 1); 391 fault = check_access (state, va, tlb, 1);
392 if (fault) { 392 if (fault) {
393 DEBUG_LOG(ARM11, "check_fault\n"); 393 DEBUG_LOG(ARM11, "check_fault\n");
394 return fault; 394 return fault;
395 } 395 }
396#endif 396#endif
397 } 397 }
398 398
399 /*if MMU disabled or C flag is set alloc cache */ 399 /*if MMU disabled or C flag is set alloc cache */
400 if (MMU_Disabled) { 400 if (MMU_Disabled) {
401// printf("MMU disabled.\n"); 401// printf("MMU disabled.\n");
402// sleep(1); 402// sleep(1);
403 pa = va; 403 pa = va;
404 } 404 }
405 if(state->space.conf_obj == NULL) 405 if(state->space.conf_obj == NULL)
406 state->space.read(state->space.conf_obj, pa, instr, 4); 406 state->space.read(state->space.conf_obj, pa, instr, 4);
407 else 407 else
408 *instr = Memory::Read32(pa); //mem_read_raw(32, pa, instr); 408 *instr = Memory::Read32(pa); //mem_read_raw(32, pa, instr);
409 409
410 return NO_FAULT; 410 return NO_FAULT;
411} 411}
412 412
413static fault_t 413static fault_t
414arm1176jzf_s_mmu_read_byte (ARMul_State *state, ARMword virt_addr, ARMword *data) 414arm1176jzf_s_mmu_read_byte (ARMul_State *state, ARMword virt_addr, ARMword *data)
415{ 415{
416 /* ARMword temp,offset; */ 416 /* ARMword temp,offset; */
417 fault_t fault; 417 fault_t fault;
418 fault = arm1176jzf_s_mmu_read (state, virt_addr, data, ARM_BYTE_TYPE); 418 fault = arm1176jzf_s_mmu_read (state, virt_addr, data, ARM_BYTE_TYPE);
419 return fault; 419 return fault;
420} 420}
421 421
422static fault_t 422static fault_t
423arm1176jzf_s_mmu_read_halfword (ARMul_State *state, ARMword virt_addr, 423arm1176jzf_s_mmu_read_halfword (ARMul_State *state, ARMword virt_addr,
424 ARMword *data) 424 ARMword *data)
425{ 425{
426 /* ARMword temp,offset; */ 426 /* ARMword temp,offset; */
427 fault_t fault; 427 fault_t fault;
428 fault = arm1176jzf_s_mmu_read (state, virt_addr, data, ARM_HALFWORD_TYPE); 428 fault = arm1176jzf_s_mmu_read (state, virt_addr, data, ARM_HALFWORD_TYPE);
429 return fault; 429 return fault;
430} 430}
431 431
432static fault_t 432static fault_t
433arm1176jzf_s_mmu_read_word (ARMul_State *state, ARMword virt_addr, ARMword *data) 433arm1176jzf_s_mmu_read_word (ARMul_State *state, ARMword virt_addr, ARMword *data)
434{ 434{
435 return arm1176jzf_s_mmu_read (state, virt_addr, data, ARM_WORD_TYPE); 435 return arm1176jzf_s_mmu_read (state, virt_addr, data, ARM_WORD_TYPE);
436} 436}
437 437
438static fault_t 438static fault_t
439arm1176jzf_s_mmu_read (ARMul_State *state, ARMword va, ARMword *data, 439arm1176jzf_s_mmu_read (ARMul_State *state, ARMword va, ARMword *data,
440 ARMword datatype) 440 ARMword datatype)
441{ 441{
442 fault_t fault; 442 fault_t fault;
443 ARMword pa, real_va, temp, offset; 443 ARMword pa, real_va, temp, offset;
444 ARMword perm; /* physical addr access permissions */ 444 ARMword perm; /* physical addr access permissions */
445 int ap, sop; 445 int ap, sop;
446 446
447 DEBUG_LOG(ARM11, "va = %x\n", va); 447 DEBUG_LOG(ARM11, "va = %x\n", va);
448 448
449 va = mmu_pid_va_map (va); 449 va = mmu_pid_va_map (va);
450 real_va = va; 450 real_va = va;
451 /* if MMU disabled, memory_read */ 451 /* if MMU disabled, memory_read */
452 if (MMU_Disabled) { 452 if (MMU_Disabled) {
453// printf("MMU disabled cpu_id:%x addr:%x.\n", state->mmu.process_id, va); 453// printf("MMU disabled cpu_id:%x addr:%x.\n", state->mmu.process_id, va);
454// sleep(1); 454// sleep(1);
455 455
456 /* *data = mem_read_word(state, va); */ 456 /* *data = mem_read_word(state, va); */
457 if (datatype == ARM_BYTE_TYPE) 457 if (datatype == ARM_BYTE_TYPE)
458 /* *data = mem_read_byte (state, va); */ 458 /* *data = mem_read_byte (state, va); */
459 if(state->space.conf_obj != NULL) 459 if(state->space.conf_obj != NULL)
460 state->space.read(state->space.conf_obj, va, data, 1); 460 state->space.read(state->space.conf_obj, va, data, 1);
461 else 461 else
462 *data = Memory::Read8(va); //mem_read_raw(8, va, data); 462 *data = Memory::Read8(va); //mem_read_raw(8, va, data);
463 else if (datatype == ARM_HALFWORD_TYPE) 463 else if (datatype == ARM_HALFWORD_TYPE)
464 /* *data = mem_read_halfword (state, va); */ 464 /* *data = mem_read_halfword (state, va); */
465 if(state->space.conf_obj != NULL) 465 if(state->space.conf_obj != NULL)
466 state->space.read(state->space.conf_obj, va, data, 2); 466 state->space.read(state->space.conf_obj, va, data, 2);
467 else 467 else
468 *data = Memory::Read16(va); //mem_read_raw(16, va, data); 468 *data = Memory::Read16(va); //mem_read_raw(16, va, data);
469 else if (datatype == ARM_WORD_TYPE) 469 else if (datatype == ARM_WORD_TYPE)
470 /* *data = mem_read_word (state, va); */ 470 /* *data = mem_read_word (state, va); */
471 if(state->space.conf_obj != NULL) 471 if(state->space.conf_obj != NULL)
472 state->space.read(state->space.conf_obj, va, data, 4); 472 state->space.read(state->space.conf_obj, va, data, 4);
473 else 473 else
474 *data = Memory::Read32(va); //mem_read_raw(32, va, data); 474 *data = Memory::Read32(va); //mem_read_raw(32, va, data);
475 else { 475 else {
476 ERROR_LOG(ARM11, "SKYEYE:1 arm1176jzf_s_mmu_read error: unknown data type %d\n", datatype); 476 ERROR_LOG(ARM11, "SKYEYE:1 arm1176jzf_s_mmu_read error: unknown data type %d\n", datatype);
477 } 477 }
478 478
479 return NO_FAULT; 479 return NO_FAULT;
480 } 480 }
481// printf("MMU enabled.\n"); 481// printf("MMU enabled.\n");
482// sleep(1); 482// sleep(1);
483 483
484 /* align check */ 484 /* align check */
485 if (((va & 3) && (datatype == ARM_WORD_TYPE) && MMU_Aligned) || 485 if (((va & 3) && (datatype == ARM_WORD_TYPE) && MMU_Aligned) ||
486 ((va & 1) && (datatype == ARM_HALFWORD_TYPE) && MMU_Aligned)) { 486 ((va & 1) && (datatype == ARM_HALFWORD_TYPE) && MMU_Aligned)) {
487 DEBUG_LOG(ARM11, "align\n"); 487 DEBUG_LOG(ARM11, "align\n");
488 return ALIGNMENT_FAULT; 488 return ALIGNMENT_FAULT;
489 } 489 }
490 490
491 /* va &= ~(WORD_SIZE - 1); */ 491 /* va &= ~(WORD_SIZE - 1); */
492 #if 0 492 #if 0
493 uint32_t page_base; 493 uint32_t page_base;
494 page_base = get_phys_page(state, va); 494 page_base = get_phys_page(state, va);
495 if((page_base & 0xFFF) == 0){ 495 if((page_base & 0xFFF) == 0){
496 pa = (page_base << 12) | (va & 0xFFF); 496 pa = (page_base << 12) | (va & 0xFFF);
497 goto skip_translation; 497 goto skip_translation;
498 } 498 }
499 #endif 499 #endif
500 /*translate va to tlb */ 500 /*translate va to tlb */
501#if 0 501#if 0
502 fault = mmu_translate (state, va, ARM920T_D_TLB (), &tlb); 502 fault = mmu_translate (state, va, ARM920T_D_TLB (), &tlb);
503#endif 503#endif
504 fault = mmu_translate (state, va, &pa, &ap, &sop); 504 fault = mmu_translate (state, va, &pa, &ap, &sop);
505#if 0 505#if 0
506 if(va ==0xbebb1774 || state->Reg[15] == 0x400ff594){ 506 if(va ==0xbebb1774 || state->Reg[15] == 0x400ff594){
507 //printf("In %s, current=0x%x. mode is %x, pc=0x%x\n", __FUNCTION__, state->CurrInstr, state->Mode, state->Reg[15]); 507 //printf("In %s, current=0x%x. mode is %x, pc=0x%x\n", __FUNCTION__, state->CurrInstr, state->Mode, state->Reg[15]);
508 printf("In %s, ap is %d, sop is %d, va=0x%x, pa=0x%x, fault=%d, data=0x%x\n", __FUNCTION__, ap, sop, va, pa, fault, data); 508 printf("In %s, ap is %d, sop is %d, va=0x%x, pa=0x%x, fault=%d, data=0x%x\n", __FUNCTION__, ap, sop, va, pa, fault, data);
509 int i; 509 int i;
@@ -512,68 +512,68 @@ arm1176jzf_s_mmu_read (ARMul_State *state, ARMword va, ARMword *data,
512 printf("\n"); 512 printf("\n");
513 } 513 }
514#endif 514#endif
515 if (fault) { 515 if (fault) {
516 DEBUG_LOG(ARM11, "translate\n"); 516 DEBUG_LOG(ARM11, "translate\n");
517 //printf("mmu read fault at %x\n", va); 517 //printf("mmu read fault at %x\n", va);
518 //printf("fault is %d\n", fault); 518 //printf("fault is %d\n", fault);
519 return fault; 519 return fault;
520 } 520 }
521// printf("va is %x pa is %x\n", va, pa); 521// printf("va is %x pa is %x\n", va, pa);
522 522
523 /* no tlb, only check permission */ 523 /* no tlb, only check permission */
524 if (!check_perms(state, ap, 1)) { 524 if (!check_perms(state, ap, 1)) {
525 if (sop == 0) { 525 if (sop == 0) {
526 return SECTION_PERMISSION_FAULT; 526 return SECTION_PERMISSION_FAULT;
527 } else { 527 } else {
528 return SUBPAGE_PERMISSION_FAULT; 528 return SUBPAGE_PERMISSION_FAULT;
529 } 529 }
530 } 530 }
531#if 0 531#if 0
532 /*check access permission */ 532 /*check access permission */
533 fault = check_access (state, va, tlb, 1); 533 fault = check_access (state, va, tlb, 1);
534 if (fault) 534 if (fault)
535 return fault; 535 return fault;
536#endif 536#endif
537 537
538 //insert_tlb(state, va, pa); 538 //insert_tlb(state, va, pa);
539skip_translation: 539skip_translation:
540 /* *data = mem_read_word(state, pa); */ 540 /* *data = mem_read_word(state, pa); */
541 if (datatype == ARM_BYTE_TYPE) { 541 if (datatype == ARM_BYTE_TYPE) {
542 /* *data = mem_read_byte (state, pa | (real_va & 3)); */ 542 /* *data = mem_read_byte (state, pa | (real_va & 3)); */
543 if(state->space.conf_obj != NULL) 543 if(state->space.conf_obj != NULL)
544 state->space.read(state->space.conf_obj, pa | (real_va & 3), data, 1); 544 state->space.read(state->space.conf_obj, pa | (real_va & 3), data, 1);
545 else 545 else
546 *data = Memory::Read8(pa | (real_va & 3)); //mem_read_raw(8, pa | (real_va & 3), data); 546 *data = Memory::Read8(pa | (real_va & 3)); //mem_read_raw(8, pa | (real_va & 3), data);
547 /* mem_read_raw(32, pa | (real_va & 3), data); */ 547 /* mem_read_raw(32, pa | (real_va & 3), data); */
548 } else if (datatype == ARM_HALFWORD_TYPE) { 548 } else if (datatype == ARM_HALFWORD_TYPE) {
549 /* *data = mem_read_halfword (state, pa | (real_va & 2)); */ 549 /* *data = mem_read_halfword (state, pa | (real_va & 2)); */
550 if(state->space.conf_obj != NULL) 550 if(state->space.conf_obj != NULL)
551 state->space.read(state->space.conf_obj, pa | (real_va & 3), data, 2); 551 state->space.read(state->space.conf_obj, pa | (real_va & 3), data, 2);
552 else 552 else
553 *data = Memory::Read16(pa | (real_va & 3)); //mem_read_raw(16, pa | (real_va & 3), data); 553 *data = Memory::Read16(pa | (real_va & 3)); //mem_read_raw(16, pa | (real_va & 3), data);
554 /* mem_read_raw(32, pa | (real_va & 2), data); */ 554 /* mem_read_raw(32, pa | (real_va & 2), data); */
555 } else if (datatype == ARM_WORD_TYPE) 555 } else if (datatype == ARM_WORD_TYPE)
556 /* *data = mem_read_word (state, pa); */ 556 /* *data = mem_read_word (state, pa); */
557 if(state->space.conf_obj != NULL) 557 if(state->space.conf_obj != NULL)
558 state->space.read(state->space.conf_obj, pa , data, 4); 558 state->space.read(state->space.conf_obj, pa , data, 4);
559 else 559 else
560 *data = Memory::Read32(pa); //mem_read_raw(32, pa, data); 560 *data = Memory::Read32(pa); //mem_read_raw(32, pa, data);
561 else { 561 else {
562 ERROR_LOG(ARM11, "SKYEYE:2 arm1176jzf_s_mmu_read error: unknown data type %d\n", datatype); 562 ERROR_LOG(ARM11, "SKYEYE:2 arm1176jzf_s_mmu_read error: unknown data type %d\n", datatype);
563 } 563 }
564 if(0 && (va == 0x2869c)){ 564 if(0 && (va == 0x2869c)){
565 printf("In %s, pa is %x va=0x%x, value is %x pc %x, instr=0x%x\n", __FUNCTION__, pa, va, *data, state->Reg[15], state->CurrInstr); 565 printf("In %s, pa is %x va=0x%x, value is %x pc %x, instr=0x%x\n", __FUNCTION__, pa, va, *data, state->Reg[15], state->CurrInstr);
566 } 566 }
567 567
568 /* ldrex or ldrexb */ 568 /* ldrex or ldrexb */
569 if(((state->CurrInstr & 0x0FF000F0) == 0x01900090) || 569 if(((state->CurrInstr & 0x0FF000F0) == 0x01900090) ||
570 ((state->CurrInstr & 0x0FF000F0) == 0x01d00090)){ 570 ((state->CurrInstr & 0x0FF000F0) == 0x01d00090)){
571 int rn = (state->CurrInstr & 0xF0000) >> 16; 571 int rn = (state->CurrInstr & 0xF0000) >> 16;
572 if(state->Reg[rn] == va){ 572 if(state->Reg[rn] == va){
573 add_exclusive_addr(state, pa | (real_va & 3)); 573 add_exclusive_addr(state, pa | (real_va & 3));
574 state->exclusive_access_state = 1; 574 state->exclusive_access_state = 1;
575 } 575 }
576 } 576 }
577#if 0 577#if 0
578 if (state->pc == 0xc011a868) { 578 if (state->pc == 0xc011a868) {
579 printf("pa is %x value is %x size is %x\n", pa, data, datatype); 579 printf("pa is %x value is %x size is %x\n", pa, data, datatype);
@@ -582,103 +582,103 @@ skip_translation:
582 } 582 }
583#endif 583#endif
584 584
585 return NO_FAULT; 585 return NO_FAULT;
586} 586}
587 587
588 588
589static fault_t 589static fault_t
590arm1176jzf_s_mmu_write_byte (ARMul_State *state, ARMword virt_addr, ARMword data) 590arm1176jzf_s_mmu_write_byte (ARMul_State *state, ARMword virt_addr, ARMword data)
591{ 591{
592 return arm1176jzf_s_mmu_write (state, virt_addr, data, ARM_BYTE_TYPE); 592 return arm1176jzf_s_mmu_write (state, virt_addr, data, ARM_BYTE_TYPE);
593} 593}
594 594
595static fault_t 595static fault_t
596arm1176jzf_s_mmu_write_halfword (ARMul_State *state, ARMword virt_addr, 596arm1176jzf_s_mmu_write_halfword (ARMul_State *state, ARMword virt_addr,
597 ARMword data) 597 ARMword data)
598{ 598{
599 return arm1176jzf_s_mmu_write (state, virt_addr, data, ARM_HALFWORD_TYPE); 599 return arm1176jzf_s_mmu_write (state, virt_addr, data, ARM_HALFWORD_TYPE);
600} 600}
601 601
602static fault_t 602static fault_t
603arm1176jzf_s_mmu_write_word (ARMul_State *state, ARMword virt_addr, ARMword data) 603arm1176jzf_s_mmu_write_word (ARMul_State *state, ARMword virt_addr, ARMword data)
604{ 604{
605 return arm1176jzf_s_mmu_write (state, virt_addr, data, ARM_WORD_TYPE); 605 return arm1176jzf_s_mmu_write (state, virt_addr, data, ARM_WORD_TYPE);
606} 606}
607 607
608 608
609 609
610static fault_t 610static fault_t
611arm1176jzf_s_mmu_write (ARMul_State *state, ARMword va, ARMword data, 611arm1176jzf_s_mmu_write (ARMul_State *state, ARMword va, ARMword data,
612 ARMword datatype) 612 ARMword datatype)
613{ 613{
614 int b; 614 int b;
615 ARMword pa, real_va; 615 ARMword pa, real_va;
616 ARMword perm; /* physical addr access permissions */ 616 ARMword perm; /* physical addr access permissions */
617 fault_t fault; 617 fault_t fault;
618 int ap, sop; 618 int ap, sop;
619 619
620#if 0 620#if 0
621 /8 for sky_printk debugger.*/ 621 /8 for sky_printk debugger.*/
622 if (va == 0xffffffff) { 622 if (va == 0xffffffff) {
623 putchar((char)data); 623 putchar((char)data);
624 return 0; 624 return 0;
625 } 625 }
626 if (va == 0xBfffffff) { 626 if (va == 0xBfffffff) {
627 putchar((char)data); 627 putchar((char)data);
628 return 0; 628 return 0;
629 } 629 }
630#endif 630#endif
631 631
632 DEBUG_LOG(ARM11, "va = %x, val = %x\n", va, data); 632 DEBUG_LOG(ARM11, "va = %x, val = %x\n", va, data);
633 va = mmu_pid_va_map (va); 633 va = mmu_pid_va_map (va);
634 real_va = va; 634 real_va = va;
635 635
636 if (MMU_Disabled) { 636 if (MMU_Disabled) {
637 /* mem_write_word(state, va, data); */ 637 /* mem_write_word(state, va, data); */
638 if (datatype == ARM_BYTE_TYPE) 638 if (datatype == ARM_BYTE_TYPE)
639 /* mem_write_byte (state, va, data); */ 639 /* mem_write_byte (state, va, data); */
640 if(state->space.conf_obj != NULL) 640 if(state->space.conf_obj != NULL)
641 state->space.write(state->space.conf_obj, va, &data, 1); 641 state->space.write(state->space.conf_obj, va, &data, 1);
642 else 642 else
643 Memory::Write8(va, data); 643 Memory::Write8(va, data);
644 else if (datatype == ARM_HALFWORD_TYPE) 644 else if (datatype == ARM_HALFWORD_TYPE)
645 /* mem_write_halfword (state, va, data); */ 645 /* mem_write_halfword (state, va, data); */
646 if(state->space.conf_obj != NULL) 646 if(state->space.conf_obj != NULL)
647 state->space.write(state->space.conf_obj, va, &data, 2); 647 state->space.write(state->space.conf_obj, va, &data, 2);
648 else 648 else
649 Memory::Write16(va, data); 649 Memory::Write16(va, data);
650 else if (datatype == ARM_WORD_TYPE) 650 else if (datatype == ARM_WORD_TYPE)
651 /* mem_write_word (state, va, data); */ 651 /* mem_write_word (state, va, data); */
652 if(state->space.conf_obj != NULL) 652 if(state->space.conf_obj != NULL)
653 state->space.write(state->space.conf_obj, va, &data, 4); 653 state->space.write(state->space.conf_obj, va, &data, 4);
654 else 654 else
655 Memory::Write32(va, data); 655 Memory::Write32(va, data);
656 else { 656 else {
657 ERROR_LOG (ARM11, "SKYEYE:1 arm1176jzf_s_mmu_write error: unknown data type %d\n", datatype); 657 ERROR_LOG (ARM11, "SKYEYE:1 arm1176jzf_s_mmu_write error: unknown data type %d\n", datatype);
658 } 658 }
659 goto finished_write; 659 goto finished_write;
660 //return 0; 660 //return 0;
661 } 661 }
662 /*align check */ 662 /*align check */
663 /* if ((va & (WORD_SIZE - 1)) && MMU_Aligned){ */ 663 /* if ((va & (WORD_SIZE - 1)) && MMU_Aligned){ */
664 if (((va & 3) && (datatype == ARM_WORD_TYPE) && MMU_Aligned) || 664 if (((va & 3) && (datatype == ARM_WORD_TYPE) && MMU_Aligned) ||
665 ((va & 1) && (datatype == ARM_HALFWORD_TYPE) && MMU_Aligned)) { 665 ((va & 1) && (datatype == ARM_HALFWORD_TYPE) && MMU_Aligned)) {
666 DEBUG_LOG(ARM11, "align\n"); 666 DEBUG_LOG(ARM11, "align\n");
667 return ALIGNMENT_FAULT; 667 return ALIGNMENT_FAULT;
668 } 668 }
669 va &= ~(WORD_SIZE - 1); 669 va &= ~(WORD_SIZE - 1);
670 #if 0 670 #if 0
671 uint32_t page_base; 671 uint32_t page_base;
672 page_base = get_phys_page(state, va); 672 page_base = get_phys_page(state, va);
673 if((page_base & 0xFFF) == 0){ 673 if((page_base & 0xFFF) == 0){
674 pa = (page_base << 12) | (va & 0xFFF); 674 pa = (page_base << 12) | (va & 0xFFF);
675 goto skip_translation; 675 goto skip_translation;
676 } 676 }
677 #endif 677 #endif
678 /*tlb translate */ 678 /*tlb translate */
679 fault = mmu_translate (state, va, &pa, &ap, &sop); 679 fault = mmu_translate (state, va, &pa, &ap, &sop);
680#if 0 680#if 0
681 if(va ==0xbebb1774 || state->Reg[15] == 0x40102334){ 681 if(va ==0xbebb1774 || state->Reg[15] == 0x40102334){
682 //printf("In %s, current=0x%x. mode is %x, pc=0x%x\n", __FUNCTION__, state->CurrInstr, state->Mode, state->Reg[15]); 682 //printf("In %s, current=0x%x. mode is %x, pc=0x%x\n", __FUNCTION__, state->CurrInstr, state->Mode, state->Reg[15]);
683 printf("In %s, ap is %d, sop is %d, va=0x%x, pa=0x%x, fault=%d, data=0x%x\n", __FUNCTION__, ap, sop, va, pa, fault, data); 683 printf("In %s, ap is %d, sop is %d, va=0x%x, pa=0x%x, fault=%d, data=0x%x\n", __FUNCTION__, ap, sop, va, pa, fault, data);
684 int i; 684 int i;
@@ -687,29 +687,29 @@ arm1176jzf_s_mmu_write (ARMul_State *state, ARMword va, ARMword data,
687 printf("\n"); 687 printf("\n");
688 } 688 }
689#endif 689#endif
690 if (fault) { 690 if (fault) {
691 DEBUG_LOG(ARM11, "translate\n"); 691 DEBUG_LOG(ARM11, "translate\n");
692 //printf("mmu write fault at %x\n", va); 692 //printf("mmu write fault at %x\n", va);
693 return fault; 693 return fault;
694 } 694 }
695// printf("va is %x pa is %x\n", va, pa); 695// printf("va is %x pa is %x\n", va, pa);
696 696
697 /* no tlb, only check permission */ 697 /* no tlb, only check permission */
698 if (!check_perms(state, ap, 0)) { 698 if (!check_perms(state, ap, 0)) {
699 if (sop == 0) { 699 if (sop == 0) {
700 return SECTION_PERMISSION_FAULT; 700 return SECTION_PERMISSION_FAULT;
701 } else { 701 } else {
702 return SUBPAGE_PERMISSION_FAULT; 702 return SUBPAGE_PERMISSION_FAULT;
703 } 703 }
704 } 704 }
705 705
706#if 0 706#if 0
707 /* tlb check access */ 707 /* tlb check access */
708 fault = check_access (state, va, tlb, 0); 708 fault = check_access (state, va, tlb, 0);
709 if (fault) { 709 if (fault) {
710 DEBUG_LOG(ARM11, "check_access\n"); 710 DEBUG_LOG(ARM11, "check_access\n");
711 return fault; 711 return fault;
712 } 712 }
713#endif 713#endif
714#if 0 714#if 0
715 if (pa <= 0x502860ff && (pa + 1 << datatype) > 0x502860ff) { 715 if (pa <= 0x502860ff && (pa + 1 << datatype) > 0x502860ff) {
@@ -723,51 +723,51 @@ arm1176jzf_s_mmu_write (ARMul_State *state, ARMword va, ARMword data,
723 exit(-1); 723 exit(-1);
724 } 724 }
725#endif 725#endif
726 //insert_tlb(state, va, pa); 726 //insert_tlb(state, va, pa);
727skip_translation: 727skip_translation:
728 /* strex */ 728 /* strex */
729 if(((state->CurrInstr & 0x0FF000F0) == 0x01800090) || 729 if(((state->CurrInstr & 0x0FF000F0) == 0x01800090) ||
730 ((state->CurrInstr & 0x0FF000F0) == 0x01c00090)){ 730 ((state->CurrInstr & 0x0FF000F0) == 0x01c00090)){
731 /* failed , the address is monitord now. */ 731 /* failed , the address is monitord now. */
732 int dest_reg = (state->CurrInstr & 0xF000) >> 12; 732 int dest_reg = (state->CurrInstr & 0xF000) >> 12;
733 if((exclusive_detect(state, pa | (real_va & 3)) == 0) && (state->exclusive_access_state == 1)){ 733 if((exclusive_detect(state, pa | (real_va & 3)) == 0) && (state->exclusive_access_state == 1)){
734 remove_exclusive(state, pa | (real_va & 3)); 734 remove_exclusive(state, pa | (real_va & 3));
735 state->Reg[dest_reg] = 0; 735 state->Reg[dest_reg] = 0;
736 state->exclusive_access_state = 0; 736 state->exclusive_access_state = 0;
737 } 737 }
738 else{ 738 else{
739 state->Reg[dest_reg] = 1; 739 state->Reg[dest_reg] = 1;
740 //printf("In %s, try to strex a monitored address 0x%x\n", __FUNCTION__, pa); 740 //printf("In %s, try to strex a monitored address 0x%x\n", __FUNCTION__, pa);
741 return NO_FAULT; 741 return NO_FAULT;
742 } 742 }
743 } 743 }
744 744
745 if (datatype == ARM_BYTE_TYPE) { 745 if (datatype == ARM_BYTE_TYPE) {
746 /* mem_write_byte (state, 746 /* mem_write_byte (state,
747 (pa | (real_va & 3)), 747 (pa | (real_va & 3)),
748 data); 748 data);
749 */ 749 */
750 if(state->space.conf_obj != NULL) 750 if(state->space.conf_obj != NULL)
751 state->space.write(state->space.conf_obj, (pa | (real_va & 3)), &data, 1); 751 state->space.write(state->space.conf_obj, (pa | (real_va & 3)), &data, 1);
752 else 752 else
753 Memory::Write8((pa | (real_va & 3)), data); 753 Memory::Write8((pa | (real_va & 3)), data);
754 754
755 } else if (datatype == ARM_HALFWORD_TYPE) 755 } else if (datatype == ARM_HALFWORD_TYPE)
756 /* mem_write_halfword (state, 756 /* mem_write_halfword (state,
757 (pa | 757 (pa |
758 (real_va & 2)), 758 (real_va & 2)),
759 data); 759 data);
760 */ 760 */
761 if(state->space.conf_obj != NULL) 761 if(state->space.conf_obj != NULL)
762 state->space.write(state->space.conf_obj, (pa | (real_va & 3)), &data, 2); 762 state->space.write(state->space.conf_obj, (pa | (real_va & 3)), &data, 2);
763 else 763 else
764 Memory::Write16((pa | (real_va & 3)), data); 764 Memory::Write16((pa | (real_va & 3)), data);
765 else if (datatype == ARM_WORD_TYPE) 765 else if (datatype == ARM_WORD_TYPE)
766 /* mem_write_word (state, pa, data); */ 766 /* mem_write_word (state, pa, data); */
767 if(state->space.conf_obj != NULL) 767 if(state->space.conf_obj != NULL)
768 state->space.write(state->space.conf_obj, pa, &data, 4); 768 state->space.write(state->space.conf_obj, pa, &data, 4);
769 else 769 else
770 Memory::Write32(pa, data); 770 Memory::Write32(pa, data);
771#if 0 771#if 0
772 if (state->NumInstrs > 236403) { 772 if (state->NumInstrs > 236403) {
773 printf("write memory\n"); 773 printf("write memory\n");
@@ -777,23 +777,23 @@ skip_translation:
777#endif 777#endif
778finished_write: 778finished_write:
779#if DIFF_WRITE 779#if DIFF_WRITE
780 if(state->icounter > state->debug_icounter){ 780 if(state->icounter > state->debug_icounter){
781 if(state->CurrWrite >= 17 ){ 781 if(state->CurrWrite >= 17 ){
782 printf("Wrong write array, 0x%x", state->CurrWrite); 782 printf("Wrong write array, 0x%x", state->CurrWrite);
783 exit(-1); 783 exit(-1);
784 } 784 }
785 uint32 record_data = data; 785 uint32 record_data = data;
786 if(datatype == ARM_BYTE_TYPE) 786 if(datatype == ARM_BYTE_TYPE)
787 record_data &= 0xFF; 787 record_data &= 0xFF;
788 if(datatype == ARM_HALFWORD_TYPE) 788 if(datatype == ARM_HALFWORD_TYPE)
789 record_data &= 0xFFFF; 789 record_data &= 0xFFFF;
790 790
791 state->WriteAddr[state->CurrWrite] = pa | (real_va & 3); 791 state->WriteAddr[state->CurrWrite] = pa | (real_va & 3);
792 state->WriteData[state->CurrWrite] = record_data; 792 state->WriteData[state->CurrWrite] = record_data;
793 state->WritePc[state->CurrWrite] = state->Reg[15]; 793 state->WritePc[state->CurrWrite] = state->Reg[15];
794 state->CurrWrite++; 794 state->CurrWrite++;
795 //printf("In %s, pc=0x%x, addr=0x%x, data=0x%x, CFlag=%d\n", __FUNCTION__, state->Reg[15], pa | (real_va & 3), record_data, state->CFlag); 795 //printf("In %s, pc=0x%x, addr=0x%x, data=0x%x, CFlag=%d\n", __FUNCTION__, state->Reg[15], pa | (real_va & 3), record_data, state->CFlag);
796 } 796 }
797#endif 797#endif
798 798
799 return NO_FAULT; 799 return NO_FAULT;
@@ -802,331 +802,331 @@ finished_write:
802ARMword 802ARMword
803arm1176jzf_s_mmu_mrc (ARMul_State *state, ARMword instr, ARMword *value) 803arm1176jzf_s_mmu_mrc (ARMul_State *state, ARMword instr, ARMword *value)
804{ 804{
805 int creg = BITS (16, 19) & 0xf; 805 int creg = BITS (16, 19) & 0xf;
806 int OPC_1 = BITS (21, 23) & 0x7; 806 int OPC_1 = BITS (21, 23) & 0x7;
807 int OPC_2 = BITS (5, 7) & 0x7; 807 int OPC_2 = BITS (5, 7) & 0x7;
808 ARMword data; 808 ARMword data;
809 809
810 switch (creg) { 810 switch (creg) {
811 case MMU_ID: 811 case MMU_ID:
812 if (OPC_2 == 0) { 812 if (OPC_2 == 0) {
813 data = state->cpu->cpu_val; 813 data = state->cpu->cpu_val;
814 } else if (OPC_2 == 1) { 814 } else if (OPC_2 == 1) {
815 /* Cache type: 815 /* Cache type:
816 * 000 0110 1 000 101 110 0 10 000 101 110 0 10 816 * 000 0110 1 000 101 110 0 10 000 101 110 0 10
817 * */ 817 * */
818 data = 0x0D172172; 818 data = 0x0D172172;
819 } 819 }
820 break; 820 break;
821 case MMU_CONTROL: 821 case MMU_CONTROL:
822 /* 822 /*
823 * 6:3 read as 1 823 * 6:3 read as 1
824 * 10 read as 0 824 * 10 read as 0
825 * 18,16 read as 1 825 * 18,16 read as 1
826 * */ 826 * */
827 data = (state->mmu.control | 0x50078) & 0xFFFFFBFF; 827 data = (state->mmu.control | 0x50078) & 0xFFFFFBFF;
828 break; 828 break;
829 case MMU_TRANSLATION_TABLE_BASE: 829 case MMU_TRANSLATION_TABLE_BASE:
830#if 0 830#if 0
831 data = state->mmu.translation_table_base; 831 data = state->mmu.translation_table_base;
832#endif 832#endif
833 switch (OPC_2) { 833 switch (OPC_2) {
834 case 0: 834 case 0:
835 data = state->mmu.translation_table_base0; 835 data = state->mmu.translation_table_base0;
836 break; 836 break;
837 case 1: 837 case 1:
838 data = state->mmu.translation_table_base1; 838 data = state->mmu.translation_table_base1;
839 break; 839 break;
840 case 2: 840 case 2:
841 data = state->mmu.translation_table_ctrl; 841 data = state->mmu.translation_table_ctrl;
842 break; 842 break;
843 default: 843 default:
844 printf ("mmu_mrc read UNKNOWN - p15 c2 opcode2 %d\n", OPC_2); 844 printf ("mmu_mrc read UNKNOWN - p15 c2 opcode2 %d\n", OPC_2);
845 break; 845 break;
846 } 846 }
847 break; 847 break;
848 case MMU_DOMAIN_ACCESS_CONTROL: 848 case MMU_DOMAIN_ACCESS_CONTROL:
849 data = state->mmu.domain_access_control; 849 data = state->mmu.domain_access_control;
850 break; 850 break;
851 case MMU_FAULT_STATUS: 851 case MMU_FAULT_STATUS:
852 /* OPC_2 = 0: data FSR value 852 /* OPC_2 = 0: data FSR value
853 * */ 853 * */
854 if (OPC_2 == 0) 854 if (OPC_2 == 0)
855 data = state->mmu.fault_status; 855 data = state->mmu.fault_status;
856 if (OPC_2 == 1) 856 if (OPC_2 == 1)
857 data = state->mmu.fault_statusi; 857 data = state->mmu.fault_statusi;
858 break; 858 break;
859 case MMU_FAULT_ADDRESS: 859 case MMU_FAULT_ADDRESS:
860 data = state->mmu.fault_address; 860 data = state->mmu.fault_address;
861 break; 861 break;
862 case MMU_PID: 862 case MMU_PID:
863 //data = state->mmu.process_id; 863 //data = state->mmu.process_id;
864 if(OPC_2 == 0) 864 if(OPC_2 == 0)
865 data = state->mmu.process_id; 865 data = state->mmu.process_id;
866 else if(OPC_2 == 1) 866 else if(OPC_2 == 1)
867 data = state->mmu.context_id; 867 data = state->mmu.context_id;
868 else if(OPC_2 == 3){ 868 else if(OPC_2 == 3){
869 data = state->mmu.thread_uro_id; 869 data = state->mmu.thread_uro_id;
870 } 870 }
871 else{ 871 else{
872 printf ("mmu_mcr read UNKNOWN - reg %d\n", creg); 872 printf ("mmu_mcr read UNKNOWN - reg %d\n", creg);
873 } 873 }
874 //printf("SKYEYE In %s, read pid 0x%x, OPC_2 %d, instr=0x%x\n", __FUNCTION__, data, OPC_2, instr); 874 //printf("SKYEYE In %s, read pid 0x%x, OPC_2 %d, instr=0x%x\n", __FUNCTION__, data, OPC_2, instr);
875 //exit(-1); 875 //exit(-1);
876 break; 876 break;
877 default: 877 default:
878 printf ("mmu_mrc read UNKNOWN - reg %d\n", creg); 878 printf ("mmu_mrc read UNKNOWN - reg %d\n", creg);
879 data = 0; 879 data = 0;
880 break; 880 break;
881 } 881 }
882/* printf("\t\t\t\t\tpc = 0x%08x\n", state->Reg[15]); */ 882/* printf("\t\t\t\t\tpc = 0x%08x\n", state->Reg[15]); */
883 *value = data; 883 *value = data;
884 return data; 884 return data;
885} 885}
886 886
887 887
888static ARMword 888static ARMword
889arm1176jzf_s_mmu_mcr (ARMul_State *state, ARMword instr, ARMword value) 889arm1176jzf_s_mmu_mcr (ARMul_State *state, ARMword instr, ARMword value)
890{ 890{
891 int creg = BITS (16, 19) & 0xf; 891 int creg = BITS (16, 19) & 0xf;
892 int CRm = BITS (0, 3) & 0xf; 892 int CRm = BITS (0, 3) & 0xf;
893 int OPC_1 = BITS (21, 23) & 0x7; 893 int OPC_1 = BITS (21, 23) & 0x7;
894 int OPC_2 = BITS (5, 7) & 0x7; 894 int OPC_2 = BITS (5, 7) & 0x7;
895 if (!strncmp (state->cpu->cpu_arch_name, "armv6", 5)) { 895 if (!strncmp (state->cpu->cpu_arch_name, "armv6", 5)) {
896 switch (creg) { 896 switch (creg) {
897 case MMU_CONTROL: 897 case MMU_CONTROL:
898 /* 898 /*
899 * 6:3 read as 1 899 * 6:3 read as 1
900 * 10 read as 0 900 * 10 read as 0
901 * 18,16 read as 1 901 * 18,16 read as 1
902 * */ 902 * */
903 if(OPC_2 == 0) 903 if(OPC_2 == 0)
904 state->mmu.control = (value | 0x50078) & 0xFFFFFBFF; 904 state->mmu.control = (value | 0x50078) & 0xFFFFFBFF;
905 else if(OPC_2 == 1) 905 else if(OPC_2 == 1)
906 state->mmu.auxiliary_control = value; 906 state->mmu.auxiliary_control = value;
907 else if(OPC_2 == 2) 907 else if(OPC_2 == 2)
908 state->mmu.coprocessor_access_control = value; 908 state->mmu.coprocessor_access_control = value;
909 else 909 else
910 fprintf(stderr, "In %s, wrong OPC_2 %d\n", __FUNCTION__, OPC_2); 910 fprintf(stderr, "In %s, wrong OPC_2 %d\n", __FUNCTION__, OPC_2);
911 break; 911 break;
912 case MMU_TRANSLATION_TABLE_BASE: 912 case MMU_TRANSLATION_TABLE_BASE:
913 switch (OPC_2) { 913 switch (OPC_2) {
914 /* int i; */ 914 /* int i; */
915 case 0: 915 case 0:
916#if 0 916#if 0
917 /* TTBR0 */ 917 /* TTBR0 */
918 if (state->mmu.translation_table_ctrl & 0x7) { 918 if (state->mmu.translation_table_ctrl & 0x7) {
919 for (i = 0; i <= state->mmu.translation_table_ctrl; i++) 919 for (i = 0; i <= state->mmu.translation_table_ctrl; i++)
920 state->mmu.translation_table_base0 &= ~(1 << (5 + i)); 920 state->mmu.translation_table_base0 &= ~(1 << (5 + i));
921 } 921 }
922#endif 922#endif
923 state->mmu.translation_table_base0 = (value); 923 state->mmu.translation_table_base0 = (value);
924 break; 924 break;
925 case 1: 925 case 1:
926#if 0 926#if 0
927 /* TTBR1 */ 927 /* TTBR1 */
928 if (state->mmu.translation_table_ctrl & 0x7) { 928 if (state->mmu.translation_table_ctrl & 0x7) {
929 for (i = 0; i <= state->mmu.translation_table_ctrl; i++) 929 for (i = 0; i <= state->mmu.translation_table_ctrl; i++)
930 state->mmu.translation_table_base1 &= 1 << (5 + i); 930 state->mmu.translation_table_base1 &= 1 << (5 + i);
931 } 931 }
932#endif 932#endif
933 state->mmu.translation_table_base1 = (value); 933 state->mmu.translation_table_base1 = (value);
934 break; 934 break;
935 case 2: 935 case 2:
936 /* TTBC */ 936 /* TTBC */
937 state->mmu.translation_table_ctrl = value & 0x7; 937 state->mmu.translation_table_ctrl = value & 0x7;
938 break; 938 break;
939 default: 939 default:
940 printf ("mmu_mcr wrote UNKNOWN - cp15 c2 opcode2 %d\n", OPC_2); 940 printf ("mmu_mcr wrote UNKNOWN - cp15 c2 opcode2 %d\n", OPC_2);
941 break; 941 break;
942 } 942 }
943 //printf("SKYEYE In %s, write TLB_BASE 0x%x OPC_2=%d instr=0x%x\n", __FUNCTION__, value, OPC_2, instr); 943 //printf("SKYEYE In %s, write TLB_BASE 0x%x OPC_2=%d instr=0x%x\n", __FUNCTION__, value, OPC_2, instr);
944 //invalidate_all_tlb(state); 944 //invalidate_all_tlb(state);
945 break; 945 break;
946 case MMU_DOMAIN_ACCESS_CONTROL: 946 case MMU_DOMAIN_ACCESS_CONTROL:
947 /* printf("mmu_mcr wrote DACR "); */ 947 /* printf("mmu_mcr wrote DACR "); */
948 state->mmu.domain_access_control = value; 948 state->mmu.domain_access_control = value;
949 break; 949 break;
950 950
951 case MMU_FAULT_STATUS: 951 case MMU_FAULT_STATUS:
952 if (OPC_2 == 0) 952 if (OPC_2 == 0)
953 state->mmu.fault_status = value & 0xFF; 953 state->mmu.fault_status = value & 0xFF;
954 if (OPC_2 == 1) { 954 if (OPC_2 == 1) {
955 printf("set fault status instr\n"); 955 printf("set fault status instr\n");
956 } 956 }
957 break; 957 break;
958 case MMU_FAULT_ADDRESS: 958 case MMU_FAULT_ADDRESS:
959 state->mmu.fault_address = value; 959 state->mmu.fault_address = value;
960 break; 960 break;
961 961
962 case MMU_CACHE_OPS: 962 case MMU_CACHE_OPS:
963 break; 963 break;
964 case MMU_TLB_OPS: 964 case MMU_TLB_OPS:
965 { 965 {
966 switch(CRm){ 966 switch(CRm){
967 case 5: /* ITLB */ 967 case 5: /* ITLB */
968 { 968 {
969 switch(OPC_2){ 969 switch(OPC_2){
970 case 0: /* invalidate all */ 970 case 0: /* invalidate all */
971 //invalidate_all_tlb(state); 971 //invalidate_all_tlb(state);
972 break; 972 break;
973 case 1: /* invalidate by MVA */ 973 case 1: /* invalidate by MVA */
974 //invalidate_by_mva(state, value); 974 //invalidate_by_mva(state, value);
975 break; 975 break;
976 case 2: /* invalidate by asid */ 976 case 2: /* invalidate by asid */
977 //invalidate_by_asid(state, value); 977 //invalidate_by_asid(state, value);
978 break; 978 break;
979 default: 979 default:
980 printf ("mmu_mcr wrote UNKNOWN - reg %d\n", creg); 980 printf ("mmu_mcr wrote UNKNOWN - reg %d\n", creg);
981 break; 981 break;
982 } 982 }
983 break; 983 break;
984 } 984 }
985 case 6: /* DTLB */ 985 case 6: /* DTLB */
986 { 986 {
987 switch(OPC_2){ 987 switch(OPC_2){
988 case 0: /* invalidate all */ 988 case 0: /* invalidate all */
989 //invalidate_all_tlb(state); 989 //invalidate_all_tlb(state);
990 break; 990 break;
991 case 1: /* invalidate by MVA */ 991 case 1: /* invalidate by MVA */
992 //invalidate_by_mva(state, value); 992 //invalidate_by_mva(state, value);
993 break; 993 break;
994 case 2: /* invalidate by asid */ 994 case 2: /* invalidate by asid */
995 //invalidate_by_asid(state, value); 995 //invalidate_by_asid(state, value);
996 break; 996 break;
997 default: 997 default:
998 printf ("mmu_mcr wrote UNKNOWN - reg %d\n", creg); 998 printf ("mmu_mcr wrote UNKNOWN - reg %d\n", creg);
999 break; 999 break;
1000 } 1000 }
1001 break; 1001 break;
1002 } 1002 }
1003 case 7: /* Unified TLB */ 1003 case 7: /* Unified TLB */
1004 { 1004 {
1005 switch(OPC_2){ 1005 switch(OPC_2){
1006 case 0: /* invalidate all */ 1006 case 0: /* invalidate all */
1007 //invalidate_all_tlb(state); 1007 //invalidate_all_tlb(state);
1008 break; 1008 break;
1009 case 1: /* invalidate by MVA */ 1009 case 1: /* invalidate by MVA */
1010 //invalidate_by_mva(state, value); 1010 //invalidate_by_mva(state, value);
1011 break; 1011 break;
1012 case 2: /* invalidate by asid */ 1012 case 2: /* invalidate by asid */
1013 //invalidate_by_asid(state, value); 1013 //invalidate_by_asid(state, value);
1014 break; 1014 break;
1015 default: 1015 default:
1016 printf ("mmu_mcr wrote UNKNOWN - reg %d\n", creg); 1016 printf ("mmu_mcr wrote UNKNOWN - reg %d\n", creg);
1017 break; 1017 break;
1018 } 1018 }
1019 break; 1019 break;
1020 } 1020 }
1021 1021
1022 default: 1022 default:
1023 printf ("mmu_mcr wrote UNKNOWN - reg %d, CRm=%d\n", creg, CRm); 1023 printf ("mmu_mcr wrote UNKNOWN - reg %d, CRm=%d\n", creg, CRm);
1024 break; 1024 break;
1025 } 1025 }
1026 //printf("SKYEYE In %s, write TLB 0x%x OPC_1=%d, OPC_2=%d , CRm=%d instr=0x%x\n", __FUNCTION__, value, OPC_1, OPC_2, CRm, instr); 1026 //printf("SKYEYE In %s, write TLB 0x%x OPC_1=%d, OPC_2=%d , CRm=%d instr=0x%x\n", __FUNCTION__, value, OPC_1, OPC_2, CRm, instr);
1027 } 1027 }
1028 break; 1028 break;
1029 case MMU_CACHE_LOCKDOWN: 1029 case MMU_CACHE_LOCKDOWN:
1030 /* 1030 /*
1031 * FIXME: cache lock down*/ 1031 * FIXME: cache lock down*/
1032 break; 1032 break;
1033 case MMU_TLB_LOCKDOWN: 1033 case MMU_TLB_LOCKDOWN:
1034 printf("SKYEYE In %s, write TLB_LOCKDOWN 0x%x OPC_2=%d instr=0x%x\n", __FUNCTION__, value, OPC_2, instr); 1034 printf("SKYEYE In %s, write TLB_LOCKDOWN 0x%x OPC_2=%d instr=0x%x\n", __FUNCTION__, value, OPC_2, instr);
1035 /* FIXME:tlb lock down */ 1035 /* FIXME:tlb lock down */
1036 break; 1036 break;
1037 case MMU_PID: 1037 case MMU_PID:
1038 //printf("SKYEYE In %s, write pid 0x%x OPC_2=%d instr=0x%x\n", __FUNCTION__, value, OPC_2, instr); 1038 //printf("SKYEYE In %s, write pid 0x%x OPC_2=%d instr=0x%x\n", __FUNCTION__, value, OPC_2, instr);
1039 //state->mmu.process_id = value; 1039 //state->mmu.process_id = value;
1040 /*0:24 should be zero. */ 1040 /*0:24 should be zero. */
1041 //state->mmu.process_id = value & 0xfe000000; 1041 //state->mmu.process_id = value & 0xfe000000;
1042 if(OPC_2 == 0) 1042 if(OPC_2 == 0)
1043 state->mmu.process_id = value; 1043 state->mmu.process_id = value;
1044 else if(OPC_2 == 1) 1044 else if(OPC_2 == 1)
1045 state->mmu.context_id = value; 1045 state->mmu.context_id = value;
1046 else if(OPC_2 == 3){ 1046 else if(OPC_2 == 3){
1047 state->mmu.thread_uro_id = value; 1047 state->mmu.thread_uro_id = value;
1048 } 1048 }
1049 else{ 1049 else{
1050 printf ("mmu_mcr wrote UNKNOWN - reg %d\n", creg); 1050 printf ("mmu_mcr wrote UNKNOWN - reg %d\n", creg);
1051 } 1051 }
1052 break; 1052 break;
1053 1053
1054 default: 1054 default:
1055 printf ("mmu_mcr wrote UNKNOWN - reg %d\n", creg); 1055 printf ("mmu_mcr wrote UNKNOWN - reg %d\n", creg);
1056 break; 1056 break;
1057 } 1057 }
1058 } 1058 }
1059 1059
1060 return No_exp; 1060 return No_exp;
1061} 1061}
1062 1062
1063///* teawater add for arm2x86 2005.06.19------------------------------------------- */ 1063///* teawater add for arm2x86 2005.06.19------------------------------------------- */
1064//static int 1064//static int
1065//arm1176jzf_s_mmu_v2p_dbct (ARMul_State *state, ARMword virt_addr, 1065//arm1176jzf_s_mmu_v2p_dbct (ARMul_State *state, ARMword virt_addr,
1066// ARMword *phys_addr) 1066// ARMword *phys_addr)
1067//{ 1067//{
1068// fault_t fault; 1068// fault_t fault;
1069// int ap, sop; 1069// int ap, sop;
1070// 1070//
1071// ARMword perm; /* physical addr access permissions */ 1071// ARMword perm; /* physical addr access permissions */
1072// virt_addr = mmu_pid_va_map (virt_addr); 1072// virt_addr = mmu_pid_va_map (virt_addr);
1073// if (MMU_Enabled) { 1073// if (MMU_Enabled) {
1074// 1074//
1075// /*align check */ 1075// /*align check */
1076// if ((virt_addr & (WORD_SIZE - 1)) && MMU_Aligned) { 1076// if ((virt_addr & (WORD_SIZE - 1)) && MMU_Aligned) {
1077// DEBUG_LOG(ARM11, "align\n"); 1077// DEBUG_LOG(ARM11, "align\n");
1078// return ALIGNMENT_FAULT; 1078// return ALIGNMENT_FAULT;
1079// } else 1079// } else
1080// virt_addr &= ~(WORD_SIZE - 1); 1080// virt_addr &= ~(WORD_SIZE - 1);
1081// 1081//
1082// /*translate tlb */ 1082// /*translate tlb */
1083// fault = mmu_translate (state, virt_addr, phys_addr, &ap, &sop); 1083// fault = mmu_translate (state, virt_addr, phys_addr, &ap, &sop);
1084// if (fault) { 1084// if (fault) {
1085// DEBUG_LOG(ARM11, "translate\n"); 1085// DEBUG_LOG(ARM11, "translate\n");
1086// return fault; 1086// return fault;
1087// } 1087// }
1088// 1088//
1089// /* permission check */ 1089// /* permission check */
1090// if (!check_perms(state, ap, 1)) { 1090// if (!check_perms(state, ap, 1)) {
1091// if (sop == 0) { 1091// if (sop == 0) {
1092// return SECTION_PERMISSION_FAULT; 1092// return SECTION_PERMISSION_FAULT;
1093// } else { 1093// } else {
1094// return SUBPAGE_PERMISSION_FAULT; 1094// return SUBPAGE_PERMISSION_FAULT;
1095// } 1095// }
1096// } 1096// }
1097//#if 0 1097//#if 0
1098// /*check access */ 1098// /*check access */
1099// fault = check_access (state, virt_addr, tlb, 1); 1099// fault = check_access (state, virt_addr, tlb, 1);
1100// if (fault) { 1100// if (fault) {
1101// DEBUG_LOG(ARM11, "check_fault\n"); 1101// DEBUG_LOG(ARM11, "check_fault\n");
1102// return fault; 1102// return fault;
1103// } 1103// }
1104//#endif 1104//#endif
1105// } 1105// }
1106// 1106//
1107// if (MMU_Disabled) { 1107// if (MMU_Disabled) {
1108// *phys_addr = virt_addr; 1108// *phys_addr = virt_addr;
1109// } 1109// }
1110// 1110//
1111// return 0; 1111// return 0;
1112//} 1112//}
1113 1113
1114/* AJ2D-------------------------------------------------------------------------- */ 1114/* AJ2D-------------------------------------------------------------------------- */
1115 1115
1116/*arm1176jzf-s mmu_ops_t*/ 1116/*arm1176jzf-s mmu_ops_t*/
1117mmu_ops_t arm1176jzf_s_mmu_ops = { 1117mmu_ops_t arm1176jzf_s_mmu_ops = {
1118 arm1176jzf_s_mmu_init, 1118 arm1176jzf_s_mmu_init,
1119 arm1176jzf_s_mmu_exit, 1119 arm1176jzf_s_mmu_exit,
1120 arm1176jzf_s_mmu_read_byte, 1120 arm1176jzf_s_mmu_read_byte,
1121 arm1176jzf_s_mmu_write_byte, 1121 arm1176jzf_s_mmu_write_byte,
1122 arm1176jzf_s_mmu_read_halfword, 1122 arm1176jzf_s_mmu_read_halfword,
1123 arm1176jzf_s_mmu_write_halfword, 1123 arm1176jzf_s_mmu_write_halfword,
1124 arm1176jzf_s_mmu_read_word, 1124 arm1176jzf_s_mmu_read_word,
1125 arm1176jzf_s_mmu_write_word, 1125 arm1176jzf_s_mmu_write_word,
1126 arm1176jzf_s_mmu_load_instr, 1126 arm1176jzf_s_mmu_load_instr,
1127 arm1176jzf_s_mmu_mcr, 1127 arm1176jzf_s_mmu_mcr,
1128 arm1176jzf_s_mmu_mrc 1128 arm1176jzf_s_mmu_mrc
1129/* teawater add for arm2x86 2005.06.19------------------------------------------- */ 1129/* teawater add for arm2x86 2005.06.19------------------------------------------- */
1130/* arm1176jzf_s_mmu_v2p_dbct, */ 1130/* arm1176jzf_s_mmu_v2p_dbct, */
1131/* AJ2D-------------------------------------------------------------------------- */ 1131/* AJ2D-------------------------------------------------------------------------- */
1132}; 1132};
diff --git a/src/core/src/arm/mmu/arm1176jzf_s_mmu.h b/src/core/src/arm/mmu/arm1176jzf_s_mmu.h
index 62097222c..299c6b46b 100644
--- a/src/core/src/arm/mmu/arm1176jzf_s_mmu.h
+++ b/src/core/src/arm/mmu/arm1176jzf_s_mmu.h
@@ -22,12 +22,12 @@
22#if 0 22#if 0
23typedef struct arm1176jzf-s_mmu_s 23typedef struct arm1176jzf-s_mmu_s
24{ 24{
25 tlb_t i_tlb; 25 tlb_t i_tlb;
26 cache_t i_cache; 26 cache_t i_cache;
27 27
28 tlb_t d_tlb; 28 tlb_t d_tlb;
29 cache_t d_cache; 29 cache_t d_cache;
30 wb_t wb_t; 30 wb_t wb_t;
31} arm1176jzf-s_mmu_t; 31} arm1176jzf-s_mmu_t;
32#endif 32#endif
33extern mmu_ops_t arm1176jzf_s_mmu_ops; 33extern mmu_ops_t arm1176jzf_s_mmu_ops;
diff --git a/src/core/src/arm/mmu/cache.h b/src/core/src/arm/mmu/cache.h
index b26d92693..d308d9b87 100644
--- a/src/core/src/arm/mmu/cache.h
+++ b/src/core/src/arm/mmu/cache.h
@@ -3,85 +3,85 @@
3 3
4typedef struct cache_line_t 4typedef struct cache_line_t
5{ 5{
6 ARMword tag; /* cache line align address | 6 ARMword tag; /* cache line align address |
7 bit2: last half dirty 7 bit2: last half dirty
8 bit1: first half dirty 8 bit1: first half dirty
9 bit0: cache valid flag 9 bit0: cache valid flag
10 */ 10 */
11 ARMword pa; /*physical address */ 11 ARMword pa; /*physical address */
12 ARMword *data; /*array of cached data */ 12 ARMword *data; /*array of cached data */
13} cache_line_t; 13} cache_line_t;
14#define TAG_VALID_FLAG 0x00000001 14#define TAG_VALID_FLAG 0x00000001
15#define TAG_FIRST_HALF_DIRTY 0x00000002 15#define TAG_FIRST_HALF_DIRTY 0x00000002
16#define TAG_LAST_HALF_DIRTY 0x00000004 16#define TAG_LAST_HALF_DIRTY 0x00000004
17 17
18/*cache set association*/ 18/*cache set association*/
19typedef struct cache_set_s 19typedef struct cache_set_s
20{ 20{
21 cache_line_t *lines; 21 cache_line_t *lines;
22 int cycle; 22 int cycle;
23} cache_set_t; 23} cache_set_t;
24 24
25enum 25enum
26{ 26{
27 CACHE_WRITE_BACK, 27 CACHE_WRITE_BACK,
28 CACHE_WRITE_THROUGH, 28 CACHE_WRITE_THROUGH,
29}; 29};
30 30
31typedef struct cache_s 31typedef struct cache_s
32{ 32{
33 int width; /*bytes in a line */ 33 int width; /*bytes in a line */
34 int way; /*way of set asscociate */ 34 int way; /*way of set asscociate */
35 int set; /*num of set */ 35 int set; /*num of set */
36 int w_mode; /*write back or write through */ 36 int w_mode; /*write back or write through */
37 //int a_mode; /*alloc mode: random or round-bin*/ 37 //int a_mode; /*alloc mode: random or round-bin*/
38 cache_set_t *sets; 38 cache_set_t *sets;
39 /**/} cache_s; 39 /**/} cache_s;
40 40
41typedef struct cache_desc_s 41typedef struct cache_desc_s
42{ 42{
43 int width; 43 int width;
44 int way; 44 int way;
45 int set; 45 int set;
46 int w_mode; 46 int w_mode;
47// int a_mode; 47// int a_mode;
48} cache_desc_t; 48} cache_desc_t;
49 49
50 50
51/*virtual address to cache set index*/ 51/*virtual address to cache set index*/
52#define va_cache_set(va, cache_t) \ 52#define va_cache_set(va, cache_t) \
53 (((va) / (cache_t)->width) & ((cache_t)->set - 1)) 53 (((va) / (cache_t)->width) & ((cache_t)->set - 1))
54/*virtual address to cahce line aligned*/ 54/*virtual address to cahce line aligned*/
55#define va_cache_align(va, cache_t) \ 55#define va_cache_align(va, cache_t) \
56 ((va) & ~((cache_t)->width - 1)) 56 ((va) & ~((cache_t)->width - 1))
57/*virtaul address to cache line word index*/ 57/*virtaul address to cache line word index*/
58#define va_cache_index(va, cache_t) \ 58#define va_cache_index(va, cache_t) \
59 (((va) & ((cache_t)->width - 1)) >> WORD_SHT) 59 (((va) & ((cache_t)->width - 1)) >> WORD_SHT)
60 60
61/*see Page 558 in arm manual*/ 61/*see Page 558 in arm manual*/
62/*set/index format value to cache set value*/ 62/*set/index format value to cache set value*/
63#define index_cache_set(index, cache_t) \ 63#define index_cache_set(index, cache_t) \
64 (((index) / (cache_t)->width) & ((cache_t)->set - 1)) 64 (((index) / (cache_t)->width) & ((cache_t)->set - 1))
65 65
66/*************************cache********************/ 66/*************************cache********************/
67/* mmu cache init 67/* mmu cache init
68 * 68 *
69 * @cache_t :cache_t to init 69 * @cache_t :cache_t to init
70 * @width :cache line width in byte 70 * @width :cache line width in byte
71 * @way :way of each cache set 71 * @way :way of each cache set
72 * @set :cache set num 72 * @set :cache set num
73 * @w_mode :cache w_mode 73 * @w_mode :cache w_mode
74 * 74 *
75 * $ -1: error 75 * $ -1: error
76 * 0: sucess 76 * 0: sucess
77 */ 77 */
78int 78int
79mmu_cache_init (cache_s * cache_t, int width, int way, int set, int w_mode); 79mmu_cache_init (cache_s * cache_t, int width, int way, int set, int w_mode);
80 80
81/* free a cache_t's inner data, the ptr self is not freed, 81/* free a cache_t's inner data, the ptr self is not freed,
82 * when needed do like below: 82 * when needed do like below:
83 * mmu_cache_exit(cache); 83 * mmu_cache_exit(cache);
84 * free(cache_t); 84 * free(cache_t);
85 * 85 *
86 * @cache_t : the cache_t to free 86 * @cache_t : the cache_t to free
87 */ 87 */
@@ -89,40 +89,40 @@ void mmu_cache_exit (cache_s * cache_t);
89 89
90/* mmu cache search 90/* mmu cache search
91 * 91 *
92 * @state :ARMul_State 92 * @state :ARMul_State
93 * @cache_t :cache_t to search 93 * @cache_t :cache_t to search
94 * @va :virtual address 94 * @va :virtual address
95 * 95 *
96 * $ NULL: no cache match 96 * $ NULL: no cache match
97 * cache :cache matched 97 * cache :cache matched
98 * */ 98 * */
99cache_line_t *mmu_cache_search (ARMul_State * state, cache_s * cache_t, 99cache_line_t *mmu_cache_search (ARMul_State * state, cache_s * cache_t,
100 ARMword va); 100 ARMword va);
101 101
102/* mmu cache search by set/index 102/* mmu cache search by set/index
103 * 103 *
104 * @state :ARMul_State 104 * @state :ARMul_State
105 * @cache_t :cache_t to search 105 * @cache_t :cache_t to search
106 * @index :set/index value. 106 * @index :set/index value.
107 * 107 *
108 * $ NULL: no cache match 108 * $ NULL: no cache match
109 * cache :cache matched 109 * cache :cache matched
110 * */ 110 * */
111 111
112cache_line_t *mmu_cache_search_by_index (ARMul_State * state, 112cache_line_t *mmu_cache_search_by_index (ARMul_State * state,
113 cache_s * cache_t, ARMword index); 113 cache_s * cache_t, ARMword index);
114 114
115/* mmu cache alloc 115/* mmu cache alloc
116 * 116 *
117 * @state :ARMul_State 117 * @state :ARMul_State
118 * @cache_t :cache_t to alloc from 118 * @cache_t :cache_t to alloc from
119 * @va :virtual address that require cache alloc, need not cache aligned 119 * @va :virtual address that require cache alloc, need not cache aligned
120 * @pa :physical address of va 120 * @pa :physical address of va
121 * 121 *
122 * $ cache_alloced, always alloc OK 122 * $ cache_alloced, always alloc OK
123 */ 123 */
124cache_line_t *mmu_cache_alloc (ARMul_State * state, cache_s * cache_t, 124cache_line_t *mmu_cache_alloc (ARMul_State * state, cache_s * cache_t,
125 ARMword va, ARMword pa); 125 ARMword va, ARMword pa);
126 126
127/* mmu_cache_write_back write cache data to memory 127/* mmu_cache_write_back write cache data to memory
128 * 128 *
@@ -132,31 +132,31 @@ cache_line_t *mmu_cache_alloc (ARMul_State * state, cache_s * cache_t,
132 */ 132 */
133void 133void
134mmu_cache_write_back (ARMul_State * state, cache_s * cache_t, 134mmu_cache_write_back (ARMul_State * state, cache_s * cache_t,
135 cache_line_t * cache); 135 cache_line_t * cache);
136 136
137/* mmu_cache_clean: clean a cache of va in cache_t 137/* mmu_cache_clean: clean a cache of va in cache_t
138 * 138 *
139 * @state :ARMul_State 139 * @state :ARMul_State
140 * @cache_t :cache_t to clean 140 * @cache_t :cache_t to clean
141 * @va :virtaul address 141 * @va :virtaul address
142 */ 142 */
143void mmu_cache_clean (ARMul_State * state, cache_s * cache_t, ARMword va); 143void mmu_cache_clean (ARMul_State * state, cache_s * cache_t, ARMword va);
144void 144void
145mmu_cache_clean_by_index (ARMul_State * state, cache_s * cache_t, 145mmu_cache_clean_by_index (ARMul_State * state, cache_s * cache_t,
146 ARMword index); 146 ARMword index);
147 147
148/* mmu_cache_invalidate : invalidate a cache of va 148/* mmu_cache_invalidate : invalidate a cache of va
149 * 149 *
150 * @state :ARMul_State 150 * @state :ARMul_State
151 * @cache_t :cache_t to invalid 151 * @cache_t :cache_t to invalid
152 * @va :virt_addr to invalid 152 * @va :virt_addr to invalid
153 */ 153 */
154void 154void
155mmu_cache_invalidate (ARMul_State * state, cache_s * cache_t, ARMword va); 155mmu_cache_invalidate (ARMul_State * state, cache_s * cache_t, ARMword va);
156 156
157void 157void
158mmu_cache_invalidate_by_index (ARMul_State * state, cache_s * cache_t, 158mmu_cache_invalidate_by_index (ARMul_State * state, cache_s * cache_t,
159 ARMword index); 159 ARMword index);
160 160
161void mmu_cache_invalidate_all (ARMul_State * state, cache_s * cache_t); 161void mmu_cache_invalidate_all (ARMul_State * state, cache_s * cache_t);
162 162
diff --git a/src/core/src/arm/mmu/rb.h b/src/core/src/arm/mmu/rb.h
index b2850eff9..7bf0ebb26 100644
--- a/src/core/src/arm/mmu/rb.h
+++ b/src/core/src/arm/mmu/rb.h
@@ -3,10 +3,10 @@
3 3
4enum rb_type_t 4enum rb_type_t
5{ 5{
6 RB_INVALID = 0, //invalid 6 RB_INVALID = 0, //invalid
7 RB_1, //1 word 7 RB_1, //1 word
8 RB_4, //4 word 8 RB_4, //4 word
9 RB_8, //8 word 9 RB_8, //8 word
10}; 10};
11 11
12/*bytes of each rb_type*/ 12/*bytes of each rb_type*/
@@ -15,21 +15,21 @@ extern ARMword rb_masks[];
15#define RB_WORD_NUM 8 15#define RB_WORD_NUM 8
16typedef struct rb_entry_s 16typedef struct rb_entry_s
17{ 17{
18 ARMword data[RB_WORD_NUM]; //array to store data 18 ARMword data[RB_WORD_NUM]; //array to store data
19 ARMword va; //first word va 19 ARMword va; //first word va
20 int type; //rb type 20 int type; //rb type
21 fault_t fault; //fault set by rb alloc 21 fault_t fault; //fault set by rb alloc
22} rb_entry_t; 22} rb_entry_t;
23 23
24typedef struct rb_s 24typedef struct rb_s
25{ 25{
26 int num; 26 int num;
27 rb_entry_t *entrys; 27 rb_entry_t *entrys;
28} rb_s; 28} rb_s;
29 29
30/*mmu_rb_init 30/*mmu_rb_init
31 * @rb_t :rb_t to init 31 * @rb_t :rb_t to init
32 * @num :number of entry 32 * @num :number of entry
33 * */ 33 * */
34int mmu_rb_init (rb_s * rb_t, int num); 34int mmu_rb_init (rb_s * rb_t, int num);
35 35
@@ -38,11 +38,11 @@ void mmu_rb_exit (rb_s * rb_t);
38 38
39 39
40/*mmu_rb_search 40/*mmu_rb_search
41 * @rb_t :rb_t to serach 41 * @rb_t :rb_t to serach
42 * @va :va address to math 42 * @va :va address to math
43 * 43 *
44 * $ NULL :not match 44 * $ NULL :not match
45 * NO-NULL: 45 * NO-NULL:
46 * */ 46 * */
47rb_entry_t *mmu_rb_search (rb_s * rb_t, ARMword va); 47rb_entry_t *mmu_rb_search (rb_s * rb_t, ARMword va);
48 48
@@ -50,6 +50,6 @@ rb_entry_t *mmu_rb_search (rb_s * rb_t, ARMword va);
50void mmu_rb_invalidate_entry (rb_s * rb_t, int i); 50void mmu_rb_invalidate_entry (rb_s * rb_t, int i);
51void mmu_rb_invalidate_all (rb_s * rb_t); 51void mmu_rb_invalidate_all (rb_s * rb_t);
52void mmu_rb_load (ARMul_State * state, rb_s * rb_t, int i_rb, 52void mmu_rb_load (ARMul_State * state, rb_s * rb_t, int i_rb,
53 int type, ARMword va); 53 int type, ARMword va);
54 54
55#endif /*_MMU_RB_H_*/ 55#endif /*_MMU_RB_H_*/
diff --git a/src/core/src/arm/mmu/tlb.h b/src/core/src/arm/mmu/tlb.h
index 949fcaade..938c01786 100644
--- a/src/core/src/arm/mmu/tlb.h
+++ b/src/core/src/arm/mmu/tlb.h
@@ -3,81 +3,81 @@
3 3
4typedef enum tlb_mapping_t 4typedef enum tlb_mapping_t
5{ 5{
6 TLB_INVALID = 0, 6 TLB_INVALID = 0,
7 TLB_SMALLPAGE = 1, 7 TLB_SMALLPAGE = 1,
8 TLB_LARGEPAGE = 2, 8 TLB_LARGEPAGE = 2,
9 TLB_SECTION = 3, 9 TLB_SECTION = 3,
10 TLB_ESMALLPAGE = 4, 10 TLB_ESMALLPAGE = 4,
11 TLB_TINYPAGE = 5 11 TLB_TINYPAGE = 5
12} tlb_mapping_t; 12} tlb_mapping_t;
13 13
14extern ARMword tlb_masks[]; 14extern ARMword tlb_masks[];
15 15
16/* Permissions bits in a TLB entry: 16/* Permissions bits in a TLB entry:
17 * 17 *
18 * 31 12 11 10 9 8 7 6 5 4 3 2 1 0 18 * 31 12 11 10 9 8 7 6 5 4 3 2 1 0
19 * +-------------+-----+-----+-----+-----+---+---+-------+ 19 * +-------------+-----+-----+-----+-----+---+---+-------+
20 * Page:| | ap3 | ap2 | ap1 | ap0 | C | B | | 20 * Page:| | ap3 | ap2 | ap1 | ap0 | C | B | |
21 * +-------------+-----+-----+-----+-----+---+---+-------+ 21 * +-------------+-----+-----+-----+-----+---+---+-------+
22 * 22 *
23 * 31 12 11 10 9 4 3 2 1 0 23 * 31 12 11 10 9 4 3 2 1 0
24 * +-------------+-----+-----------------+---+---+-------+ 24 * +-------------+-----+-----------------+---+---+-------+
25 * Section: | | AP | | C | B | | 25 * Section: | | AP | | C | B | |
26 * +-------------+-----+-----------------+---+---+-------+ 26 * +-------------+-----+-----------------+---+---+-------+
27 */ 27 */
28 28
29/* 29/*
30section: 30section:
31 section base address [31:20] 31 section base address [31:20]
32 AP - table 8-2, page 8-8 32 AP - table 8-2, page 8-8
33 domain 33 domain
34 C,B 34 C,B
35 35
36page: 36page:
37 page base address [31:16] or [31:12] 37 page base address [31:16] or [31:12]
38 ap[3:0] 38 ap[3:0]
39 domain (from L1) 39 domain (from L1)
40 C,B 40 C,B
41*/ 41*/
42 42
43 43
44typedef struct tlb_entry_t 44typedef struct tlb_entry_t
45{ 45{
46 ARMword virt_addr; 46 ARMword virt_addr;
47 ARMword phys_addr; 47 ARMword phys_addr;
48 ARMword perms; 48 ARMword perms;
49 ARMword domain; 49 ARMword domain;
50 tlb_mapping_t mapping; 50 tlb_mapping_t mapping;
51} tlb_entry_t; 51} tlb_entry_t;
52 52
53typedef struct tlb_s 53typedef struct tlb_s
54{ 54{
55 int num; /*num of tlb entry */ 55 int num; /*num of tlb entry */
56 int cycle; /*current tlb cycle */ 56 int cycle; /*current tlb cycle */
57 tlb_entry_t *entrys; 57 tlb_entry_t *entrys;
58} tlb_s; 58} tlb_s;
59 59
60 60
61#define tlb_c_flag(tlb) \ 61#define tlb_c_flag(tlb) \
62 ((tlb)->perms & 0x8) 62 ((tlb)->perms & 0x8)
63#define tlb_b_flag(tlb) \ 63#define tlb_b_flag(tlb) \
64 ((tlb)->perms & 0x4) 64 ((tlb)->perms & 0x4)
65 65
66#define tlb_va_to_pa(tlb, va) \ 66#define tlb_va_to_pa(tlb, va) \
67(\ 67(\
68 {\ 68 {\
69 ARMword mask = tlb_masks[tlb->mapping]; \ 69 ARMword mask = tlb_masks[tlb->mapping]; \
70 (tlb->phys_addr & mask) | (va & ~mask);\ 70 (tlb->phys_addr & mask) | (va & ~mask);\
71 }\ 71 }\
72) 72)
73 73
74fault_t 74fault_t
75check_access (ARMul_State * state, ARMword virt_addr, tlb_entry_t * tlb, 75check_access (ARMul_State * state, ARMword virt_addr, tlb_entry_t * tlb,
76 int read); 76 int read);
77 77
78fault_t 78fault_t
79translate (ARMul_State * state, ARMword virt_addr, tlb_s * tlb_t, 79translate (ARMul_State * state, ARMword virt_addr, tlb_s * tlb_t,
80 tlb_entry_t ** tlb); 80 tlb_entry_t ** tlb);
81 81
82int mmu_tlb_init (tlb_s * tlb_t, int num); 82int mmu_tlb_init (tlb_s * tlb_t, int num);
83 83
@@ -89,6 +89,6 @@ void
89mmu_tlb_invalidate_entry (ARMul_State * state, tlb_s * tlb_t, ARMword addr); 89mmu_tlb_invalidate_entry (ARMul_State * state, tlb_s * tlb_t, ARMword addr);
90 90
91tlb_entry_t *mmu_tlb_search (ARMul_State * state, tlb_s * tlb_t, 91tlb_entry_t *mmu_tlb_search (ARMul_State * state, tlb_s * tlb_t,
92 ARMword virt_addr); 92 ARMword virt_addr);
93 93
94#endif /*_MMU_TLB_H_*/ 94#endif /*_MMU_TLB_H_*/
diff --git a/src/core/src/arm/mmu/wb.h b/src/core/src/arm/mmu/wb.h
index 1b987afc3..8fb7de946 100644
--- a/src/core/src/arm/mmu/wb.h
+++ b/src/core/src/arm/mmu/wb.h
@@ -3,34 +3,34 @@
3 3
4typedef struct wb_entry_s 4typedef struct wb_entry_s
5{ 5{
6 ARMword pa; //phy_addr 6 ARMword pa; //phy_addr
7 ARMbyte *data; //data 7 ARMbyte *data; //data
8 int nb; //number byte to write 8 int nb; //number byte to write
9} wb_entry_t; 9} wb_entry_t;
10 10
11typedef struct wb_s 11typedef struct wb_s
12{ 12{
13 int num; //number of wb_entry 13 int num; //number of wb_entry
14 int nb; //number of byte of each entry 14 int nb; //number of byte of each entry
15 int first; // 15 int first; //
16 int last; // 16 int last; //
17 int used; // 17 int used; //
18 wb_entry_t *entrys; 18 wb_entry_t *entrys;
19} wb_s; 19} wb_s;
20 20
21typedef struct wb_desc_s 21typedef struct wb_desc_s
22{ 22{
23 int num; 23 int num;
24 int nb; 24 int nb;
25} wb_desc_t; 25} wb_desc_t;
26 26
27/* wb_init 27/* wb_init
28 * @wb_t :wb_t to init 28 * @wb_t :wb_t to init
29 * @num :num of entrys 29 * @num :num of entrys
30 * @nw :num of word of each entry 30 * @nw :num of word of each entry
31 * 31 *
32 * $ -1:error 32 * $ -1:error
33 * 0:ok 33 * 0:ok
34 * */ 34 * */
35int mmu_wb_init (wb_s * wb_t, int num, int nb); 35int mmu_wb_init (wb_s * wb_t, int num, int nb);
36 36
@@ -42,17 +42,17 @@ void mmu_wb_exit (wb_s * wb);
42 42
43 43
44/* wb_write_bytes :put bytess in Write Buffer 44/* wb_write_bytes :put bytess in Write Buffer
45 * @state: ARMul_State 45 * @state: ARMul_State
46 * @wb_t: write buffer 46 * @wb_t: write buffer
47 * @pa: physical address 47 * @pa: physical address
48 * @data: data ptr 48 * @data: data ptr
49 * @n number of byte to write 49 * @n number of byte to write
50 * 50 *
51 * Note: write buffer merge is not implemented, can be done late 51 * Note: write buffer merge is not implemented, can be done late
52 * */ 52 * */
53void 53void
54mmu_wb_write_bytess (ARMul_State * state, wb_s * wb_t, ARMword pa, 54mmu_wb_write_bytess (ARMul_State * state, wb_s * wb_t, ARMword pa,
55 ARMbyte * data, int n); 55 ARMbyte * data, int n);
56 56
57 57
58/* wb_drain_all 58/* wb_drain_all
HIC SVNT DRACONES