diff options
| author | 2014-03-29 23:28:38 -0400 | |
|---|---|---|
| committer | 2014-03-29 23:28:38 -0400 | |
| commit | 328c415c745adf91b920572658ae1157bcfef220 (patch) | |
| tree | 71e5c962f938fbcbf09e522e175e5e2fe3ef9823 /src/core | |
| parent | initialize mem regions (diff) | |
| download | yuzu-328c415c745adf91b920572658ae1157bcfef220.tar.gz yuzu-328c415c745adf91b920572658ae1157bcfef220.tar.xz yuzu-328c415c745adf91b920572658ae1157bcfef220.zip | |
added ARM11 MMU from skyeye
Diffstat (limited to 'src/core')
| -rw-r--r-- | src/core/core.vcxproj | 1 | ||||
| -rw-r--r-- | src/core/core.vcxproj.filters | 3 | ||||
| -rw-r--r-- | src/core/src/arm/armmmu.cpp | 2 | ||||
| -rw-r--r-- | src/core/src/arm/armmmu.h | 18 | ||||
| -rw-r--r-- | src/core/src/arm/mmu/arm1176jzf_s_mmu.cpp (renamed from src/core/src/arm/mmu/arm1176jzf_s_mmu.c) | 233 | ||||
| -rw-r--r-- | src/core/src/mem_map.h | 4 |
6 files changed, 116 insertions, 145 deletions
diff --git a/src/core/core.vcxproj b/src/core/core.vcxproj index a774f9e4b..d6382b634 100644 --- a/src/core/core.vcxproj +++ b/src/core/core.vcxproj | |||
| @@ -144,6 +144,7 @@ | |||
| 144 | <ClCompile Include="src\arm\armsupp.cpp" /> | 144 | <ClCompile Include="src\arm\armsupp.cpp" /> |
| 145 | <ClCompile Include="src\arm\armvirt.cpp" /> | 145 | <ClCompile Include="src\arm\armvirt.cpp" /> |
| 146 | <ClCompile Include="src\arm\disassembler\arm_disasm.cpp" /> | 146 | <ClCompile Include="src\arm\disassembler\arm_disasm.cpp" /> |
| 147 | <ClCompile Include="src\arm\mmu\arm1176jzf_s_mmu.cpp" /> | ||
| 147 | <ClCompile Include="src\core.cpp" /> | 148 | <ClCompile Include="src\core.cpp" /> |
| 148 | <ClCompile Include="src\core_timing.cpp" /> | 149 | <ClCompile Include="src\core_timing.cpp" /> |
| 149 | <ClCompile Include="src\elf\elf_reader.cpp" /> | 150 | <ClCompile Include="src\elf\elf_reader.cpp" /> |
diff --git a/src/core/core.vcxproj.filters b/src/core/core.vcxproj.filters index 50d0cbc71..9fb4d2892 100644 --- a/src/core/core.vcxproj.filters +++ b/src/core/core.vcxproj.filters | |||
| @@ -37,6 +37,9 @@ | |||
| 37 | <ClCompile Include="src\arm\armos.cpp"> | 37 | <ClCompile Include="src\arm\armos.cpp"> |
| 38 | <Filter>arm</Filter> | 38 | <Filter>arm</Filter> |
| 39 | </ClCompile> | 39 | </ClCompile> |
| 40 | <ClCompile Include="src\arm\mmu\arm1176jzf_s_mmu.cpp"> | ||
| 41 | <Filter>arm\mmu</Filter> | ||
| 42 | </ClCompile> | ||
| 40 | </ItemGroup> | 43 | </ItemGroup> |
| 41 | <ItemGroup> | 44 | <ItemGroup> |
| 42 | <Filter Include="arm"> | 45 | <Filter Include="arm"> |
diff --git a/src/core/src/arm/armmmu.cpp b/src/core/src/arm/armmmu.cpp index 476f8051d..93a094fc1 100644 --- a/src/core/src/arm/armmmu.cpp +++ b/src/core/src/arm/armmmu.cpp | |||
| @@ -72,7 +72,7 @@ mmu_init (ARMul_State * state) | |||
| 72 | /* case 0x560f5810: */ | 72 | /* case 0x560f5810: */ |
| 73 | case 0x0007b000: | 73 | case 0x0007b000: |
| 74 | NOTICE_LOG(ARM11, "SKYEYE: use arm11jzf-s mmu ops\n"); | 74 | NOTICE_LOG(ARM11, "SKYEYE: use arm11jzf-s mmu ops\n"); |
| 75 | //state->mmu.ops = arm1176jzf_s_mmu_ops; | 75 | state->mmu.ops = arm1176jzf_s_mmu_ops; |
| 76 | _dbg_assert_msg_(ARM11, false, "ImplementMe: arm1176jzf_s_mmu_ops!"); | 76 | _dbg_assert_msg_(ARM11, false, "ImplementMe: arm1176jzf_s_mmu_ops!"); |
| 77 | break; | 77 | break; |
| 78 | 78 | ||
diff --git a/src/core/src/arm/armmmu.h b/src/core/src/arm/armmmu.h index bf2904f63..a8d908c20 100644 --- a/src/core/src/arm/armmmu.h +++ b/src/core/src/arm/armmmu.h | |||
| @@ -104,15 +104,15 @@ typedef enum mmu_regnum_t | |||
| 104 | 104 | ||
| 105 | /*virt_addr exchange according to CP15.R13(process id virtul mapping)*/ | 105 | /*virt_addr exchange according to CP15.R13(process id virtul mapping)*/ |
| 106 | #define PID_VA_MAP_MASK 0xfe000000 | 106 | #define PID_VA_MAP_MASK 0xfe000000 |
| 107 | #define mmu_pid_va_map(va) ({\ | 107 | //#define mmu_pid_va_map(va) ({\ |
| 108 | ARMword ret; \ | 108 | // ARMword ret; \ |
| 109 | if ((va) & PID_VA_MAP_MASK)\ | 109 | // if ((va) & PID_VA_MAP_MASK)\ |
| 110 | ret = (va); \ | 110 | // ret = (va); \ |
| 111 | else \ | 111 | // else \ |
| 112 | ret = ((va) | (state->mmu.process_id & PID_VA_MAP_MASK));\ | 112 | // ret = ((va) | (state->mmu.process_id & PID_VA_MAP_MASK));\ |
| 113 | ret;\ | 113 | // ret;\ |
| 114 | }) | 114 | //}) |
| 115 | 115 | #define mmu_pid_va_map(va) ((va) & PID_VA_MAP_MASK) ? (va) : ((va) | (state->mmu.process_id & PID_VA_MAP_MASK)) | |
| 116 | 116 | ||
| 117 | /* FS[3:0] in the fault status register: */ | 117 | /* FS[3:0] in the fault status register: */ |
| 118 | 118 | ||
diff --git a/src/core/src/arm/mmu/arm1176jzf_s_mmu.c b/src/core/src/arm/mmu/arm1176jzf_s_mmu.cpp index 5d8c4590a..d45925c53 100644 --- a/src/core/src/arm/mmu/arm1176jzf_s_mmu.c +++ b/src/core/src/arm/mmu/arm1176jzf_s_mmu.cpp | |||
| @@ -21,10 +21,13 @@ | |||
| 21 | #include <assert.h> | 21 | #include <assert.h> |
| 22 | #include <string.h> | 22 | #include <string.h> |
| 23 | #include <stdint.h> | 23 | #include <stdint.h> |
| 24 | #include <skyeye_ram.h> | ||
| 25 | 24 | ||
| 26 | #include "armdefs.h" | 25 | #include "mem_map.h" |
| 27 | #include "bank_defs.h" | 26 | |
| 27 | #include "arm/skyeye_defs.h" | ||
| 28 | |||
| 29 | #include "arm/armdefs.h" | ||
| 30 | //#include "bank_defs.h" | ||
| 28 | #if 0 | 31 | #if 0 |
| 29 | #define TLB_SIZE 1024 * 1024 | 32 | #define TLB_SIZE 1024 * 1024 |
| 30 | #define ASID 255 | 33 | #define ASID 255 |
| @@ -59,44 +62,10 @@ static inline void insert_tlb(ARMul_State* state, ARMword va, ARMword pa){ | |||
| 59 | #endif | 62 | #endif |
| 60 | #define BANK0_START 0x50000000 | 63 | #define BANK0_START 0x50000000 |
| 61 | static void* mem_ptr = NULL; | 64 | static void* mem_ptr = NULL; |
| 62 | //static void mem_read_raw(uint32_t offset, uint32_t &value, int size) | ||
| 63 | static void mem_read_raw(int size, uint32_t offset, uint32_t *value) | ||
| 64 | { | ||
| 65 | #if 0 | ||
| 66 | if(mem_ptr == NULL) | ||
| 67 | mem_ptr = (uint8_t*)get_dma_addr(BANK0_START); | ||
| 68 | //printf("In %s, offset=0x%x, mem_ptr=0x%llx\n", __FUNCTION__, offset, mem_ptr); | ||
| 69 | if(offset >= 0x50000000 && offset < 0x70000000){ | ||
| 70 | mem_read(size, offset, value); | ||
| 71 | } | ||
| 72 | else{ | ||
| 73 | bus_read(size, offset, value); | ||
| 74 | } | ||
| 75 | #endif | ||
| 76 | bus_read(size, offset, value); | ||
| 77 | } | ||
| 78 | |||
| 79 | //static void mem_write_raw(uint32_t offset, uint32_t value, int size) | ||
| 80 | static void mem_write_raw(int size, uint32_t offset, uint32_t value) | ||
| 81 | { | ||
| 82 | #if 0 | ||
| 83 | if(mem_ptr == NULL) | ||
| 84 | mem_ptr = (uint8_t*)get_dma_addr(BANK0_START); | ||
| 85 | //printf("In %s, offset=0x%x, mem_ptr=0x%llx\n", __FUNCTION__, offset, mem_ptr); | ||
| 86 | if(offset >= 0x50000000 && offset < 0x70000000){ | ||
| 87 | mem_write(size, offset, value); | ||
| 88 | } | ||
| 89 | else{ | ||
| 90 | bus_write(size, offset, value); | ||
| 91 | } | ||
| 92 | #endif | ||
| 93 | bus_write(size, offset, value); | ||
| 94 | } | ||
| 95 | 65 | ||
| 96 | static int exclusive_detect(ARMul_State* state, ARMword addr){ | 66 | static int exclusive_detect(ARMul_State* state, ARMword addr){ |
| 97 | int i; | ||
| 98 | #if 0 | 67 | #if 0 |
| 99 | for(i = 0; i < 128; i++){ | 68 | for(int i = 0; i < 128; i++){ |
| 100 | if(state->exclusive_tag_array[i] == addr) | 69 | if(state->exclusive_tag_array[i] == addr) |
| 101 | return 0; | 70 | return 0; |
| 102 | } | 71 | } |
| @@ -108,9 +77,8 @@ static int exclusive_detect(ARMul_State* state, ARMword addr){ | |||
| 108 | } | 77 | } |
| 109 | 78 | ||
| 110 | static void add_exclusive_addr(ARMul_State* state, ARMword addr){ | 79 | static void add_exclusive_addr(ARMul_State* state, ARMword addr){ |
| 111 | int i; | ||
| 112 | #if 0 | 80 | #if 0 |
| 113 | for(i = 0; i < 128; i++){ | 81 | for(int i = 0; i < 128; i++){ |
| 114 | if(state->exclusive_tag_array[i] == 0xffffffff){ | 82 | if(state->exclusive_tag_array[i] == 0xffffffff){ |
| 115 | state->exclusive_tag_array[i] = addr; | 83 | state->exclusive_tag_array[i] = addr; |
| 116 | //printf("In %s, add addr 0x%x\n", __func__, addr); | 84 | //printf("In %s, add addr 0x%x\n", __func__, addr); |
| @@ -262,10 +230,11 @@ mmu_translate (ARMul_State *state, ARMword virt_addr, ARMword *phys_addr, int *a | |||
| 262 | } | 230 | } |
| 263 | 231 | ||
| 264 | /* l1desc = mem_read_word (state, l1addr); */ | 232 | /* l1desc = mem_read_word (state, l1addr); */ |
| 265 | if(state->space.conf_obj != NULL) | 233 | if (state->space.conf_obj != NULL) |
| 266 | state->space.read(state->space.conf_obj, l1addr, &l1desc, 4); | 234 | state->space.read(state->space.conf_obj, l1addr, &l1desc, 4); |
| 267 | else | 235 | else |
| 268 | mem_read_raw(32, l1addr, &l1desc); | 236 | l1desc = Memory::Read32(l1addr); //mem_read_raw(32, l1addr, &l1desc); |
| 237 | |||
| 269 | #if 0 | 238 | #if 0 |
| 270 | if (virt_addr == 0xc000d2bc) { | 239 | if (virt_addr == 0xc000d2bc) { |
| 271 | printf("mmu_control is %x\n", state->mmu.translation_table_ctrl); | 240 | printf("mmu_control is %x\n", state->mmu.translation_table_ctrl); |
| @@ -298,7 +267,8 @@ mmu_translate (ARMul_State *state, ARMword virt_addr, ARMword *phys_addr, int *a | |||
| 298 | if(state->space.conf_obj != NULL) | 267 | if(state->space.conf_obj != NULL) |
| 299 | state->space.read(state->space.conf_obj, l2addr, &l2desc, 4); | 268 | state->space.read(state->space.conf_obj, l2addr, &l2desc, 4); |
| 300 | else | 269 | else |
| 301 | mem_read_raw(32, l2addr, &l2desc); | 270 | l2desc = Memory::Read32(l2addr); //mem_read_raw(32, l2addr, &l2desc); |
| 271 | |||
| 302 | /* chy 2003-09-02 for xscale */ | 272 | /* chy 2003-09-02 for xscale */ |
| 303 | *ap = (l2desc >> 4) & 0x3; | 273 | *ap = (l2desc >> 4) & 0x3; |
| 304 | *sop = 1; /* page */ | 274 | *sop = 1; /* page */ |
| @@ -385,7 +355,7 @@ arm1176jzf_s_mmu_load_instr (ARMul_State *state, ARMword va, ARMword *instr) | |||
| 385 | 355 | ||
| 386 | static int debug_count = 0; /* used for debug */ | 356 | static int debug_count = 0; /* used for debug */ |
| 387 | 357 | ||
| 388 | d_msg ("va = %x\n", va); | 358 | DEBUG_LOG(ARM11, "va = %x\n", va); |
| 389 | 359 | ||
| 390 | va = mmu_pid_va_map (va); | 360 | va = mmu_pid_va_map (va); |
| 391 | if (MMU_Enabled) { | 361 | if (MMU_Enabled) { |
| @@ -393,7 +363,7 @@ arm1176jzf_s_mmu_load_instr (ARMul_State *state, ARMword va, ARMword *instr) | |||
| 393 | // sleep(1); | 363 | // sleep(1); |
| 394 | /* align check */ | 364 | /* align check */ |
| 395 | if ((va & (WORD_SIZE - 1)) && MMU_Aligned) { | 365 | if ((va & (WORD_SIZE - 1)) && MMU_Aligned) { |
| 396 | d_msg ("align\n"); | 366 | DEBUG_LOG(ARM11, "align\n"); |
| 397 | return ALIGNMENT_FAULT; | 367 | return ALIGNMENT_FAULT; |
| 398 | } else | 368 | } else |
| 399 | va &= ~(WORD_SIZE - 1); | 369 | va &= ~(WORD_SIZE - 1); |
| @@ -401,7 +371,7 @@ arm1176jzf_s_mmu_load_instr (ARMul_State *state, ARMword va, ARMword *instr) | |||
| 401 | /* translate tlb */ | 371 | /* translate tlb */ |
| 402 | fault = mmu_translate (state, va, &pa, &ap, &sop); | 372 | fault = mmu_translate (state, va, &pa, &ap, &sop); |
| 403 | if (fault) { | 373 | if (fault) { |
| 404 | d_msg ("translate\n"); | 374 | DEBUG_LOG(ARM11, "translate\n"); |
| 405 | printf("va=0x%x, icounter=%lld, fault=%d\n", va, state->NumInstrs, fault); | 375 | printf("va=0x%x, icounter=%lld, fault=%d\n", va, state->NumInstrs, fault); |
| 406 | return fault; | 376 | return fault; |
| 407 | } | 377 | } |
| @@ -420,7 +390,7 @@ arm1176jzf_s_mmu_load_instr (ARMul_State *state, ARMword va, ARMword *instr) | |||
| 420 | /*check access */ | 390 | /*check access */ |
| 421 | fault = check_access (state, va, tlb, 1); | 391 | fault = check_access (state, va, tlb, 1); |
| 422 | if (fault) { | 392 | if (fault) { |
| 423 | d_msg ("check_fault\n"); | 393 | DEBUG_LOG(ARM11, "check_fault\n"); |
| 424 | return fault; | 394 | return fault; |
| 425 | } | 395 | } |
| 426 | #endif | 396 | #endif |
| @@ -435,9 +405,9 @@ arm1176jzf_s_mmu_load_instr (ARMul_State *state, ARMword va, ARMword *instr) | |||
| 435 | if(state->space.conf_obj == NULL) | 405 | if(state->space.conf_obj == NULL) |
| 436 | state->space.read(state->space.conf_obj, pa, instr, 4); | 406 | state->space.read(state->space.conf_obj, pa, instr, 4); |
| 437 | else | 407 | else |
| 438 | mem_read_raw(32, pa, instr); | 408 | *instr = Memory::Read32(pa); //mem_read_raw(32, pa, instr); |
| 439 | 409 | ||
| 440 | return 0; | 410 | return NO_FAULT; |
| 441 | } | 411 | } |
| 442 | 412 | ||
| 443 | static fault_t | 413 | static fault_t |
| @@ -474,7 +444,7 @@ arm1176jzf_s_mmu_read (ARMul_State *state, ARMword va, ARMword *data, | |||
| 474 | ARMword perm; /* physical addr access permissions */ | 444 | ARMword perm; /* physical addr access permissions */ |
| 475 | int ap, sop; | 445 | int ap, sop; |
| 476 | 446 | ||
| 477 | d_msg ("va = %x\n", va); | 447 | DEBUG_LOG(ARM11, "va = %x\n", va); |
| 478 | 448 | ||
| 479 | va = mmu_pid_va_map (va); | 449 | va = mmu_pid_va_map (va); |
| 480 | real_va = va; | 450 | real_va = va; |
| @@ -489,25 +459,24 @@ arm1176jzf_s_mmu_read (ARMul_State *state, ARMword va, ARMword *data, | |||
| 489 | if(state->space.conf_obj != NULL) | 459 | if(state->space.conf_obj != NULL) |
| 490 | state->space.read(state->space.conf_obj, va, data, 1); | 460 | state->space.read(state->space.conf_obj, va, data, 1); |
| 491 | else | 461 | else |
| 492 | mem_read_raw(8, va, data); | 462 | *data = Memory::Read8(va); //mem_read_raw(8, va, data); |
| 493 | else if (datatype == ARM_HALFWORD_TYPE) | 463 | else if (datatype == ARM_HALFWORD_TYPE) |
| 494 | /* *data = mem_read_halfword (state, va); */ | 464 | /* *data = mem_read_halfword (state, va); */ |
| 495 | if(state->space.conf_obj != NULL) | 465 | if(state->space.conf_obj != NULL) |
| 496 | state->space.read(state->space.conf_obj, va, data, 2); | 466 | state->space.read(state->space.conf_obj, va, data, 2); |
| 497 | else | 467 | else |
| 498 | mem_read_raw(16, va, data); | 468 | *data = Memory::Read16(va); //mem_read_raw(16, va, data); |
| 499 | else if (datatype == ARM_WORD_TYPE) | 469 | else if (datatype == ARM_WORD_TYPE) |
| 500 | /* *data = mem_read_word (state, va); */ | 470 | /* *data = mem_read_word (state, va); */ |
| 501 | if(state->space.conf_obj != NULL) | 471 | if(state->space.conf_obj != NULL) |
| 502 | state->space.read(state->space.conf_obj, va, data, 4); | 472 | state->space.read(state->space.conf_obj, va, data, 4); |
| 503 | else | 473 | else |
| 504 | mem_read_raw(32, va, data); | 474 | *data = Memory::Read32(va); //mem_read_raw(32, va, data); |
| 505 | else { | 475 | else { |
| 506 | printf ("SKYEYE:1 arm1176jzf_s_mmu_read error: unknown data type %d\n", datatype); | 476 | ERROR_LOG(ARM11, "SKYEYE:1 arm1176jzf_s_mmu_read error: unknown data type %d\n", datatype); |
| 507 | skyeye_exit (-1); | ||
| 508 | } | 477 | } |
| 509 | 478 | ||
| 510 | return 0; | 479 | return NO_FAULT; |
| 511 | } | 480 | } |
| 512 | // printf("MMU enabled.\n"); | 481 | // printf("MMU enabled.\n"); |
| 513 | // sleep(1); | 482 | // sleep(1); |
| @@ -515,7 +484,7 @@ arm1176jzf_s_mmu_read (ARMul_State *state, ARMword va, ARMword *data, | |||
| 515 | /* align check */ | 484 | /* align check */ |
| 516 | if (((va & 3) && (datatype == ARM_WORD_TYPE) && MMU_Aligned) || | 485 | if (((va & 3) && (datatype == ARM_WORD_TYPE) && MMU_Aligned) || |
| 517 | ((va & 1) && (datatype == ARM_HALFWORD_TYPE) && MMU_Aligned)) { | 486 | ((va & 1) && (datatype == ARM_HALFWORD_TYPE) && MMU_Aligned)) { |
| 518 | d_msg ("align\n"); | 487 | DEBUG_LOG(ARM11, "align\n"); |
| 519 | return ALIGNMENT_FAULT; | 488 | return ALIGNMENT_FAULT; |
| 520 | } | 489 | } |
| 521 | 490 | ||
| @@ -544,7 +513,7 @@ arm1176jzf_s_mmu_read (ARMul_State *state, ARMword va, ARMword *data, | |||
| 544 | } | 513 | } |
| 545 | #endif | 514 | #endif |
| 546 | if (fault) { | 515 | if (fault) { |
| 547 | d_msg ("translate\n"); | 516 | DEBUG_LOG(ARM11, "translate\n"); |
| 548 | //printf("mmu read fault at %x\n", va); | 517 | //printf("mmu read fault at %x\n", va); |
| 549 | //printf("fault is %d\n", fault); | 518 | //printf("fault is %d\n", fault); |
| 550 | return fault; | 519 | return fault; |
| @@ -574,24 +543,23 @@ skip_translation: | |||
| 574 | if(state->space.conf_obj != NULL) | 543 | if(state->space.conf_obj != NULL) |
| 575 | state->space.read(state->space.conf_obj, pa | (real_va & 3), data, 1); | 544 | state->space.read(state->space.conf_obj, pa | (real_va & 3), data, 1); |
| 576 | else | 545 | else |
| 577 | mem_read_raw(8, pa | (real_va & 3), data); | 546 | *data = Memory::Read8(pa | (real_va & 3)); //mem_read_raw(8, pa | (real_va & 3), data); |
| 578 | /* mem_read_raw(32, pa | (real_va & 3), data); */ | 547 | /* mem_read_raw(32, pa | (real_va & 3), data); */ |
| 579 | } else if (datatype == ARM_HALFWORD_TYPE) { | 548 | } else if (datatype == ARM_HALFWORD_TYPE) { |
| 580 | /* *data = mem_read_halfword (state, pa | (real_va & 2)); */ | 549 | /* *data = mem_read_halfword (state, pa | (real_va & 2)); */ |
| 581 | if(state->space.conf_obj != NULL) | 550 | if(state->space.conf_obj != NULL) |
| 582 | state->space.read(state->space.conf_obj, pa | (real_va & 3), data, 2); | 551 | state->space.read(state->space.conf_obj, pa | (real_va & 3), data, 2); |
| 583 | else | 552 | else |
| 584 | mem_read_raw(16, pa | (real_va & 3), data); | 553 | *data = Memory::Read16(pa | (real_va & 3)); //mem_read_raw(16, pa | (real_va & 3), data); |
| 585 | /* mem_read_raw(32, pa | (real_va & 2), data); */ | 554 | /* mem_read_raw(32, pa | (real_va & 2), data); */ |
| 586 | } else if (datatype == ARM_WORD_TYPE) | 555 | } else if (datatype == ARM_WORD_TYPE) |
| 587 | /* *data = mem_read_word (state, pa); */ | 556 | /* *data = mem_read_word (state, pa); */ |
| 588 | if(state->space.conf_obj != NULL) | 557 | if(state->space.conf_obj != NULL) |
| 589 | state->space.read(state->space.conf_obj, pa , data, 4); | 558 | state->space.read(state->space.conf_obj, pa , data, 4); |
| 590 | else | 559 | else |
| 591 | mem_read_raw(32, pa, data); | 560 | *data = Memory::Read32(pa); //mem_read_raw(32, pa, data); |
| 592 | else { | 561 | else { |
| 593 | printf ("SKYEYE:2 arm1176jzf_s_mmu_read error: unknown data type %d\n", datatype); | 562 | ERROR_LOG(ARM11, "SKYEYE:2 arm1176jzf_s_mmu_read error: unknown data type %d\n", datatype); |
| 594 | skyeye_exit (-1); | ||
| 595 | } | 563 | } |
| 596 | if(0 && (va == 0x2869c)){ | 564 | if(0 && (va == 0x2869c)){ |
| 597 | printf("In %s, pa is %x va=0x%x, value is %x pc %x, instr=0x%x\n", __FUNCTION__, pa, va, *data, state->Reg[15], state->CurrInstr); | 565 | printf("In %s, pa is %x va=0x%x, value is %x pc %x, instr=0x%x\n", __FUNCTION__, pa, va, *data, state->Reg[15], state->CurrInstr); |
| @@ -614,7 +582,7 @@ skip_translation: | |||
| 614 | } | 582 | } |
| 615 | #endif | 583 | #endif |
| 616 | 584 | ||
| 617 | return 0; | 585 | return NO_FAULT; |
| 618 | } | 586 | } |
| 619 | 587 | ||
| 620 | 588 | ||
| @@ -661,7 +629,7 @@ arm1176jzf_s_mmu_write (ARMul_State *state, ARMword va, ARMword data, | |||
| 661 | } | 629 | } |
| 662 | #endif | 630 | #endif |
| 663 | 631 | ||
| 664 | d_msg ("va = %x, val = %x\n", va, data); | 632 | DEBUG_LOG(ARM11, "va = %x, val = %x\n", va, data); |
| 665 | va = mmu_pid_va_map (va); | 633 | va = mmu_pid_va_map (va); |
| 666 | real_va = va; | 634 | real_va = va; |
| 667 | 635 | ||
| @@ -672,22 +640,21 @@ arm1176jzf_s_mmu_write (ARMul_State *state, ARMword va, ARMword data, | |||
| 672 | if(state->space.conf_obj != NULL) | 640 | if(state->space.conf_obj != NULL) |
| 673 | state->space.write(state->space.conf_obj, va, &data, 1); | 641 | state->space.write(state->space.conf_obj, va, &data, 1); |
| 674 | else | 642 | else |
| 675 | mem_write_raw(8, va, data); | 643 | Memory::Write8(va, data); |
| 676 | else if (datatype == ARM_HALFWORD_TYPE) | 644 | else if (datatype == ARM_HALFWORD_TYPE) |
| 677 | /* mem_write_halfword (state, va, data); */ | 645 | /* mem_write_halfword (state, va, data); */ |
| 678 | if(state->space.conf_obj != NULL) | 646 | if(state->space.conf_obj != NULL) |
| 679 | state->space.write(state->space.conf_obj, va, &data, 2); | 647 | state->space.write(state->space.conf_obj, va, &data, 2); |
| 680 | else | 648 | else |
| 681 | mem_write_raw(16, va, data); | 649 | Memory::Write16(va, data); |
| 682 | else if (datatype == ARM_WORD_TYPE) | 650 | else if (datatype == ARM_WORD_TYPE) |
| 683 | /* mem_write_word (state, va, data); */ | 651 | /* mem_write_word (state, va, data); */ |
| 684 | if(state->space.conf_obj != NULL) | 652 | if(state->space.conf_obj != NULL) |
| 685 | state->space.write(state->space.conf_obj, va, &data, 4); | 653 | state->space.write(state->space.conf_obj, va, &data, 4); |
| 686 | else | 654 | else |
| 687 | mem_write_raw(32, va, data); | 655 | Memory::Write32(va, data); |
| 688 | else { | 656 | else { |
| 689 | printf ("SKYEYE:1 arm1176jzf_s_mmu_write error: unknown data type %d\n", datatype); | 657 | ERROR_LOG (ARM11, "SKYEYE:1 arm1176jzf_s_mmu_write error: unknown data type %d\n", datatype); |
| 690 | skyeye_exit (-1); | ||
| 691 | } | 658 | } |
| 692 | goto finished_write; | 659 | goto finished_write; |
| 693 | //return 0; | 660 | //return 0; |
| @@ -696,7 +663,7 @@ arm1176jzf_s_mmu_write (ARMul_State *state, ARMword va, ARMword data, | |||
| 696 | /* if ((va & (WORD_SIZE - 1)) && MMU_Aligned){ */ | 663 | /* if ((va & (WORD_SIZE - 1)) && MMU_Aligned){ */ |
| 697 | if (((va & 3) && (datatype == ARM_WORD_TYPE) && MMU_Aligned) || | 664 | if (((va & 3) && (datatype == ARM_WORD_TYPE) && MMU_Aligned) || |
| 698 | ((va & 1) && (datatype == ARM_HALFWORD_TYPE) && MMU_Aligned)) { | 665 | ((va & 1) && (datatype == ARM_HALFWORD_TYPE) && MMU_Aligned)) { |
| 699 | d_msg ("align\n"); | 666 | DEBUG_LOG(ARM11, "align\n"); |
| 700 | return ALIGNMENT_FAULT; | 667 | return ALIGNMENT_FAULT; |
| 701 | } | 668 | } |
| 702 | va &= ~(WORD_SIZE - 1); | 669 | va &= ~(WORD_SIZE - 1); |
| @@ -721,7 +688,7 @@ arm1176jzf_s_mmu_write (ARMul_State *state, ARMword va, ARMword data, | |||
| 721 | } | 688 | } |
| 722 | #endif | 689 | #endif |
| 723 | if (fault) { | 690 | if (fault) { |
| 724 | d_msg ("translate\n"); | 691 | DEBUG_LOG(ARM11, "translate\n"); |
| 725 | //printf("mmu write fault at %x\n", va); | 692 | //printf("mmu write fault at %x\n", va); |
| 726 | return fault; | 693 | return fault; |
| 727 | } | 694 | } |
| @@ -740,7 +707,7 @@ arm1176jzf_s_mmu_write (ARMul_State *state, ARMword va, ARMword data, | |||
| 740 | /* tlb check access */ | 707 | /* tlb check access */ |
| 741 | fault = check_access (state, va, tlb, 0); | 708 | fault = check_access (state, va, tlb, 0); |
| 742 | if (fault) { | 709 | if (fault) { |
| 743 | d_msg ("check_access\n"); | 710 | DEBUG_LOG(ARM11, "check_access\n"); |
| 744 | return fault; | 711 | return fault; |
| 745 | } | 712 | } |
| 746 | #endif | 713 | #endif |
| @@ -771,7 +738,7 @@ skip_translation: | |||
| 771 | else{ | 738 | else{ |
| 772 | state->Reg[dest_reg] = 1; | 739 | state->Reg[dest_reg] = 1; |
| 773 | //printf("In %s, try to strex a monitored address 0x%x\n", __FUNCTION__, pa); | 740 | //printf("In %s, try to strex a monitored address 0x%x\n", __FUNCTION__, pa); |
| 774 | return 0; | 741 | return NO_FAULT; |
| 775 | } | 742 | } |
| 776 | } | 743 | } |
| 777 | 744 | ||
| @@ -783,7 +750,7 @@ skip_translation: | |||
| 783 | if(state->space.conf_obj != NULL) | 750 | if(state->space.conf_obj != NULL) |
| 784 | state->space.write(state->space.conf_obj, (pa | (real_va & 3)), &data, 1); | 751 | state->space.write(state->space.conf_obj, (pa | (real_va & 3)), &data, 1); |
| 785 | else | 752 | else |
| 786 | mem_write_raw(8, (pa | (real_va & 3)), data); | 753 | Memory::Write8((pa | (real_va & 3)), data); |
| 787 | 754 | ||
| 788 | } else if (datatype == ARM_HALFWORD_TYPE) | 755 | } else if (datatype == ARM_HALFWORD_TYPE) |
| 789 | /* mem_write_halfword (state, | 756 | /* mem_write_halfword (state, |
| @@ -794,13 +761,13 @@ skip_translation: | |||
| 794 | if(state->space.conf_obj != NULL) | 761 | if(state->space.conf_obj != NULL) |
| 795 | state->space.write(state->space.conf_obj, (pa | (real_va & 3)), &data, 2); | 762 | state->space.write(state->space.conf_obj, (pa | (real_va & 3)), &data, 2); |
| 796 | else | 763 | else |
| 797 | mem_write_raw(16, (pa | (real_va & 3)), data); | 764 | Memory::Write16((pa | (real_va & 3)), data); |
| 798 | else if (datatype == ARM_WORD_TYPE) | 765 | else if (datatype == ARM_WORD_TYPE) |
| 799 | /* mem_write_word (state, pa, data); */ | 766 | /* mem_write_word (state, pa, data); */ |
| 800 | if(state->space.conf_obj != NULL) | 767 | if(state->space.conf_obj != NULL) |
| 801 | state->space.write(state->space.conf_obj, pa, &data, 4); | 768 | state->space.write(state->space.conf_obj, pa, &data, 4); |
| 802 | else | 769 | else |
| 803 | mem_write_raw(32, pa, data); | 770 | Memory::Write32(pa, data); |
| 804 | #if 0 | 771 | #if 0 |
| 805 | if (state->NumInstrs > 236403) { | 772 | if (state->NumInstrs > 236403) { |
| 806 | printf("write memory\n"); | 773 | printf("write memory\n"); |
| @@ -829,13 +796,13 @@ finished_write: | |||
| 829 | } | 796 | } |
| 830 | #endif | 797 | #endif |
| 831 | 798 | ||
| 832 | return 0; | 799 | return NO_FAULT; |
| 833 | } | 800 | } |
| 834 | 801 | ||
| 835 | ARMword | 802 | ARMword |
| 836 | arm1176jzf_s_mmu_mrc (ARMul_State *state, ARMword instr, ARMword *value) | 803 | arm1176jzf_s_mmu_mrc (ARMul_State *state, ARMword instr, ARMword *value) |
| 837 | { | 804 | { |
| 838 | mmu_regnum_t creg = BITS (16, 19) & 0xf; | 805 | int creg = BITS (16, 19) & 0xf; |
| 839 | int OPC_1 = BITS (21, 23) & 0x7; | 806 | int OPC_1 = BITS (21, 23) & 0x7; |
| 840 | int OPC_2 = BITS (5, 7) & 0x7; | 807 | int OPC_2 = BITS (5, 7) & 0x7; |
| 841 | ARMword data; | 808 | ARMword data; |
| @@ -921,8 +888,8 @@ arm1176jzf_s_mmu_mrc (ARMul_State *state, ARMword instr, ARMword *value) | |||
| 921 | static ARMword | 888 | static ARMword |
| 922 | arm1176jzf_s_mmu_mcr (ARMul_State *state, ARMword instr, ARMword value) | 889 | arm1176jzf_s_mmu_mcr (ARMul_State *state, ARMword instr, ARMword value) |
| 923 | { | 890 | { |
| 924 | mmu_regnum_t creg = BITS (16, 19) & 0xf; | 891 | int creg = BITS (16, 19) & 0xf; |
| 925 | mmu_regnum_t CRm = BITS (0, 3) & 0xf; | 892 | int CRm = BITS (0, 3) & 0xf; |
| 926 | int OPC_1 = BITS (21, 23) & 0x7; | 893 | int OPC_1 = BITS (21, 23) & 0x7; |
| 927 | int OPC_2 = BITS (5, 7) & 0x7; | 894 | int OPC_2 = BITS (5, 7) & 0x7; |
| 928 | if (!strncmp (state->cpu->cpu_arch_name, "armv6", 5)) { | 895 | if (!strncmp (state->cpu->cpu_arch_name, "armv6", 5)) { |
| @@ -1093,56 +1060,56 @@ arm1176jzf_s_mmu_mcr (ARMul_State *state, ARMword instr, ARMword value) | |||
| 1093 | return No_exp; | 1060 | return No_exp; |
| 1094 | } | 1061 | } |
| 1095 | 1062 | ||
| 1096 | /* teawater add for arm2x86 2005.06.19------------------------------------------- */ | 1063 | ///* teawater add for arm2x86 2005.06.19------------------------------------------- */ |
| 1097 | static int | 1064 | //static int |
| 1098 | arm1176jzf_s_mmu_v2p_dbct (ARMul_State *state, ARMword virt_addr, | 1065 | //arm1176jzf_s_mmu_v2p_dbct (ARMul_State *state, ARMword virt_addr, |
| 1099 | ARMword *phys_addr) | 1066 | // ARMword *phys_addr) |
| 1100 | { | 1067 | //{ |
| 1101 | fault_t fault; | 1068 | // fault_t fault; |
| 1102 | int ap, sop; | 1069 | // int ap, sop; |
| 1103 | 1070 | // | |
| 1104 | ARMword perm; /* physical addr access permissions */ | 1071 | // ARMword perm; /* physical addr access permissions */ |
| 1105 | virt_addr = mmu_pid_va_map (virt_addr); | 1072 | // virt_addr = mmu_pid_va_map (virt_addr); |
| 1106 | if (MMU_Enabled) { | 1073 | // if (MMU_Enabled) { |
| 1107 | 1074 | // | |
| 1108 | /*align check */ | 1075 | // /*align check */ |
| 1109 | if ((virt_addr & (WORD_SIZE - 1)) && MMU_Aligned) { | 1076 | // if ((virt_addr & (WORD_SIZE - 1)) && MMU_Aligned) { |
| 1110 | d_msg ("align\n"); | 1077 | // DEBUG_LOG(ARM11, "align\n"); |
| 1111 | return ALIGNMENT_FAULT; | 1078 | // return ALIGNMENT_FAULT; |
| 1112 | } else | 1079 | // } else |
| 1113 | virt_addr &= ~(WORD_SIZE - 1); | 1080 | // virt_addr &= ~(WORD_SIZE - 1); |
| 1114 | 1081 | // | |
| 1115 | /*translate tlb */ | 1082 | // /*translate tlb */ |
| 1116 | fault = mmu_translate (state, virt_addr, phys_addr, &ap, &sop); | 1083 | // fault = mmu_translate (state, virt_addr, phys_addr, &ap, &sop); |
| 1117 | if (fault) { | 1084 | // if (fault) { |
| 1118 | d_msg ("translate\n"); | 1085 | // DEBUG_LOG(ARM11, "translate\n"); |
| 1119 | return fault; | 1086 | // return fault; |
| 1120 | } | 1087 | // } |
| 1121 | 1088 | // | |
| 1122 | /* permission check */ | 1089 | // /* permission check */ |
| 1123 | if (!check_perms(state, ap, 1)) { | 1090 | // if (!check_perms(state, ap, 1)) { |
| 1124 | if (sop == 0) { | 1091 | // if (sop == 0) { |
| 1125 | return SECTION_PERMISSION_FAULT; | 1092 | // return SECTION_PERMISSION_FAULT; |
| 1126 | } else { | 1093 | // } else { |
| 1127 | return SUBPAGE_PERMISSION_FAULT; | 1094 | // return SUBPAGE_PERMISSION_FAULT; |
| 1128 | } | 1095 | // } |
| 1129 | } | 1096 | // } |
| 1130 | #if 0 | 1097 | //#if 0 |
| 1131 | /*check access */ | 1098 | // /*check access */ |
| 1132 | fault = check_access (state, virt_addr, tlb, 1); | 1099 | // fault = check_access (state, virt_addr, tlb, 1); |
| 1133 | if (fault) { | 1100 | // if (fault) { |
| 1134 | d_msg ("check_fault\n"); | 1101 | // DEBUG_LOG(ARM11, "check_fault\n"); |
| 1135 | return fault; | 1102 | // return fault; |
| 1136 | } | 1103 | // } |
| 1137 | #endif | 1104 | //#endif |
| 1138 | } | 1105 | // } |
| 1139 | 1106 | // | |
| 1140 | if (MMU_Disabled) { | 1107 | // if (MMU_Disabled) { |
| 1141 | *phys_addr = virt_addr; | 1108 | // *phys_addr = virt_addr; |
| 1142 | } | 1109 | // } |
| 1143 | 1110 | // | |
| 1144 | return 0; | 1111 | // return 0; |
| 1145 | } | 1112 | //} |
| 1146 | 1113 | ||
| 1147 | /* AJ2D-------------------------------------------------------------------------- */ | 1114 | /* AJ2D-------------------------------------------------------------------------- */ |
| 1148 | 1115 | ||
diff --git a/src/core/src/mem_map.h b/src/core/src/mem_map.h index 48137a19b..55f02e285 100644 --- a/src/core/src/mem_map.h +++ b/src/core/src/mem_map.h | |||
| @@ -71,8 +71,8 @@ u32 Read32(const u32 addr); | |||
| 71 | u32 Read8_ZX(const u32 addr); | 71 | u32 Read8_ZX(const u32 addr); |
| 72 | u32 Read16_ZX(const u32 addr); | 72 | u32 Read16_ZX(const u32 addr); |
| 73 | 73 | ||
| 74 | void Write8(const u32 addr, const u32 data); | 74 | void Write8(const u32 addr, const u8 data); |
| 75 | void Write16(const u32 addr, const u32 data); | 75 | void Write16(const u32 addr, const u16 data); |
| 76 | void Write32(const u32 addr, const u32 data); | 76 | void Write32(const u32 addr, const u32 data); |
| 77 | 77 | ||
| 78 | u8* GetPointer(const u32 Address); | 78 | u8* GetPointer(const u32 Address); |