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| author |  Tony Wasserka | 2015-04-10 01:31:01 +0200 |
|---|---|---|
| committer | Tony Wasserka | 2015-07-13 22:27:20 +0200 |
| commit | 256bdfb5797b7d4ee6c4fefa3dac99c0766a4df7 (patch) | |
| tree | d09655758e3d274ea9dff3f08d8b61387b3ea236 /src/core | |
| parent | Merge pull request #859 from Apology11/master (diff) | |
| download | yuzu-256bdfb5797b7d4ee6c4fefa3dac99c0766a4df7.tar.gz yuzu-256bdfb5797b7d4ee6c4fefa3dac99c0766a4df7.tar.xz yuzu-256bdfb5797b7d4ee6c4fefa3dac99c0766a4df7.zip | |
HW: Fix a stupid issue which led to unknown register reads/writes.
Diffstat (limited to 'src/core')
| -rw-r--r-- | src/core/hw/hw.cpp | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/core/hw/hw.cpp b/src/core/hw/hw.cpp index c7006a498..b5fdbf9c1 100644 --- a/src/core/hw/hw.cpp +++ b/src/core/hw/hw.cpp | |||
| @@ -15,6 +15,21 @@ template <typename T> | |||
| 15 | inline void Read(T &var, const u32 addr) { | 15 | inline void Read(T &var, const u32 addr) { |
| 16 | switch (addr & 0xFFFFF000) { | 16 | switch (addr & 0xFFFFF000) { |
| 17 | case VADDR_GPU: | 17 | case VADDR_GPU: |
| 18 | case VADDR_GPU + 0x1000: | ||
| 19 | case VADDR_GPU + 0x2000: | ||
| 20 | case VADDR_GPU + 0x3000: | ||
| 21 | case VADDR_GPU + 0x4000: | ||
| 22 | case VADDR_GPU + 0x5000: | ||
| 23 | case VADDR_GPU + 0x6000: | ||
| 24 | case VADDR_GPU + 0x7000: | ||
| 25 | case VADDR_GPU + 0x8000: | ||
| 26 | case VADDR_GPU + 0x9000: | ||
| 27 | case VADDR_GPU + 0xA000: | ||
| 28 | case VADDR_GPU + 0xB000: | ||
| 29 | case VADDR_GPU + 0xC000: | ||
| 30 | case VADDR_GPU + 0xD000: | ||
| 31 | case VADDR_GPU + 0xE000: | ||
| 32 | case VADDR_GPU + 0xF000: | ||
| 18 | GPU::Read(var, addr); | 33 | GPU::Read(var, addr); |
| 19 | break; | 34 | break; |
| 20 | case VADDR_LCD: | 35 | case VADDR_LCD: |
| @@ -29,6 +44,21 @@ template <typename T> | |||
| 29 | inline void Write(u32 addr, const T data) { | 44 | inline void Write(u32 addr, const T data) { |
| 30 | switch (addr & 0xFFFFF000) { | 45 | switch (addr & 0xFFFFF000) { |
| 31 | case VADDR_GPU: | 46 | case VADDR_GPU: |
| 47 | case VADDR_GPU + 0x1000: | ||
| 48 | case VADDR_GPU + 0x2000: | ||
| 49 | case VADDR_GPU + 0x3000: | ||
| 50 | case VADDR_GPU + 0x4000: | ||
| 51 | case VADDR_GPU + 0x5000: | ||
| 52 | case VADDR_GPU + 0x6000: | ||
| 53 | case VADDR_GPU + 0x7000: | ||
| 54 | case VADDR_GPU + 0x8000: | ||
| 55 | case VADDR_GPU + 0x9000: | ||
| 56 | case VADDR_GPU + 0xA000: | ||
| 57 | case VADDR_GPU + 0xB000: | ||
| 58 | case VADDR_GPU + 0xC000: | ||
| 59 | case VADDR_GPU + 0xD000: | ||
| 60 | case VADDR_GPU + 0xE000: | ||
| 61 | case VADDR_GPU + 0xF000: | ||
| 32 | GPU::Write(addr, data); | 62 | GPU::Write(addr, data); |
| 33 | break; | 63 | break; |
| 34 | case VADDR_LCD: | 64 | case VADDR_LCD: |