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| author | 2021-01-24 22:51:12 -0800 | |
|---|---|---|
| committer | 2021-01-28 21:42:26 -0800 | |
| commit | 055194d2ab69ca68687eb2ec49d1f98d78937a2c (patch) | |
| tree | 411e5a046350db3a8b78748a715543662b7db946 /src/core | |
| parent | common: common_funcs: Log error on R_UNLESS. (diff) | |
| download | yuzu-055194d2ab69ca68687eb2ec49d1f98d78937a2c.tar.gz yuzu-055194d2ab69ca68687eb2ec49d1f98d78937a2c.tar.xz yuzu-055194d2ab69ca68687eb2ec49d1f98d78937a2c.zip | |
core: arm: Remove unnecessary JIT checks.
Diffstat (limited to 'src/core')
| -rw-r--r-- | src/core/arm/dynarmic/arm_dynarmic_32.cpp | 12 | ||||
| -rw-r--r-- | src/core/arm/dynarmic/arm_dynarmic_64.cpp | 12 |
2 files changed, 0 insertions, 24 deletions
diff --git a/src/core/arm/dynarmic/arm_dynarmic_32.cpp b/src/core/arm/dynarmic/arm_dynarmic_32.cpp index 7d7e191ea..6c4c8e9e4 100644 --- a/src/core/arm/dynarmic/arm_dynarmic_32.cpp +++ b/src/core/arm/dynarmic/arm_dynarmic_32.cpp | |||
| @@ -251,16 +251,10 @@ void ARM_Dynarmic_32::SetTPIDR_EL0(u64 value) { | |||
| 251 | } | 251 | } |
| 252 | 252 | ||
| 253 | void ARM_Dynarmic_32::ChangeProcessorID(std::size_t new_core_id) { | 253 | void ARM_Dynarmic_32::ChangeProcessorID(std::size_t new_core_id) { |
| 254 | if (!jit) { | ||
| 255 | return; | ||
| 256 | } | ||
| 257 | jit->ChangeProcessorID(new_core_id); | 254 | jit->ChangeProcessorID(new_core_id); |
| 258 | } | 255 | } |
| 259 | 256 | ||
| 260 | void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) { | 257 | void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) { |
| 261 | if (!jit) { | ||
| 262 | return; | ||
| 263 | } | ||
| 264 | Dynarmic::A32::Context context; | 258 | Dynarmic::A32::Context context; |
| 265 | jit->SaveContext(context); | 259 | jit->SaveContext(context); |
| 266 | ctx.cpu_registers = context.Regs(); | 260 | ctx.cpu_registers = context.Regs(); |
| @@ -270,9 +264,6 @@ void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) { | |||
| 270 | } | 264 | } |
| 271 | 265 | ||
| 272 | void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) { | 266 | void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) { |
| 273 | if (!jit) { | ||
| 274 | return; | ||
| 275 | } | ||
| 276 | Dynarmic::A32::Context context; | 267 | Dynarmic::A32::Context context; |
| 277 | context.Regs() = ctx.cpu_registers; | 268 | context.Regs() = ctx.cpu_registers; |
| 278 | context.ExtRegs() = ctx.extension_registers; | 269 | context.ExtRegs() = ctx.extension_registers; |
| @@ -282,9 +273,6 @@ void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) { | |||
| 282 | } | 273 | } |
| 283 | 274 | ||
| 284 | void ARM_Dynarmic_32::PrepareReschedule() { | 275 | void ARM_Dynarmic_32::PrepareReschedule() { |
| 285 | if (!jit) { | ||
| 286 | return; | ||
| 287 | } | ||
| 288 | jit->HaltExecution(); | 276 | jit->HaltExecution(); |
| 289 | } | 277 | } |
| 290 | 278 | ||
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.cpp b/src/core/arm/dynarmic/arm_dynarmic_64.cpp index f755a39cf..4c5ebca22 100644 --- a/src/core/arm/dynarmic/arm_dynarmic_64.cpp +++ b/src/core/arm/dynarmic/arm_dynarmic_64.cpp | |||
| @@ -290,16 +290,10 @@ void ARM_Dynarmic_64::SetTPIDR_EL0(u64 value) { | |||
| 290 | } | 290 | } |
| 291 | 291 | ||
| 292 | void ARM_Dynarmic_64::ChangeProcessorID(std::size_t new_core_id) { | 292 | void ARM_Dynarmic_64::ChangeProcessorID(std::size_t new_core_id) { |
| 293 | if (!jit) { | ||
| 294 | return; | ||
| 295 | } | ||
| 296 | jit->ChangeProcessorID(new_core_id); | 293 | jit->ChangeProcessorID(new_core_id); |
| 297 | } | 294 | } |
| 298 | 295 | ||
| 299 | void ARM_Dynarmic_64::SaveContext(ThreadContext64& ctx) { | 296 | void ARM_Dynarmic_64::SaveContext(ThreadContext64& ctx) { |
| 300 | if (!jit) { | ||
| 301 | return; | ||
| 302 | } | ||
| 303 | ctx.cpu_registers = jit->GetRegisters(); | 297 | ctx.cpu_registers = jit->GetRegisters(); |
| 304 | ctx.sp = jit->GetSP(); | 298 | ctx.sp = jit->GetSP(); |
| 305 | ctx.pc = jit->GetPC(); | 299 | ctx.pc = jit->GetPC(); |
| @@ -311,9 +305,6 @@ void ARM_Dynarmic_64::SaveContext(ThreadContext64& ctx) { | |||
| 311 | } | 305 | } |
| 312 | 306 | ||
| 313 | void ARM_Dynarmic_64::LoadContext(const ThreadContext64& ctx) { | 307 | void ARM_Dynarmic_64::LoadContext(const ThreadContext64& ctx) { |
| 314 | if (!jit) { | ||
| 315 | return; | ||
| 316 | } | ||
| 317 | jit->SetRegisters(ctx.cpu_registers); | 308 | jit->SetRegisters(ctx.cpu_registers); |
| 318 | jit->SetSP(ctx.sp); | 309 | jit->SetSP(ctx.sp); |
| 319 | jit->SetPC(ctx.pc); | 310 | jit->SetPC(ctx.pc); |
| @@ -325,9 +316,6 @@ void ARM_Dynarmic_64::LoadContext(const ThreadContext64& ctx) { | |||
| 325 | } | 316 | } |
| 326 | 317 | ||
| 327 | void ARM_Dynarmic_64::PrepareReschedule() { | 318 | void ARM_Dynarmic_64::PrepareReschedule() { |
| 328 | if (!jit) { | ||
| 329 | return; | ||
| 330 | } | ||
| 331 | jit->HaltExecution(); | 319 | jit->HaltExecution(); |
| 332 | } | 320 | } |
| 333 | 321 | ||