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authorGravatar Yuri Kunde Schlesner2015-05-14 20:40:53 -0700
committerGravatar Yuri Kunde Schlesner2015-05-14 20:40:53 -0700
commitbb689338943791c735c7c6adb186256457e064b4 (patch)
treea04ba64d18dd163709b1cb4b4212afaca6c091a6 /src/core/memory.h
parentMerge pull request #769 from lioncash/cond (diff)
parentMemory: Use a table based lookup scheme to read from memory regions (diff)
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Merge pull request #762 from yuriks/memmap
Memory: Use a table based lookup scheme to read from memory regions
Diffstat (limited to 'src/core/memory.h')
-rw-r--r--src/core/memory.h129
1 files changed, 129 insertions, 0 deletions
diff --git a/src/core/memory.h b/src/core/memory.h
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1// Copyright 2014 Citra Emulator Project
2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included.
4
5#pragma once
6
7#include "common/common_types.h"
8
9namespace Memory {
10
11/**
12 * Page size used by the ARM architecture. This is the smallest granularity with which memory can
13 * be mapped.
14 */
15const u32 PAGE_SIZE = 0x1000;
16
17/// Physical memory regions as seen from the ARM11
18enum : PAddr {
19 /// IO register area
20 IO_AREA_PADDR = 0x10100000,
21 IO_AREA_SIZE = 0x01000000, ///< IO area size (16MB)
22 IO_AREA_PADDR_END = IO_AREA_PADDR + IO_AREA_SIZE,
23
24 /// MPCore internal memory region
25 MPCORE_RAM_PADDR = 0x17E00000,
26 MPCORE_RAM_SIZE = 0x00002000, ///< MPCore internal memory size (8KB)
27 MPCORE_RAM_PADDR_END = MPCORE_RAM_PADDR + MPCORE_RAM_SIZE,
28
29 /// Video memory
30 VRAM_PADDR = 0x18000000,
31 VRAM_SIZE = 0x00600000, ///< VRAM size (6MB)
32 VRAM_PADDR_END = VRAM_PADDR + VRAM_SIZE,
33
34 /// DSP memory
35 DSP_RAM_PADDR = 0x1FF00000,
36 DSP_RAM_SIZE = 0x00080000, ///< DSP memory size (512KB)
37 DSP_RAM_PADDR_END = DSP_RAM_PADDR + DSP_RAM_SIZE,
38
39 /// AXI WRAM
40 AXI_WRAM_PADDR = 0x1FF80000,
41 AXI_WRAM_SIZE = 0x00080000, ///< AXI WRAM size (512KB)
42 AXI_WRAM_PADDR_END = AXI_WRAM_PADDR + AXI_WRAM_SIZE,
43
44 /// Main FCRAM
45 FCRAM_PADDR = 0x20000000,
46 FCRAM_SIZE = 0x08000000, ///< FCRAM size (128MB)
47 FCRAM_PADDR_END = FCRAM_PADDR + FCRAM_SIZE,
48};
49
50/// Virtual user-space memory regions
51enum : VAddr {
52 /// Where the application text, data and bss reside.
53 PROCESS_IMAGE_VADDR = 0x00100000,
54 PROCESS_IMAGE_MAX_SIZE = 0x03F00000,
55 PROCESS_IMAGE_VADDR_END = PROCESS_IMAGE_VADDR + PROCESS_IMAGE_MAX_SIZE,
56
57 /// Area where IPC buffers are mapped onto.
58 IPC_MAPPING_VADDR = 0x04000000,
59 IPC_MAPPING_SIZE = 0x04000000,
60 IPC_MAPPING_VADDR_END = IPC_MAPPING_VADDR + IPC_MAPPING_SIZE,
61
62 /// Application heap (includes stack).
63 HEAP_VADDR = 0x08000000,
64 HEAP_SIZE = 0x08000000,
65 HEAP_VADDR_END = HEAP_VADDR + HEAP_SIZE,
66
67 /// Area where shared memory buffers are mapped onto.
68 SHARED_MEMORY_VADDR = 0x10000000,
69 SHARED_MEMORY_SIZE = 0x04000000,
70 SHARED_MEMORY_VADDR_END = SHARED_MEMORY_VADDR + SHARED_MEMORY_SIZE,
71
72 /// Maps 1:1 to an offset in FCRAM. Used for HW allocations that need to be linear in physical memory.
73 LINEAR_HEAP_VADDR = 0x14000000,
74 LINEAR_HEAP_SIZE = 0x08000000,
75 LINEAR_HEAP_VADDR_END = LINEAR_HEAP_VADDR + LINEAR_HEAP_SIZE,
76
77 /// Maps 1:1 to the IO register area.
78 IO_AREA_VADDR = 0x1EC00000,
79 IO_AREA_VADDR_END = IO_AREA_VADDR + IO_AREA_SIZE,
80
81 /// Maps 1:1 to VRAM.
82 VRAM_VADDR = 0x1F000000,
83 VRAM_VADDR_END = VRAM_VADDR + VRAM_SIZE,
84
85 /// Maps 1:1 to DSP memory.
86 DSP_RAM_VADDR = 0x1FF00000,
87 DSP_RAM_VADDR_END = DSP_RAM_VADDR + DSP_RAM_SIZE,
88
89 /// Read-only page containing kernel and system configuration values.
90 CONFIG_MEMORY_VADDR = 0x1FF80000,
91 CONFIG_MEMORY_SIZE = 0x00001000,
92 CONFIG_MEMORY_VADDR_END = CONFIG_MEMORY_VADDR + CONFIG_MEMORY_SIZE,
93
94 /// Usually read-only page containing mostly values read from hardware.
95 SHARED_PAGE_VADDR = 0x1FF81000,
96 SHARED_PAGE_SIZE = 0x00001000,
97 SHARED_PAGE_VADDR_END = SHARED_PAGE_VADDR + SHARED_PAGE_SIZE,
98
99 // TODO(yuriks): The size of this area is dynamic, the kernel grows
100 // it as more and more threads are created. For now we'll just use a
101 // hardcoded value.
102 /// Area where TLS (Thread-Local Storage) buffers are allocated.
103 TLS_AREA_VADDR = 0x1FF82000,
104 TLS_AREA_SIZE = 0x00030000, // Each TLS buffer is 0x200 bytes, allows for 300 threads
105 TLS_AREA_VADDR_END = TLS_AREA_VADDR + TLS_AREA_SIZE,
106};
107
108u8 Read8(VAddr addr);
109u16 Read16(VAddr addr);
110u32 Read32(VAddr addr);
111u64 Read64(VAddr addr);
112
113void Write8(VAddr addr, u8 data);
114void Write16(VAddr addr, u16 data);
115void Write32(VAddr addr, u32 data);
116void Write64(VAddr addr, u64 data);
117
118void WriteBlock(VAddr addr, const u8* data, size_t size);
119
120u8* GetPointer(VAddr virtual_address);
121
122/**
123 * Gets a pointer to the memory region beginning at the specified physical address.
124 *
125 * @note This is currently implemented using PhysicalToVirtualAddress().
126 */
127u8* GetPhysicalPointer(PAddr address);
128
129}