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| author | 2014-12-29 19:35:06 -0800 | |
|---|---|---|
| committer | 2014-12-29 19:35:06 -0800 | |
| commit | d5049cbba53d242b8461859fd02000b294164e77 (patch) | |
| tree | 9f5888bf28cf41ce61e80d690d0981986da20be0 /src/core/mem_map_funcs.cpp | |
| parent | Merge pull request #253 from purpasmart96/mem_map (diff) | |
| download | yuzu-d5049cbba53d242b8461859fd02000b294164e77.tar.gz yuzu-d5049cbba53d242b8461859fd02000b294164e77.tar.xz yuzu-d5049cbba53d242b8461859fd02000b294164e77.zip | |
MemMap: Add support for DSP Read & Writes in the memory map
Diffstat (limited to 'src/core/mem_map_funcs.cpp')
| -rw-r--r-- | src/core/mem_map_funcs.cpp | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/core/mem_map_funcs.cpp b/src/core/mem_map_funcs.cpp index fdf382ed6..97ef1c5a3 100644 --- a/src/core/mem_map_funcs.cpp +++ b/src/core/mem_map_funcs.cpp | |||
| @@ -82,6 +82,10 @@ inline void Read(T &var, const VAddr vaddr) { | |||
| 82 | } else if ((vaddr >= CONFIG_MEMORY_VADDR) && (vaddr < CONFIG_MEMORY_VADDR_END)) { | 82 | } else if ((vaddr >= CONFIG_MEMORY_VADDR) && (vaddr < CONFIG_MEMORY_VADDR_END)) { |
| 83 | ConfigMem::Read<T>(var, vaddr); | 83 | ConfigMem::Read<T>(var, vaddr); |
| 84 | 84 | ||
| 85 | // DSP memory | ||
| 86 | } else if ((vaddr >= DSP_MEMORY_VADDR) && (vaddr < DSP_MEMORY_VADDR_END)) { | ||
| 87 | var = *((const T*)&g_dsp_mem[vaddr - DSP_MEMORY_VADDR]); | ||
| 88 | |||
| 85 | // VRAM | 89 | // VRAM |
| 86 | } else if ((vaddr >= VRAM_VADDR) && (vaddr < VRAM_VADDR_END)) { | 90 | } else if ((vaddr >= VRAM_VADDR) && (vaddr < VRAM_VADDR_END)) { |
| 87 | var = *((const T*)&g_vram[vaddr - VRAM_VADDR]); | 91 | var = *((const T*)&g_vram[vaddr - VRAM_VADDR]); |
| @@ -122,8 +126,10 @@ inline void Write(const VAddr vaddr, const T data) { | |||
| 122 | } else if ((vaddr >= VRAM_VADDR) && (vaddr < VRAM_VADDR_END)) { | 126 | } else if ((vaddr >= VRAM_VADDR) && (vaddr < VRAM_VADDR_END)) { |
| 123 | *(T*)&g_vram[vaddr - VRAM_VADDR] = data; | 127 | *(T*)&g_vram[vaddr - VRAM_VADDR] = data; |
| 124 | 128 | ||
| 125 | //} else if ((vaddr & 0xFFF00000) == 0x1FF00000) { | 129 | // DSP memory |
| 126 | // _assert_msg_(MEMMAP, false, "umimplemented write to DSP memory"); | 130 | } else if ((vaddr >= DSP_MEMORY_VADDR) && (vaddr < DSP_MEMORY_VADDR_END)) { |
| 131 | *(T*)&g_dsp_mem[vaddr - DSP_MEMORY_VADDR] = data; | ||
| 132 | |||
| 127 | //} else if ((vaddr & 0xFFFF0000) == 0x1FF80000) { | 133 | //} else if ((vaddr & 0xFFFF0000) == 0x1FF80000) { |
| 128 | // _assert_msg_(MEMMAP, false, "umimplemented write to Configuration Memory"); | 134 | // _assert_msg_(MEMMAP, false, "umimplemented write to Configuration Memory"); |
| 129 | //} else if ((vaddr & 0xFFFFF000) == 0x1FF81000) { | 135 | //} else if ((vaddr & 0xFFFFF000) == 0x1FF81000) { |