summaryrefslogtreecommitdiff
path: root/src/core/mem_map_funcs.cpp
diff options
context:
space:
mode:
authorGravatar bunnei2014-12-29 23:08:51 -0500
committerGravatar bunnei2014-12-29 23:08:51 -0500
commitb3240f645580d30f9b8e1771430556f51102d7ff (patch)
tree7d33f0427cd1e4e92c5f733e742100c72e5d193c /src/core/mem_map_funcs.cpp
parentMerge pull request #364 from Subv/master (diff)
parentMemMap: Add support for DSP Read & Writes in the memory map (diff)
downloadyuzu-b3240f645580d30f9b8e1771430556f51102d7ff.tar.gz
yuzu-b3240f645580d30f9b8e1771430556f51102d7ff.tar.xz
yuzu-b3240f645580d30f9b8e1771430556f51102d7ff.zip
Merge pull request #368 from purpasmart96/dsp_mem
MemMap: Add support for DSP Read & Writes in the memory map
Diffstat (limited to 'src/core/mem_map_funcs.cpp')
-rw-r--r--src/core/mem_map_funcs.cpp10
1 files changed, 8 insertions, 2 deletions
diff --git a/src/core/mem_map_funcs.cpp b/src/core/mem_map_funcs.cpp
index fdf382ed6..97ef1c5a3 100644
--- a/src/core/mem_map_funcs.cpp
+++ b/src/core/mem_map_funcs.cpp
@@ -82,6 +82,10 @@ inline void Read(T &var, const VAddr vaddr) {
82 } else if ((vaddr >= CONFIG_MEMORY_VADDR) && (vaddr < CONFIG_MEMORY_VADDR_END)) { 82 } else if ((vaddr >= CONFIG_MEMORY_VADDR) && (vaddr < CONFIG_MEMORY_VADDR_END)) {
83 ConfigMem::Read<T>(var, vaddr); 83 ConfigMem::Read<T>(var, vaddr);
84 84
85 // DSP memory
86 } else if ((vaddr >= DSP_MEMORY_VADDR) && (vaddr < DSP_MEMORY_VADDR_END)) {
87 var = *((const T*)&g_dsp_mem[vaddr - DSP_MEMORY_VADDR]);
88
85 // VRAM 89 // VRAM
86 } else if ((vaddr >= VRAM_VADDR) && (vaddr < VRAM_VADDR_END)) { 90 } else if ((vaddr >= VRAM_VADDR) && (vaddr < VRAM_VADDR_END)) {
87 var = *((const T*)&g_vram[vaddr - VRAM_VADDR]); 91 var = *((const T*)&g_vram[vaddr - VRAM_VADDR]);
@@ -122,8 +126,10 @@ inline void Write(const VAddr vaddr, const T data) {
122 } else if ((vaddr >= VRAM_VADDR) && (vaddr < VRAM_VADDR_END)) { 126 } else if ((vaddr >= VRAM_VADDR) && (vaddr < VRAM_VADDR_END)) {
123 *(T*)&g_vram[vaddr - VRAM_VADDR] = data; 127 *(T*)&g_vram[vaddr - VRAM_VADDR] = data;
124 128
125 //} else if ((vaddr & 0xFFF00000) == 0x1FF00000) { 129 // DSP memory
126 // _assert_msg_(MEMMAP, false, "umimplemented write to DSP memory"); 130 } else if ((vaddr >= DSP_MEMORY_VADDR) && (vaddr < DSP_MEMORY_VADDR_END)) {
131 *(T*)&g_dsp_mem[vaddr - DSP_MEMORY_VADDR] = data;
132
127 //} else if ((vaddr & 0xFFFF0000) == 0x1FF80000) { 133 //} else if ((vaddr & 0xFFFF0000) == 0x1FF80000) {
128 // _assert_msg_(MEMMAP, false, "umimplemented write to Configuration Memory"); 134 // _assert_msg_(MEMMAP, false, "umimplemented write to Configuration Memory");
129 //} else if ((vaddr & 0xFFFFF000) == 0x1FF81000) { 135 //} else if ((vaddr & 0xFFFFF000) == 0x1FF81000) {