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authorGravatar bunnei2014-04-27 21:25:16 -0400
committerGravatar bunnei2014-04-27 21:25:16 -0400
commit438dba40c1def91e9de252ef05f8650464e5c0c2 (patch)
tree8f323d6095dfefe9d00f34cc4d7229be58a9f409 /src/core/hw
parentMerge pull request #4 from cpp3ds/master (diff)
parentremoved DISALLOW_COPY_AND_ASSIGN in favor of NonCopyable class (diff)
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Merge branch 'hle-interface-updates'
Diffstat (limited to 'src/core/hw')
-rw-r--r--src/core/hw/hw.cpp76
-rw-r--r--src/core/hw/lcd.cpp103
-rw-r--r--src/core/hw/lcd.h73
3 files changed, 206 insertions, 46 deletions
diff --git a/src/core/hw/hw.cpp b/src/core/hw/hw.cpp
index 16bd70125..85669ae7f 100644
--- a/src/core/hw/hw.cpp
+++ b/src/core/hw/hw.cpp
@@ -12,49 +12,42 @@
12namespace HW { 12namespace HW {
13 13
14enum { 14enum {
15 ADDRESS_CONFIG = 0x10000000, 15 VADDR_HASH = 0x1EC01000,
16 ADDRESS_IRQ = 0x10001000, 16 VADDR_CSND = 0x1EC03000,
17 ADDRESS_NDMA = 0x10002000, 17 VADDR_DSP = 0x1EC40000,
18 ADDRESS_TIMER = 0x10003000, 18 VADDR_PDN = 0x1EC41000,
19 ADDRESS_CTRCARD = 0x10004000, 19 VADDR_CODEC = 0x1EC41000,
20 ADDRESS_CTRCARD_2 = 0x10005000, 20 VADDR_SPI = 0x1EC42000,
21 ADDRESS_SDMC_NAND = 0x10006000, 21 VADDR_SPI_2 = 0x1EC43000, // Only used under TWL_FIRM?
22 ADDRESS_SDMC_NAND_2 = 0x10007000, // Apparently not used on retail 22 VADDR_I2C = 0x1EC44000,
23 ADDRESS_PXI = 0x10008000, 23 VADDR_CODEC_2 = 0x1EC45000,
24 ADDRESS_AES = 0x10009000, 24 VADDR_HID = 0x1EC46000,
25 ADDRESS_SHA = 0x1000A000, 25 VADDR_PAD = 0x1EC46000,
26 ADDRESS_RSA = 0x1000B000, 26 VADDR_PTM = 0x1EC46000,
27 ADDRESS_XDMA = 0x1000C000, 27 VADDR_GPIO = 0x1EC47000,
28 ADDRESS_SPICARD = 0x1000D800, 28 VADDR_I2C_2 = 0x1EC48000,
29 ADDRESS_CONFIG_2 = 0x10010000, 29 VADDR_SPI_3 = 0x1EC60000,
30 ADDRESS_HASH = 0x10101000, 30 VADDR_I2C_3 = 0x1EC61000,
31 ADDRESS_CSND = 0x10103000, 31 VADDR_MIC = 0x1EC62000,
32 ADDRESS_DSP = 0x10140000, 32 VADDR_PXI = 0x1EC63000, // 0xFFFD2000
33 ADDRESS_PDN = 0x10141000, 33 //VADDR_NTRCARD
34 ADDRESS_CODEC = 0x10141000, 34 VADDR_CDMA = 0xFFFDA000, // CoreLink DMA-330? Info
35 ADDRESS_SPI = 0x10142000, 35 VADDR_DSP_2 = 0x1ED03000,
36 ADDRESS_SPI_2 = 0x10143000, 36 VADDR_HASH_2 = 0x1EE01000,
37 ADDRESS_I2C = 0x10144000, 37 VADDR_LCD = 0x1EF00000,
38 ADDRESS_CODEC_2 = 0x10145000,
39 ADDRESS_HID = 0x10146000,
40 ADDRESS_PAD = 0x10146000,
41 ADDRESS_PTM = 0x10146000,
42 ADDRESS_I2C_2 = 0x10148000,
43 ADDRESS_SPI_3 = 0x10160000,
44 ADDRESS_I2C_3 = 0x10161000,
45 ADDRESS_MIC = 0x10162000,
46 ADDRESS_PXI_2 = 0x10163000,
47 ADDRESS_NTRCARD = 0x10164000,
48 ADDRESS_DSP_2 = 0x10203000,
49 ADDRESS_HASH_2 = 0x10301000,
50}; 38};
51 39
52template <typename T> 40template <typename T>
53inline void Read(T &var, const u32 addr) { 41inline void Read(T &var, const u32 addr) {
54 switch (addr & 0xFFFFF000) { 42 switch (addr & 0xFFFFF000) {
55 43
56 case ADDRESS_NDMA: 44 // TODO(bunnei): What is the virtual address of NDMA?
57 NDMA::Read(var, addr); 45 // case VADDR_NDMA:
46 // NDMA::Read(var, addr);
47 // break;
48
49 case VADDR_LCD:
50 LCD::Read(var, addr);
58 break; 51 break;
59 52
60 default: 53 default:
@@ -66,8 +59,13 @@ template <typename T>
66inline void Write(u32 addr, const T data) { 59inline void Write(u32 addr, const T data) {
67 switch (addr & 0xFFFFF000) { 60 switch (addr & 0xFFFFF000) {
68 61
69 case ADDRESS_NDMA: 62 // TODO(bunnei): What is the virtual address of NDMA?
70 NDMA::Write(addr, data); 63 // case VADDR_NDMA
64 // NDMA::Write(addr, data);
65 // break;
66
67 case VADDR_LCD:
68 LCD::Write(addr, data);
71 break; 69 break;
72 70
73 default: 71 default:
diff --git a/src/core/hw/lcd.cpp b/src/core/hw/lcd.cpp
index 3013673f8..6468053f2 100644
--- a/src/core/hw/lcd.cpp
+++ b/src/core/hw/lcd.cpp
@@ -6,24 +6,126 @@
6#include "common/log.h" 6#include "common/log.h"
7 7
8#include "core/core.h" 8#include "core/core.h"
9#include "core/mem_map.h"
9#include "core/hw/lcd.h" 10#include "core/hw/lcd.h"
10 11
11#include "video_core/video_core.h" 12#include "video_core/video_core.h"
12 13
13namespace LCD { 14namespace LCD {
14 15
16Registers g_regs;
17
15static const u32 kFrameTicks = 268123480 / 60; ///< 268MHz / 60 frames per second 18static const u32 kFrameTicks = 268123480 / 60; ///< 268MHz / 60 frames per second
16 19
17u64 g_last_ticks = 0; ///< Last CPU ticks 20u64 g_last_ticks = 0; ///< Last CPU ticks
18 21
22/**
23 * Sets whether the framebuffers are in the GSP heap (FCRAM) or VRAM
24 * @param
25 */
26void SetFramebufferLocation(const FramebufferLocation mode) {
27 switch (mode) {
28 case FRAMEBUFFER_LOCATION_FCRAM:
29 g_regs.framebuffer_top_left_1 = PADDR_TOP_LEFT_FRAME1;
30 g_regs.framebuffer_top_left_2 = PADDR_TOP_LEFT_FRAME2;
31 g_regs.framebuffer_top_right_1 = PADDR_TOP_RIGHT_FRAME1;
32 g_regs.framebuffer_top_right_2 = PADDR_TOP_RIGHT_FRAME2;
33 g_regs.framebuffer_sub_left_1 = PADDR_SUB_FRAME1;
34 //g_regs.framebuffer_sub_left_2 = unknown;
35 g_regs.framebuffer_sub_right_1 = PADDR_SUB_FRAME2;
36 //g_regs.framebufferr_sub_right_2 = unknown;
37 break;
38
39 case FRAMEBUFFER_LOCATION_VRAM:
40 g_regs.framebuffer_top_left_1 = PADDR_VRAM_TOP_LEFT_FRAME1;
41 g_regs.framebuffer_top_left_2 = PADDR_VRAM_TOP_LEFT_FRAME2;
42 g_regs.framebuffer_top_right_1 = PADDR_VRAM_TOP_RIGHT_FRAME1;
43 g_regs.framebuffer_top_right_2 = PADDR_VRAM_TOP_RIGHT_FRAME2;
44 g_regs.framebuffer_sub_left_1 = PADDR_VRAM_SUB_FRAME1;
45 //g_regs.framebuffer_sub_left_2 = unknown;
46 g_regs.framebuffer_sub_right_1 = PADDR_VRAM_SUB_FRAME2;
47 //g_regs.framebufferr_sub_right_2 = unknown;
48 break;
49 }
50}
51
52/**
53 * Gets the location of the framebuffers
54 * @return Location of framebuffers as FramebufferLocation enum
55 */
56const FramebufferLocation GetFramebufferLocation() {
57 if ((g_regs.framebuffer_top_right_1 & ~Memory::VRAM_MASK) == Memory::VRAM_PADDR) {
58 return FRAMEBUFFER_LOCATION_VRAM;
59 } else if ((g_regs.framebuffer_top_right_1 & ~Memory::FCRAM_MASK) == Memory::FCRAM_PADDR) {
60 return FRAMEBUFFER_LOCATION_FCRAM;
61 } else {
62 ERROR_LOG(LCD, "unknown framebuffer location!");
63 }
64 return FRAMEBUFFER_LOCATION_UNKNOWN;
65}
66
67/**
68 * Gets a read-only pointer to a framebuffer in memory
69 * @param address Physical address of framebuffer
70 * @return Returns const pointer to raw framebuffer
71 */
72const u8* GetFramebufferPointer(const u32 address) {
73 switch (GetFramebufferLocation()) {
74 case FRAMEBUFFER_LOCATION_FCRAM:
75 return (const u8*)Memory::GetPointer(Memory::VirtualAddressFromPhysical_FCRAM(address));
76 case FRAMEBUFFER_LOCATION_VRAM:
77 return (const u8*)Memory::GetPointer(Memory::VirtualAddressFromPhysical_VRAM(address));
78 default:
79 ERROR_LOG(LCD, "unknown framebuffer location");
80 }
81 return NULL;
82}
83
19template <typename T> 84template <typename T>
20inline void Read(T &var, const u32 addr) { 85inline void Read(T &var, const u32 addr) {
86 switch (addr) {
87 case REG_FRAMEBUFFER_TOP_LEFT_1:
88 var = g_regs.framebuffer_top_left_1;
89 break;
90 case REG_FRAMEBUFFER_TOP_LEFT_2:
91 var = g_regs.framebuffer_top_left_2;
92 break;
93 case REG_FRAMEBUFFER_TOP_RIGHT_1:
94 var = g_regs.framebuffer_top_right_1;
95 break;
96 case REG_FRAMEBUFFER_TOP_RIGHT_2:
97 var = g_regs.framebuffer_top_right_2;
98 break;
99 case REG_FRAMEBUFFER_SUB_LEFT_1:
100 var = g_regs.framebuffer_sub_left_1;
101 break;
102 case REG_FRAMEBUFFER_SUB_RIGHT_1:
103 var = g_regs.framebuffer_sub_right_1;
104 break;
105 default:
106 ERROR_LOG(LCD, "unknown Read%d @ 0x%08X", sizeof(var) * 8, addr);
107 break;
108 }
109
21} 110}
22 111
23template <typename T> 112template <typename T>
24inline void Write(u32 addr, const T data) { 113inline void Write(u32 addr, const T data) {
114 ERROR_LOG(LCD, "unknown Write%d 0x%08X @ 0x%08X", sizeof(data) * 8, data, addr);
25} 115}
26 116
117// Explicitly instantiate template functions because we aren't defining this in the header:
118
119template void Read<u64>(u64 &var, const u32 addr);
120template void Read<u32>(u32 &var, const u32 addr);
121template void Read<u16>(u16 &var, const u32 addr);
122template void Read<u8>(u8 &var, const u32 addr);
123
124template void Write<u64>(u32 addr, const u64 data);
125template void Write<u32>(u32 addr, const u32 data);
126template void Write<u16>(u32 addr, const u16 data);
127template void Write<u8>(u32 addr, const u8 data);
128
27/// Update hardware 129/// Update hardware
28void Update() { 130void Update() {
29 u64 current_ticks = Core::g_app_core->GetTicks(); 131 u64 current_ticks = Core::g_app_core->GetTicks();
@@ -37,6 +139,7 @@ void Update() {
37/// Initialize hardware 139/// Initialize hardware
38void Init() { 140void Init() {
39 g_last_ticks = Core::g_app_core->GetTicks(); 141 g_last_ticks = Core::g_app_core->GetTicks();
142 SetFramebufferLocation(FRAMEBUFFER_LOCATION_FCRAM);
40 NOTICE_LOG(LCD, "initialized OK"); 143 NOTICE_LOG(LCD, "initialized OK");
41} 144}
42 145
diff --git a/src/core/hw/lcd.h b/src/core/hw/lcd.h
index 386ed6004..2dd3b4adc 100644
--- a/src/core/hw/lcd.h
+++ b/src/core/hw/lcd.h
@@ -8,6 +8,19 @@
8 8
9namespace LCD { 9namespace LCD {
10 10
11struct Registers {
12 u32 framebuffer_top_left_1;
13 u32 framebuffer_top_left_2;
14 u32 framebuffer_top_right_1;
15 u32 framebuffer_top_right_2;
16 u32 framebuffer_sub_left_1;
17 u32 framebuffer_sub_left_2;
18 u32 framebuffer_sub_right_1;
19 u32 framebuffer_sub_right_2;
20};
21
22extern Registers g_regs;
23
11enum { 24enum {
12 TOP_ASPECT_X = 0x5, 25 TOP_ASPECT_X = 0x5,
13 TOP_ASPECT_Y = 0x3, 26 TOP_ASPECT_Y = 0x3,
@@ -16,15 +29,61 @@ enum {
16 TOP_WIDTH = 400, 29 TOP_WIDTH = 400,
17 BOTTOM_WIDTH = 320, 30 BOTTOM_WIDTH = 320,
18 31
19 FRAMEBUFFER_SEL = 0x20184E59, 32 // Physical addresses in FCRAM used by ARM9 applications - these are correct for real hardware
20 TOP_LEFT_FRAME1 = 0x20184E60, 33 PADDR_FRAMEBUFFER_SEL = 0x20184E59,
21 TOP_LEFT_FRAME2 = 0x201CB370, 34 PADDR_TOP_LEFT_FRAME1 = 0x20184E60,
22 TOP_RIGHT_FRAME1 = 0x20282160, 35 PADDR_TOP_LEFT_FRAME2 = 0x201CB370,
23 TOP_RIGHT_FRAME2 = 0x202C8670, 36 PADDR_TOP_RIGHT_FRAME1 = 0x20282160,
24 SUB_FRAME1 = 0x202118E0, 37 PADDR_TOP_RIGHT_FRAME2 = 0x202C8670,
25 SUB_FRAME2 = 0x20249CF0, 38 PADDR_SUB_FRAME1 = 0x202118E0,
39 PADDR_SUB_FRAME2 = 0x20249CF0,
40
41 // Physical addresses in VRAM - I'm not sure how these are actually allocated (so not real)
42 PADDR_VRAM_FRAMEBUFFER_SEL = 0x18184E59,
43 PADDR_VRAM_TOP_LEFT_FRAME1 = 0x18184E60,
44 PADDR_VRAM_TOP_LEFT_FRAME2 = 0x181CB370,
45 PADDR_VRAM_TOP_RIGHT_FRAME1 = 0x18282160,
46 PADDR_VRAM_TOP_RIGHT_FRAME2 = 0x182C8670,
47 PADDR_VRAM_SUB_FRAME1 = 0x182118E0,
48 PADDR_VRAM_SUB_FRAME2 = 0x18249CF0,
49};
50
51enum {
52 REG_FRAMEBUFFER_TOP_LEFT_1 = 0x1EF00468, // Main LCD, first framebuffer for 3D left
53 REG_FRAMEBUFFER_TOP_LEFT_2 = 0x1EF0046C, // Main LCD, second framebuffer for 3D left
54 REG_FRAMEBUFFER_TOP_RIGHT_1 = 0x1EF00494, // Main LCD, first framebuffer for 3D right
55 REG_FRAMEBUFFER_TOP_RIGHT_2 = 0x1EF00498, // Main LCD, second framebuffer for 3D right
56 REG_FRAMEBUFFER_SUB_LEFT_1 = 0x1EF00568, // Sub LCD, first framebuffer
57 REG_FRAMEBUFFER_SUB_LEFT_2 = 0x1EF0056C, // Sub LCD, second framebuffer
58 REG_FRAMEBUFFER_SUB_RIGHT_1 = 0x1EF00594, // Sub LCD, unused first framebuffer
59 REG_FRAMEBUFFER_SUB_RIGHT_2 = 0x1EF00598, // Sub LCD, unused second framebuffer
60};
61
62/// Framebuffer location
63enum FramebufferLocation {
64 FRAMEBUFFER_LOCATION_UNKNOWN, ///< Framebuffer location is unknown
65 FRAMEBUFFER_LOCATION_FCRAM, ///< Framebuffer is in the GSP heap
66 FRAMEBUFFER_LOCATION_VRAM, ///< Framebuffer is in VRAM
26}; 67};
27 68
69/**
70 * Sets whether the framebuffers are in the GSP heap (FCRAM) or VRAM
71 * @param
72 */
73void SetFramebufferLocation(const FramebufferLocation mode);
74
75/**
76 * Gets a read-only pointer to a framebuffer in memory
77 * @param address Physical address of framebuffer
78 * @return Returns const pointer to raw framebuffer
79 */
80const u8* GetFramebufferPointer(const u32 address);
81
82/**
83 * Gets the location of the framebuffers
84 */
85const FramebufferLocation GetFramebufferLocation();
86
28template <typename T> 87template <typename T>
29inline void Read(T &var, const u32 addr); 88inline void Read(T &var, const u32 addr);
30 89