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| author | 2015-03-10 18:08:55 -0400 | |
|---|---|---|
| committer | 2015-03-10 18:08:55 -0400 | |
| commit | b56829df020a81248dd04688ff2b307f3444a09f (patch) | |
| tree | 24a438627339b2d506e659adfa0873cdf037852a /src/core/hw/hw.cpp | |
| parent | Merge pull request #649 from lioncash/clean (diff) | |
| parent | Added LCD registers, and implementation for color filling in OGL code. (diff) | |
| download | yuzu-b56829df020a81248dd04688ff2b307f3444a09f.tar.gz yuzu-b56829df020a81248dd04688ff2b307f3444a09f.tar.xz yuzu-b56829df020a81248dd04688ff2b307f3444a09f.zip | |
Merge pull request #629 from archshift/lcdfb
Implement SetLcdForceBlack and add implementation for color filling in the GPU code
Diffstat (limited to 'src/core/hw/hw.cpp')
| -rw-r--r-- | src/core/hw/hw.cpp | 38 |
1 files changed, 8 insertions, 30 deletions
diff --git a/src/core/hw/hw.cpp b/src/core/hw/hw.cpp index a63ba6eeb..bed50af50 100644 --- a/src/core/hw/hw.cpp +++ b/src/core/hw/hw.cpp | |||
| @@ -6,43 +6,19 @@ | |||
| 6 | 6 | ||
| 7 | #include "core/hw/hw.h" | 7 | #include "core/hw/hw.h" |
| 8 | #include "core/hw/gpu.h" | 8 | #include "core/hw/gpu.h" |
| 9 | #include "core/hw/lcd.h" | ||
| 9 | 10 | ||
| 10 | namespace HW { | 11 | namespace HW { |
| 11 | 12 | ||
| 12 | enum { | ||
| 13 | VADDR_HASH = 0x1EC01000, | ||
| 14 | VADDR_CSND = 0x1EC03000, | ||
| 15 | VADDR_DSP = 0x1EC40000, | ||
| 16 | VADDR_PDN = 0x1EC41000, | ||
| 17 | VADDR_CODEC = 0x1EC41000, | ||
| 18 | VADDR_SPI = 0x1EC42000, | ||
| 19 | VADDR_SPI_2 = 0x1EC43000, // Only used under TWL_FIRM? | ||
| 20 | VADDR_I2C = 0x1EC44000, | ||
| 21 | VADDR_CODEC_2 = 0x1EC45000, | ||
| 22 | VADDR_HID = 0x1EC46000, | ||
| 23 | VADDR_PAD = 0x1EC46000, | ||
| 24 | VADDR_PTM = 0x1EC46000, | ||
| 25 | VADDR_GPIO = 0x1EC47000, | ||
| 26 | VADDR_I2C_2 = 0x1EC48000, | ||
| 27 | VADDR_SPI_3 = 0x1EC60000, | ||
| 28 | VADDR_I2C_3 = 0x1EC61000, | ||
| 29 | VADDR_MIC = 0x1EC62000, | ||
| 30 | VADDR_PXI = 0x1EC63000, // 0xFFFD2000 | ||
| 31 | //VADDR_NTRCARD | ||
| 32 | VADDR_CDMA = 0xFFFDA000, // CoreLink DMA-330? Info | ||
| 33 | VADDR_DSP_2 = 0x1ED03000, | ||
| 34 | VADDR_HASH_2 = 0x1EE01000, | ||
| 35 | VADDR_GPU = 0x1EF00000, | ||
| 36 | }; | ||
| 37 | |||
| 38 | template <typename T> | 13 | template <typename T> |
| 39 | inline void Read(T &var, const u32 addr) { | 14 | inline void Read(T &var, const u32 addr) { |
| 40 | switch (addr & 0xFFFFF000) { | 15 | switch (addr & 0xFFFFF000) { |
| 41 | |||
| 42 | case VADDR_GPU: | 16 | case VADDR_GPU: |
| 43 | GPU::Read(var, addr); | 17 | GPU::Read(var, addr); |
| 44 | break; | 18 | break; |
| 45 | 19 | case VADDR_LCD: | |
| 20 | LCD::Write(var, addr); | ||
| 21 | break; | ||
| 46 | default: | 22 | default: |
| 47 | LOG_ERROR(HW_Memory, "unknown Read%lu @ 0x%08X", sizeof(var) * 8, addr); | 23 | LOG_ERROR(HW_Memory, "unknown Read%lu @ 0x%08X", sizeof(var) * 8, addr); |
| 48 | } | 24 | } |
| @@ -51,11 +27,12 @@ inline void Read(T &var, const u32 addr) { | |||
| 51 | template <typename T> | 27 | template <typename T> |
| 52 | inline void Write(u32 addr, const T data) { | 28 | inline void Write(u32 addr, const T data) { |
| 53 | switch (addr & 0xFFFFF000) { | 29 | switch (addr & 0xFFFFF000) { |
| 54 | |||
| 55 | case VADDR_GPU: | 30 | case VADDR_GPU: |
| 56 | GPU::Write(addr, data); | 31 | GPU::Write(addr, data); |
| 57 | break; | 32 | break; |
| 58 | 33 | case VADDR_LCD: | |
| 34 | LCD::Write(addr, data); | ||
| 35 | break; | ||
| 59 | default: | 36 | default: |
| 60 | LOG_ERROR(HW_Memory, "unknown Write%lu 0x%08X @ 0x%08X", sizeof(data) * 8, (u32)data, addr); | 37 | LOG_ERROR(HW_Memory, "unknown Write%lu 0x%08X @ 0x%08X", sizeof(data) * 8, (u32)data, addr); |
| 61 | } | 38 | } |
| @@ -80,6 +57,7 @@ void Update() { | |||
| 80 | /// Initialize hardware | 57 | /// Initialize hardware |
| 81 | void Init() { | 58 | void Init() { |
| 82 | GPU::Init(); | 59 | GPU::Init(); |
| 60 | LCD::Init(); | ||
| 83 | LOG_DEBUG(HW, "initialized OK"); | 61 | LOG_DEBUG(HW, "initialized OK"); |
| 84 | } | 62 | } |
| 85 | 63 | ||