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| author | 2014-05-17 22:50:33 +0200 | |
|---|---|---|
| committer | 2014-06-12 06:10:49 -0400 | |
| commit | 1dfa3928242ad486040b1c65768faa2c7fce4654 (patch) | |
| tree | 50efedc7e5090c36df63043bd542e7e8508fa1c0 /src/core/hw/hw.cpp | |
| parent | citra-qt: Add GX command history viewer. (diff) | |
| download | yuzu-1dfa3928242ad486040b1c65768faa2c7fce4654.tar.gz yuzu-1dfa3928242ad486040b1c65768faa2c7fce4654.tar.xz yuzu-1dfa3928242ad486040b1c65768faa2c7fce4654.zip | |
Rename LCD to GPU.
Diffstat (limited to 'src/core/hw/hw.cpp')
| -rw-r--r-- | src/core/hw/hw.cpp | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/core/hw/hw.cpp b/src/core/hw/hw.cpp index 85669ae7f..ed70486e6 100644 --- a/src/core/hw/hw.cpp +++ b/src/core/hw/hw.cpp | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | #include "common/log.h" | 6 | #include "common/log.h" |
| 7 | 7 | ||
| 8 | #include "core/hw/hw.h" | 8 | #include "core/hw/hw.h" |
| 9 | #include "core/hw/lcd.h" | 9 | #include "core/hw/gpu.h" |
| 10 | #include "core/hw/ndma.h" | 10 | #include "core/hw/ndma.h" |
| 11 | 11 | ||
| 12 | namespace HW { | 12 | namespace HW { |
| @@ -34,7 +34,7 @@ enum { | |||
| 34 | VADDR_CDMA = 0xFFFDA000, // CoreLink DMA-330? Info | 34 | VADDR_CDMA = 0xFFFDA000, // CoreLink DMA-330? Info |
| 35 | VADDR_DSP_2 = 0x1ED03000, | 35 | VADDR_DSP_2 = 0x1ED03000, |
| 36 | VADDR_HASH_2 = 0x1EE01000, | 36 | VADDR_HASH_2 = 0x1EE01000, |
| 37 | VADDR_LCD = 0x1EF00000, | 37 | VADDR_GPU = 0x1EF00000, |
| 38 | }; | 38 | }; |
| 39 | 39 | ||
| 40 | template <typename T> | 40 | template <typename T> |
| @@ -46,8 +46,8 @@ inline void Read(T &var, const u32 addr) { | |||
| 46 | // NDMA::Read(var, addr); | 46 | // NDMA::Read(var, addr); |
| 47 | // break; | 47 | // break; |
| 48 | 48 | ||
| 49 | case VADDR_LCD: | 49 | case VADDR_GPU: |
| 50 | LCD::Read(var, addr); | 50 | GPU::Read(var, addr); |
| 51 | break; | 51 | break; |
| 52 | 52 | ||
| 53 | default: | 53 | default: |
| @@ -64,8 +64,8 @@ inline void Write(u32 addr, const T data) { | |||
| 64 | // NDMA::Write(addr, data); | 64 | // NDMA::Write(addr, data); |
| 65 | // break; | 65 | // break; |
| 66 | 66 | ||
| 67 | case VADDR_LCD: | 67 | case VADDR_GPU: |
| 68 | LCD::Write(addr, data); | 68 | GPU::Write(addr, data); |
| 69 | break; | 69 | break; |
| 70 | 70 | ||
| 71 | default: | 71 | default: |
| @@ -87,13 +87,13 @@ template void Write<u8>(u32 addr, const u8 data); | |||
| 87 | 87 | ||
| 88 | /// Update hardware | 88 | /// Update hardware |
| 89 | void Update() { | 89 | void Update() { |
| 90 | LCD::Update(); | 90 | GPU::Update(); |
| 91 | NDMA::Update(); | 91 | NDMA::Update(); |
| 92 | } | 92 | } |
| 93 | 93 | ||
| 94 | /// Initialize hardware | 94 | /// Initialize hardware |
| 95 | void Init() { | 95 | void Init() { |
| 96 | LCD::Init(); | 96 | GPU::Init(); |
| 97 | NDMA::Init(); | 97 | NDMA::Init(); |
| 98 | NOTICE_LOG(HW, "initialized OK"); | 98 | NOTICE_LOG(HW, "initialized OK"); |
| 99 | } | 99 | } |