diff options
| author | 2016-09-18 09:38:01 +0900 | |
|---|---|---|
| committer | 2016-09-18 09:38:01 +0900 | |
| commit | dc8479928c5aee4c6ad6fe4f59006fb604cee701 (patch) | |
| tree | 569a7f13128450bbab973236615587ff00bced5f /src/core/hw/gpu.cpp | |
| parent | Travis: Import Dolphin’s clang-format hook. (diff) | |
| download | yuzu-dc8479928c5aee4c6ad6fe4f59006fb604cee701.tar.gz yuzu-dc8479928c5aee4c6ad6fe4f59006fb604cee701.tar.xz yuzu-dc8479928c5aee4c6ad6fe4f59006fb604cee701.zip | |
Sources: Run clang-format on everything.
Diffstat (limited to 'src/core/hw/gpu.cpp')
| -rw-r--r-- | src/core/hw/gpu.cpp | 142 |
1 files changed, 85 insertions, 57 deletions
diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp index a4dfb7e43..bf2c066f4 100644 --- a/src/core/hw/gpu.cpp +++ b/src/core/hw/gpu.cpp | |||
| @@ -12,15 +12,15 @@ | |||
| 12 | #include "common/microprofile.h" | 12 | #include "common/microprofile.h" |
| 13 | #include "common/vector_math.h" | 13 | #include "common/vector_math.h" |
| 14 | 14 | ||
| 15 | #include "core/settings.h" | ||
| 16 | #include "core/memory.h" | ||
| 17 | #include "core/core_timing.h" | 15 | #include "core/core_timing.h" |
| 16 | #include "core/memory.h" | ||
| 17 | #include "core/settings.h" | ||
| 18 | 18 | ||
| 19 | #include "core/hle/service/gsp_gpu.h" | 19 | #include "core/hle/service/gsp_gpu.h" |
| 20 | #include "core/hle/service/hid/hid.h" | 20 | #include "core/hle/service/hid/hid.h" |
| 21 | 21 | ||
| 22 | #include "core/hw/hw.h" | ||
| 23 | #include "core/hw/gpu.h" | 22 | #include "core/hw/gpu.h" |
| 23 | #include "core/hw/hw.h" | ||
| 24 | 24 | ||
| 25 | #include "core/tracer/recorder.h" | 25 | #include "core/tracer/recorder.h" |
| 26 | 26 | ||
| @@ -32,7 +32,6 @@ | |||
| 32 | 32 | ||
| 33 | #include "video_core/debug_utils/debug_utils.h" | 33 | #include "video_core/debug_utils/debug_utils.h" |
| 34 | 34 | ||
| 35 | |||
| 36 | namespace GPU { | 35 | namespace GPU { |
| 37 | 36 | ||
| 38 | Regs g_regs; | 37 | Regs g_regs; |
| @@ -49,7 +48,7 @@ static u64 frame_count; | |||
| 49 | static bool last_skip_frame; | 48 | static bool last_skip_frame; |
| 50 | 49 | ||
| 51 | template <typename T> | 50 | template <typename T> |
| 52 | inline void Read(T &var, const u32 raw_addr) { | 51 | inline void Read(T& var, const u32 raw_addr) { |
| 53 | u32 addr = raw_addr - HW::VADDR_GPU; | 52 | u32 addr = raw_addr - HW::VADDR_GPU; |
| 54 | u32 index = addr / 4; | 53 | u32 index = addr / 4; |
| 55 | 54 | ||
| @@ -105,8 +104,7 @@ inline void Write(u32 addr, const T data) { | |||
| 105 | 104 | ||
| 106 | // Memory fills are triggered once the fill value is written. | 105 | // Memory fills are triggered once the fill value is written. |
| 107 | case GPU_REG_INDEX_WORKAROUND(memory_fill_config[0].trigger, 0x00004 + 0x3): | 106 | case GPU_REG_INDEX_WORKAROUND(memory_fill_config[0].trigger, 0x00004 + 0x3): |
| 108 | case GPU_REG_INDEX_WORKAROUND(memory_fill_config[1].trigger, 0x00008 + 0x3): | 107 | case GPU_REG_INDEX_WORKAROUND(memory_fill_config[1].trigger, 0x00008 + 0x3): { |
| 109 | { | ||
| 110 | const bool is_second_filler = (index != GPU_REG_INDEX(memory_fill_config[0].trigger)); | 108 | const bool is_second_filler = (index != GPU_REG_INDEX(memory_fill_config[0].trigger)); |
| 111 | auto& config = g_regs.memory_fill_config[is_second_filler]; | 109 | auto& config = g_regs.memory_fill_config[is_second_filler]; |
| 112 | 110 | ||
| @@ -125,7 +123,9 @@ inline void Write(u32 addr, const T data) { | |||
| 125 | // regions that were between surfaces or within the touching | 123 | // regions that were between surfaces or within the touching |
| 126 | // ones for cpu to manually fill here. | 124 | // ones for cpu to manually fill here. |
| 127 | if (!VideoCore::g_renderer->Rasterizer()->AccelerateFill(config)) { | 125 | if (!VideoCore::g_renderer->Rasterizer()->AccelerateFill(config)) { |
| 128 | Memory::RasterizerFlushAndInvalidateRegion(config.GetStartAddress(), config.GetEndAddress() - config.GetStartAddress()); | 126 | Memory::RasterizerFlushAndInvalidateRegion(config.GetStartAddress(), |
| 127 | config.GetEndAddress() - | ||
| 128 | config.GetStartAddress()); | ||
| 129 | 129 | ||
| 130 | if (config.fill_24bit) { | 130 | if (config.fill_24bit) { |
| 131 | // fill with 24-bit values | 131 | // fill with 24-bit values |
| @@ -150,7 +150,8 @@ inline void Write(u32 addr, const T data) { | |||
| 150 | } | 150 | } |
| 151 | } | 151 | } |
| 152 | 152 | ||
| 153 | LOG_TRACE(HW_GPU, "MemoryFill from 0x%08x to 0x%08x", config.GetStartAddress(), config.GetEndAddress()); | 153 | LOG_TRACE(HW_GPU, "MemoryFill from 0x%08x to 0x%08x", config.GetStartAddress(), |
| 154 | config.GetEndAddress()); | ||
| 154 | 155 | ||
| 155 | if (!is_second_filler) { | 156 | if (!is_second_filler) { |
| 156 | GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PSC0); | 157 | GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PSC0); |
| @@ -167,15 +168,15 @@ inline void Write(u32 addr, const T data) { | |||
| 167 | break; | 168 | break; |
| 168 | } | 169 | } |
| 169 | 170 | ||
| 170 | case GPU_REG_INDEX(display_transfer_config.trigger): | 171 | case GPU_REG_INDEX(display_transfer_config.trigger): { |
| 171 | { | ||
| 172 | MICROPROFILE_SCOPE(GPU_DisplayTransfer); | 172 | MICROPROFILE_SCOPE(GPU_DisplayTransfer); |
| 173 | 173 | ||
| 174 | const auto& config = g_regs.display_transfer_config; | 174 | const auto& config = g_regs.display_transfer_config; |
| 175 | if (config.trigger & 1) { | 175 | if (config.trigger & 1) { |
| 176 | 176 | ||
| 177 | if (Pica::g_debug_context) | 177 | if (Pica::g_debug_context) |
| 178 | Pica::g_debug_context->OnEvent(Pica::DebugContext::Event::IncomingDisplayTransfer, nullptr); | 178 | Pica::g_debug_context->OnEvent(Pica::DebugContext::Event::IncomingDisplayTransfer, |
| 179 | nullptr); | ||
| 179 | 180 | ||
| 180 | if (!VideoCore::g_renderer->Rasterizer()->AccelerateDisplayTransfer(config)) { | 181 | if (!VideoCore::g_renderer->Rasterizer()->AccelerateDisplayTransfer(config)) { |
| 181 | u8* src_pointer = Memory::GetPhysicalPointer(config.GetPhysicalInputAddress()); | 182 | u8* src_pointer = Memory::GetPhysicalPointer(config.GetPhysicalInputAddress()); |
| @@ -187,17 +188,23 @@ inline void Write(u32 addr, const T data) { | |||
| 187 | u32 output_width = config.texture_copy.output_width * 16; | 188 | u32 output_width = config.texture_copy.output_width * 16; |
| 188 | u32 output_gap = config.texture_copy.output_gap * 16; | 189 | u32 output_gap = config.texture_copy.output_gap * 16; |
| 189 | 190 | ||
| 190 | size_t contiguous_input_size = config.texture_copy.size / input_width * (input_width + input_gap); | 191 | size_t contiguous_input_size = |
| 191 | Memory::RasterizerFlushRegion(config.GetPhysicalInputAddress(), static_cast<u32>(contiguous_input_size)); | 192 | config.texture_copy.size / input_width * (input_width + input_gap); |
| 193 | Memory::RasterizerFlushRegion(config.GetPhysicalInputAddress(), | ||
| 194 | static_cast<u32>(contiguous_input_size)); | ||
| 192 | 195 | ||
| 193 | size_t contiguous_output_size = config.texture_copy.size / output_width * (output_width + output_gap); | 196 | size_t contiguous_output_size = |
| 194 | Memory::RasterizerFlushAndInvalidateRegion(config.GetPhysicalOutputAddress(), static_cast<u32>(contiguous_output_size)); | 197 | config.texture_copy.size / output_width * (output_width + output_gap); |
| 198 | Memory::RasterizerFlushAndInvalidateRegion( | ||
| 199 | config.GetPhysicalOutputAddress(), | ||
| 200 | static_cast<u32>(contiguous_output_size)); | ||
| 195 | 201 | ||
| 196 | u32 remaining_size = config.texture_copy.size; | 202 | u32 remaining_size = config.texture_copy.size; |
| 197 | u32 remaining_input = input_width; | 203 | u32 remaining_input = input_width; |
| 198 | u32 remaining_output = output_width; | 204 | u32 remaining_output = output_width; |
| 199 | while (remaining_size > 0) { | 205 | while (remaining_size > 0) { |
| 200 | u32 copy_size = std::min({ remaining_input, remaining_output, remaining_size }); | 206 | u32 copy_size = |
| 207 | std::min({remaining_input, remaining_output, remaining_size}); | ||
| 201 | 208 | ||
| 202 | std::memcpy(dst_pointer, src_pointer, copy_size); | 209 | std::memcpy(dst_pointer, src_pointer, copy_size); |
| 203 | src_pointer += copy_size; | 210 | src_pointer += copy_size; |
| @@ -217,10 +224,11 @@ inline void Write(u32 addr, const T data) { | |||
| 217 | } | 224 | } |
| 218 | } | 225 | } |
| 219 | 226 | ||
| 220 | LOG_TRACE(HW_GPU, "TextureCopy: 0x%X bytes from 0x%08X(%u+%u)-> 0x%08X(%u+%u), flags 0x%08X", | 227 | LOG_TRACE( |
| 221 | config.texture_copy.size, | 228 | HW_GPU, |
| 222 | config.GetPhysicalInputAddress(), input_width, input_gap, | 229 | "TextureCopy: 0x%X bytes from 0x%08X(%u+%u)-> 0x%08X(%u+%u), flags 0x%08X", |
| 223 | config.GetPhysicalOutputAddress(), output_width, output_gap, | 230 | config.texture_copy.size, config.GetPhysicalInputAddress(), input_width, |
| 231 | input_gap, config.GetPhysicalOutputAddress(), output_width, output_gap, | ||
| 224 | config.flags); | 232 | config.flags); |
| 225 | 233 | ||
| 226 | GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PPF); | 234 | GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PPF); |
| @@ -228,7 +236,8 @@ inline void Write(u32 addr, const T data) { | |||
| 228 | } | 236 | } |
| 229 | 237 | ||
| 230 | if (config.scaling > config.ScaleXY) { | 238 | if (config.scaling > config.ScaleXY) { |
| 231 | LOG_CRITICAL(HW_GPU, "Unimplemented display transfer scaling mode %u", config.scaling.Value()); | 239 | LOG_CRITICAL(HW_GPU, "Unimplemented display transfer scaling mode %u", |
| 240 | config.scaling.Value()); | ||
| 232 | UNIMPLEMENTED(); | 241 | UNIMPLEMENTED(); |
| 233 | break; | 242 | break; |
| 234 | } | 243 | } |
| @@ -245,11 +254,14 @@ inline void Write(u32 addr, const T data) { | |||
| 245 | u32 output_width = config.output_width >> horizontal_scale; | 254 | u32 output_width = config.output_width >> horizontal_scale; |
| 246 | u32 output_height = config.output_height >> vertical_scale; | 255 | u32 output_height = config.output_height >> vertical_scale; |
| 247 | 256 | ||
| 248 | u32 input_size = config.input_width * config.input_height * GPU::Regs::BytesPerPixel(config.input_format); | 257 | u32 input_size = config.input_width * config.input_height * |
| 249 | u32 output_size = output_width * output_height * GPU::Regs::BytesPerPixel(config.output_format); | 258 | GPU::Regs::BytesPerPixel(config.input_format); |
| 259 | u32 output_size = | ||
| 260 | output_width * output_height * GPU::Regs::BytesPerPixel(config.output_format); | ||
| 250 | 261 | ||
| 251 | Memory::RasterizerFlushRegion(config.GetPhysicalInputAddress(), input_size); | 262 | Memory::RasterizerFlushRegion(config.GetPhysicalInputAddress(), input_size); |
| 252 | Memory::RasterizerFlushAndInvalidateRegion(config.GetPhysicalOutputAddress(), output_size); | 263 | Memory::RasterizerFlushAndInvalidateRegion(config.GetPhysicalOutputAddress(), |
| 264 | output_size); | ||
| 253 | 265 | ||
| 254 | for (u32 y = 0; y < output_height; ++y) { | 266 | for (u32 y = 0; y < output_height; ++y) { |
| 255 | for (u32 x = 0; x < output_width; ++x) { | 267 | for (u32 x = 0; x < output_width; ++x) { |
| @@ -278,11 +290,14 @@ inline void Write(u32 addr, const T data) { | |||
| 278 | u32 coarse_y = y & ~7; | 290 | u32 coarse_y = y & ~7; |
| 279 | u32 stride = output_width * dst_bytes_per_pixel; | 291 | u32 stride = output_width * dst_bytes_per_pixel; |
| 280 | 292 | ||
| 281 | src_offset = (input_x + input_y * config.input_width) * src_bytes_per_pixel; | 293 | src_offset = |
| 282 | dst_offset = VideoCore::GetMortonOffset(x, y, dst_bytes_per_pixel) + coarse_y * stride; | 294 | (input_x + input_y * config.input_width) * src_bytes_per_pixel; |
| 295 | dst_offset = VideoCore::GetMortonOffset(x, y, dst_bytes_per_pixel) + | ||
| 296 | coarse_y * stride; | ||
| 283 | } else { | 297 | } else { |
| 284 | // Both input and output are linear | 298 | // Both input and output are linear |
| 285 | src_offset = (input_x + input_y * config.input_width) * src_bytes_per_pixel; | 299 | src_offset = |
| 300 | (input_x + input_y * config.input_width) * src_bytes_per_pixel; | ||
| 286 | dst_offset = (x + y * output_width) * dst_bytes_per_pixel; | 301 | dst_offset = (x + y * output_width) * dst_bytes_per_pixel; |
| 287 | } | 302 | } |
| 288 | } else { | 303 | } else { |
| @@ -291,7 +306,9 @@ inline void Write(u32 addr, const T data) { | |||
| 291 | u32 coarse_y = input_y & ~7; | 306 | u32 coarse_y = input_y & ~7; |
| 292 | u32 stride = config.input_width * src_bytes_per_pixel; | 307 | u32 stride = config.input_width * src_bytes_per_pixel; |
| 293 | 308 | ||
| 294 | src_offset = VideoCore::GetMortonOffset(input_x, input_y, src_bytes_per_pixel) + coarse_y * stride; | 309 | src_offset = VideoCore::GetMortonOffset(input_x, input_y, |
| 310 | src_bytes_per_pixel) + | ||
| 311 | coarse_y * stride; | ||
| 295 | dst_offset = (x + y * output_width) * dst_bytes_per_pixel; | 312 | dst_offset = (x + y * output_width) * dst_bytes_per_pixel; |
| 296 | } else { | 313 | } else { |
| 297 | // Both input and output are tiled | 314 | // Both input and output are tiled |
| @@ -301,20 +318,27 @@ inline void Write(u32 addr, const T data) { | |||
| 301 | u32 in_coarse_y = input_y & ~7; | 318 | u32 in_coarse_y = input_y & ~7; |
| 302 | u32 in_stride = config.input_width * src_bytes_per_pixel; | 319 | u32 in_stride = config.input_width * src_bytes_per_pixel; |
| 303 | 320 | ||
| 304 | src_offset = VideoCore::GetMortonOffset(input_x, input_y, src_bytes_per_pixel) + in_coarse_y * in_stride; | 321 | src_offset = VideoCore::GetMortonOffset(input_x, input_y, |
| 305 | dst_offset = VideoCore::GetMortonOffset(x, y, dst_bytes_per_pixel) + out_coarse_y * out_stride; | 322 | src_bytes_per_pixel) + |
| 323 | in_coarse_y * in_stride; | ||
| 324 | dst_offset = VideoCore::GetMortonOffset(x, y, dst_bytes_per_pixel) + | ||
| 325 | out_coarse_y * out_stride; | ||
| 306 | } | 326 | } |
| 307 | } | 327 | } |
| 308 | 328 | ||
| 309 | const u8* src_pixel = src_pointer + src_offset; | 329 | const u8* src_pixel = src_pointer + src_offset; |
| 310 | src_color = DecodePixel(config.input_format, src_pixel); | 330 | src_color = DecodePixel(config.input_format, src_pixel); |
| 311 | if (config.scaling == config.ScaleX) { | 331 | if (config.scaling == config.ScaleX) { |
| 312 | Math::Vec4<u8> pixel = DecodePixel(config.input_format, src_pixel + src_bytes_per_pixel); | 332 | Math::Vec4<u8> pixel = |
| 333 | DecodePixel(config.input_format, src_pixel + src_bytes_per_pixel); | ||
| 313 | src_color = ((src_color + pixel) / 2).Cast<u8>(); | 334 | src_color = ((src_color + pixel) / 2).Cast<u8>(); |
| 314 | } else if (config.scaling == config.ScaleXY) { | 335 | } else if (config.scaling == config.ScaleXY) { |
| 315 | Math::Vec4<u8> pixel1 = DecodePixel(config.input_format, src_pixel + 1 * src_bytes_per_pixel); | 336 | Math::Vec4<u8> pixel1 = DecodePixel( |
| 316 | Math::Vec4<u8> pixel2 = DecodePixel(config.input_format, src_pixel + 2 * src_bytes_per_pixel); | 337 | config.input_format, src_pixel + 1 * src_bytes_per_pixel); |
| 317 | Math::Vec4<u8> pixel3 = DecodePixel(config.input_format, src_pixel + 3 * src_bytes_per_pixel); | 338 | Math::Vec4<u8> pixel2 = DecodePixel( |
| 339 | config.input_format, src_pixel + 2 * src_bytes_per_pixel); | ||
| 340 | Math::Vec4<u8> pixel3 = DecodePixel( | ||
| 341 | config.input_format, src_pixel + 3 * src_bytes_per_pixel); | ||
| 318 | src_color = (((src_color + pixel1) + (pixel2 + pixel3)) / 4).Cast<u8>(); | 342 | src_color = (((src_color + pixel1) + (pixel2 + pixel3)) / 4).Cast<u8>(); |
| 319 | } | 343 | } |
| 320 | 344 | ||
| @@ -341,17 +365,20 @@ inline void Write(u32 addr, const T data) { | |||
| 341 | break; | 365 | break; |
| 342 | 366 | ||
| 343 | default: | 367 | default: |
| 344 | LOG_ERROR(HW_GPU, "Unknown destination framebuffer format %x", config.output_format.Value()); | 368 | LOG_ERROR(HW_GPU, "Unknown destination framebuffer format %x", |
| 369 | config.output_format.Value()); | ||
| 345 | break; | 370 | break; |
| 346 | } | 371 | } |
| 347 | } | 372 | } |
| 348 | } | 373 | } |
| 349 | 374 | ||
| 350 | LOG_TRACE(HW_GPU, "DisplayTriggerTransfer: 0x%08x bytes from 0x%08x(%ux%u)-> 0x%08x(%ux%u), dst format %x, flags 0x%08X", | 375 | LOG_TRACE(HW_GPU, "DisplayTriggerTransfer: 0x%08x bytes from 0x%08x(%ux%u)-> " |
| 351 | config.output_height * output_width * GPU::Regs::BytesPerPixel(config.output_format), | 376 | "0x%08x(%ux%u), dst format %x, flags 0x%08X", |
| 352 | config.GetPhysicalInputAddress(), config.input_width.Value(), config.input_height.Value(), | 377 | config.output_height * output_width * |
| 353 | config.GetPhysicalOutputAddress(), output_width, output_height, | 378 | GPU::Regs::BytesPerPixel(config.output_format), |
| 354 | config.output_format.Value(), config.flags); | 379 | config.GetPhysicalInputAddress(), config.input_width.Value(), |
| 380 | config.input_height.Value(), config.GetPhysicalOutputAddress(), | ||
| 381 | output_width, output_height, config.output_format.Value(), config.flags); | ||
| 355 | } | 382 | } |
| 356 | 383 | ||
| 357 | g_regs.display_transfer_config.trigger = 0; | 384 | g_regs.display_transfer_config.trigger = 0; |
| @@ -361,17 +388,16 @@ inline void Write(u32 addr, const T data) { | |||
| 361 | } | 388 | } |
| 362 | 389 | ||
| 363 | // Seems like writing to this register triggers processing | 390 | // Seems like writing to this register triggers processing |
| 364 | case GPU_REG_INDEX(command_processor_config.trigger): | 391 | case GPU_REG_INDEX(command_processor_config.trigger): { |
| 365 | { | ||
| 366 | const auto& config = g_regs.command_processor_config; | 392 | const auto& config = g_regs.command_processor_config; |
| 367 | if (config.trigger & 1) | 393 | if (config.trigger & 1) { |
| 368 | { | ||
| 369 | MICROPROFILE_SCOPE(GPU_CmdlistProcessing); | 394 | MICROPROFILE_SCOPE(GPU_CmdlistProcessing); |
| 370 | 395 | ||
| 371 | u32* buffer = (u32*)Memory::GetPhysicalPointer(config.GetPhysicalAddress()); | 396 | u32* buffer = (u32*)Memory::GetPhysicalPointer(config.GetPhysicalAddress()); |
| 372 | 397 | ||
| 373 | if (Pica::g_debug_context && Pica::g_debug_context->recorder) { | 398 | if (Pica::g_debug_context && Pica::g_debug_context->recorder) { |
| 374 | Pica::g_debug_context->recorder->MemoryAccessed((u8*)buffer, config.size * sizeof(u32), config.GetPhysicalAddress()); | 399 | Pica::g_debug_context->recorder->MemoryAccessed( |
| 400 | (u8*)buffer, config.size * sizeof(u32), config.GetPhysicalAddress()); | ||
| 375 | } | 401 | } |
| 376 | 402 | ||
| 377 | Pica::CommandProcessor::ProcessCommandList(buffer, config.size); | 403 | Pica::CommandProcessor::ProcessCommandList(buffer, config.size); |
| @@ -389,16 +415,17 @@ inline void Write(u32 addr, const T data) { | |||
| 389 | // This is happening *after* handling the write to make sure we properly catch all memory reads. | 415 | // This is happening *after* handling the write to make sure we properly catch all memory reads. |
| 390 | if (Pica::g_debug_context && Pica::g_debug_context->recorder) { | 416 | if (Pica::g_debug_context && Pica::g_debug_context->recorder) { |
| 391 | // addr + GPU VBase - IO VBase + IO PBase | 417 | // addr + GPU VBase - IO VBase + IO PBase |
| 392 | Pica::g_debug_context->recorder->RegisterWritten<T>(addr + 0x1EF00000 - 0x1EC00000 + 0x10100000, data); | 418 | Pica::g_debug_context->recorder->RegisterWritten<T>( |
| 419 | addr + 0x1EF00000 - 0x1EC00000 + 0x10100000, data); | ||
| 393 | } | 420 | } |
| 394 | } | 421 | } |
| 395 | 422 | ||
| 396 | // Explicitly instantiate template functions because we aren't defining this in the header: | 423 | // Explicitly instantiate template functions because we aren't defining this in the header: |
| 397 | 424 | ||
| 398 | template void Read<u64>(u64 &var, const u32 addr); | 425 | template void Read<u64>(u64& var, const u32 addr); |
| 399 | template void Read<u32>(u32 &var, const u32 addr); | 426 | template void Read<u32>(u32& var, const u32 addr); |
| 400 | template void Read<u16>(u16 &var, const u32 addr); | 427 | template void Read<u16>(u16& var, const u32 addr); |
| 401 | template void Read<u8>(u8 &var, const u32 addr); | 428 | template void Read<u8>(u8& var, const u32 addr); |
| 402 | 429 | ||
| 403 | template void Write<u64>(u32 addr, const u64 data); | 430 | template void Write<u64>(u32 addr, const u64 data); |
| 404 | template void Write<u32>(u32 addr, const u32 data); | 431 | template void Write<u32>(u32 addr, const u32 data); |
| @@ -417,8 +444,9 @@ static void VBlankCallback(u64 userdata, int cycles_late) { | |||
| 417 | // - If frameskip == 0 (disabled), always swap buffers | 444 | // - If frameskip == 0 (disabled), always swap buffers |
| 418 | // - If frameskip == 1, swap buffers every other frame (starting from the first frame) | 445 | // - If frameskip == 1, swap buffers every other frame (starting from the first frame) |
| 419 | // - If frameskip > 1, swap buffers every frameskip^n frames (starting from the second frame) | 446 | // - If frameskip > 1, swap buffers every frameskip^n frames (starting from the second frame) |
| 420 | if ((((Settings::values.frame_skip != 1) ^ last_skip_frame) && last_skip_frame != g_skip_frame) || | 447 | if ((((Settings::values.frame_skip != 1) ^ last_skip_frame) && |
| 421 | Settings::values.frame_skip == 0) { | 448 | last_skip_frame != g_skip_frame) || |
| 449 | Settings::values.frame_skip == 0) { | ||
| 422 | VideoCore::g_renderer->SwapBuffers(); | 450 | VideoCore::g_renderer->SwapBuffers(); |
| 423 | } | 451 | } |
| 424 | 452 | ||
| @@ -448,12 +476,12 @@ void Init() { | |||
| 448 | // .. or at least these are the ones used by system applets. | 476 | // .. or at least these are the ones used by system applets. |
| 449 | // There's probably a smarter way to come up with addresses | 477 | // There's probably a smarter way to come up with addresses |
| 450 | // like this which does not require hardcoding. | 478 | // like this which does not require hardcoding. |
| 451 | framebuffer_top.address_left1 = 0x181E6000; | 479 | framebuffer_top.address_left1 = 0x181E6000; |
| 452 | framebuffer_top.address_left2 = 0x1822C800; | 480 | framebuffer_top.address_left2 = 0x1822C800; |
| 453 | framebuffer_top.address_right1 = 0x18273000; | 481 | framebuffer_top.address_right1 = 0x18273000; |
| 454 | framebuffer_top.address_right2 = 0x182B9800; | 482 | framebuffer_top.address_right2 = 0x182B9800; |
| 455 | framebuffer_sub.address_left1 = 0x1848F000; | 483 | framebuffer_sub.address_left1 = 0x1848F000; |
| 456 | framebuffer_sub.address_left2 = 0x184C7800; | 484 | framebuffer_sub.address_left2 = 0x184C7800; |
| 457 | 485 | ||
| 458 | framebuffer_top.width.Assign(240); | 486 | framebuffer_top.width.Assign(240); |
| 459 | framebuffer_top.height.Assign(400); | 487 | framebuffer_top.height.Assign(400); |