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authorGravatar Tony Wasserka2014-05-17 23:01:58 +0200
committerGravatar bunnei2014-06-12 06:10:50 -0400
commitd4530765ceaf75cecd16b3ed5a7829611af2d82c (patch)
tree16e0e9cd41102a5201bc97fefe5dd0d1ebebf114 /src/core/hw/gpu.cpp
parentRename LCD to GPU. (diff)
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GPU: Cleanup register definitions.
Diffstat (limited to 'src/core/hw/gpu.cpp')
-rw-r--r--src/core/hw/gpu.cpp26
1 files changed, 13 insertions, 13 deletions
diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp
index 632e1aaac..ec2d0e156 100644
--- a/src/core/hw/gpu.cpp
+++ b/src/core/hw/gpu.cpp
@@ -86,39 +86,39 @@ const u8* GetFramebufferPointer(const u32 address) {
86template <typename T> 86template <typename T>
87inline void Read(T &var, const u32 addr) { 87inline void Read(T &var, const u32 addr) {
88 switch (addr) { 88 switch (addr) {
89 case REG_FRAMEBUFFER_TOP_LEFT_1: 89 case Registers::FramebufferTopLeft1:
90 var = g_regs.framebuffer_top_left_1; 90 var = g_regs.framebuffer_top_left_1;
91 break; 91 break;
92 92
93 case REG_FRAMEBUFFER_TOP_LEFT_2: 93 case Registers::FramebufferTopLeft2:
94 var = g_regs.framebuffer_top_left_2; 94 var = g_regs.framebuffer_top_left_2;
95 break; 95 break;
96 96
97 case REG_FRAMEBUFFER_TOP_RIGHT_1: 97 case Registers::FramebufferTopRight1:
98 var = g_regs.framebuffer_top_right_1; 98 var = g_regs.framebuffer_top_right_1;
99 break; 99 break;
100 100
101 case REG_FRAMEBUFFER_TOP_RIGHT_2: 101 case Registers::FramebufferTopRight2:
102 var = g_regs.framebuffer_top_right_2; 102 var = g_regs.framebuffer_top_right_2;
103 break; 103 break;
104 104
105 case REG_FRAMEBUFFER_SUB_LEFT_1: 105 case Registers::FramebufferSubLeft1:
106 var = g_regs.framebuffer_sub_left_1; 106 var = g_regs.framebuffer_sub_left_1;
107 break; 107 break;
108 108
109 case REG_FRAMEBUFFER_SUB_RIGHT_1: 109 case Registers::FramebufferSubRight1:
110 var = g_regs.framebuffer_sub_right_1; 110 var = g_regs.framebuffer_sub_right_1;
111 break; 111 break;
112 112
113 case CommandListSize: 113 case Registers::CommandListSize:
114 var = g_regs.command_list_size; 114 var = g_regs.command_list_size;
115 break; 115 break;
116 116
117 case CommandListAddress: 117 case Registers::CommandListAddress:
118 var = g_regs.command_list_address; 118 var = g_regs.command_list_address;
119 break; 119 break;
120 120
121 case ProcessCommandList: 121 case Registers::ProcessCommandList:
122 var = g_regs.command_processing_enabled; 122 var = g_regs.command_processing_enabled;
123 break; 123 break;
124 124
@@ -130,16 +130,16 @@ inline void Read(T &var, const u32 addr) {
130 130
131template <typename T> 131template <typename T>
132inline void Write(u32 addr, const T data) { 132inline void Write(u32 addr, const T data) {
133 switch (addr) { 133 switch (static_cast<Registers::Id>(addr)) {
134 case CommandListSize: 134 case Registers::CommandListSize:
135 g_regs.command_list_size = data; 135 g_regs.command_list_size = data;
136 break; 136 break;
137 137
138 case CommandListAddress: 138 case Registers::CommandListAddress:
139 g_regs.command_list_address = data; 139 g_regs.command_list_address = data;
140 break; 140 break;
141 141
142 case ProcessCommandList: 142 case Registers::ProcessCommandList:
143 g_regs.command_processing_enabled = data; 143 g_regs.command_processing_enabled = data;
144 if (g_regs.command_processing_enabled & 1) 144 if (g_regs.command_processing_enabled & 1)
145 { 145 {