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| author | 2014-06-01 00:08:00 +0200 | |
|---|---|---|
| committer | 2014-07-23 00:33:08 +0200 | |
| commit | 16bbc4f81b89462ff1c9e9364e0ca7ee1289c3b3 (patch) | |
| tree | 31b0a53d80f519d543b8ec47d8b937c70fea2cda /src/core/hw/gpu.cpp | |
| parent | GSP: HLE GXCommandId::SET_DISPLAY_TRANSFER and GXCommandId::SET_TEXTURE_COPY. (diff) | |
| download | yuzu-16bbc4f81b89462ff1c9e9364e0ca7ee1289c3b3.tar.gz yuzu-16bbc4f81b89462ff1c9e9364e0ca7ee1289c3b3.tar.xz yuzu-16bbc4f81b89462ff1c9e9364e0ca7ee1289c3b3.zip | |
GPU: Add display transfer configuration.
Diffstat (limited to 'src/core/hw/gpu.cpp')
| -rw-r--r-- | src/core/hw/gpu.cpp | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp index f0ca4eada..a400338b5 100644 --- a/src/core/hw/gpu.cpp +++ b/src/core/hw/gpu.cpp | |||
| @@ -108,6 +108,31 @@ inline void Read(T &var, const u32 addr) { | |||
| 108 | var = g_regs.framebuffer_sub_right_1; | 108 | var = g_regs.framebuffer_sub_right_1; |
| 109 | break; | 109 | break; |
| 110 | 110 | ||
| 111 | case Registers::DisplayInputBufferAddr: | ||
| 112 | var = g_regs.display_transfer.input_address; | ||
| 113 | break; | ||
| 114 | |||
| 115 | case Registers::DisplayOutputBufferAddr: | ||
| 116 | var = g_regs.display_transfer.output_address; | ||
| 117 | break; | ||
| 118 | |||
| 119 | case Registers::DisplayOutputBufferSize: | ||
| 120 | var = g_regs.display_transfer.output_size; | ||
| 121 | break; | ||
| 122 | |||
| 123 | case Registers::DisplayInputBufferSize: | ||
| 124 | var = g_regs.display_transfer.input_size; | ||
| 125 | break; | ||
| 126 | |||
| 127 | case Registers::DisplayTransferFlags: | ||
| 128 | var = g_regs.display_transfer.flags; | ||
| 129 | break; | ||
| 130 | |||
| 131 | // Not sure if this is supposed to be readable | ||
| 132 | case Registers::DisplayTriggerTransfer: | ||
| 133 | var = g_regs.display_transfer.trigger; | ||
| 134 | break; | ||
| 135 | |||
| 111 | case Registers::CommandListSize: | 136 | case Registers::CommandListSize: |
| 112 | var = g_regs.command_list_size; | 137 | var = g_regs.command_list_size; |
| 113 | break; | 138 | break; |
| @@ -129,6 +154,33 @@ inline void Read(T &var, const u32 addr) { | |||
| 129 | template <typename T> | 154 | template <typename T> |
| 130 | inline void Write(u32 addr, const T data) { | 155 | inline void Write(u32 addr, const T data) { |
| 131 | switch (static_cast<Registers::Id>(addr)) { | 156 | switch (static_cast<Registers::Id>(addr)) { |
| 157 | case Registers::DisplayInputBufferAddr: | ||
| 158 | g_regs.display_transfer.input_address = data; | ||
| 159 | break; | ||
| 160 | |||
| 161 | case Registers::DisplayOutputBufferAddr: | ||
| 162 | g_regs.display_transfer.output_address = data; | ||
| 163 | break; | ||
| 164 | |||
| 165 | case Registers::DisplayOutputBufferSize: | ||
| 166 | g_regs.display_transfer.output_size = data; | ||
| 167 | break; | ||
| 168 | |||
| 169 | case Registers::DisplayInputBufferSize: | ||
| 170 | g_regs.display_transfer.input_size = data; | ||
| 171 | break; | ||
| 172 | |||
| 173 | case Registers::DisplayTransferFlags: | ||
| 174 | g_regs.display_transfer.flags = data; | ||
| 175 | break; | ||
| 176 | |||
| 177 | case Registers::DisplayTriggerTransfer: | ||
| 178 | g_regs.display_transfer.trigger = data; | ||
| 179 | if (g_regs.display_transfer.trigger & 1) { | ||
| 180 | // TODO: Perform display transfer! | ||
| 181 | } | ||
| 182 | break; | ||
| 183 | |||
| 132 | case Registers::CommandListSize: | 184 | case Registers::CommandListSize: |
| 133 | g_regs.command_list_size = data; | 185 | g_regs.command_list_size = data; |
| 134 | break; | 186 | break; |