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authorGravatar bunnei2015-02-18 17:19:38 -0500
committerGravatar bunnei2015-02-18 17:19:38 -0500
commit4a48b017ca7fe8fe68dfc84d70864ef6aea6a266 (patch)
treedcd7914a3a2147790d384ce0992f70d40bce8704 /src/core/hle
parentMerge pull request #570 from purpasmart96/config_mem (diff)
parentPica/Rasterizer: Replace exit() calls with UNIMPLEMENTED(). (diff)
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Merge pull request #562 from neobrain/pica_progress3
More PICA200 Emulation Fixes
Diffstat (limited to 'src/core/hle')
-rw-r--r--src/core/hle/service/gsp_gpu.cpp34
-rw-r--r--src/core/hle/service/gsp_gpu.h4
2 files changed, 21 insertions, 17 deletions
diff --git a/src/core/hle/service/gsp_gpu.cpp b/src/core/hle/service/gsp_gpu.cpp
index 31e61391f..c23cfa3c8 100644
--- a/src/core/hle/service/gsp_gpu.cpp
+++ b/src/core/hle/service/gsp_gpu.cpp
@@ -368,28 +368,28 @@ static void ExecuteCommand(const Command& command, u32 thread_id) {
368 case CommandId::SET_MEMORY_FILL: 368 case CommandId::SET_MEMORY_FILL:
369 { 369 {
370 auto& params = command.memory_fill; 370 auto& params = command.memory_fill;
371 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].address_start)), 371 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].address_start)),
372 Memory::VirtualToPhysicalAddress(params.start1) >> 3); 372 Memory::VirtualToPhysicalAddress(params.start1) >> 3);
373 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].address_end)), 373 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].address_end)),
374 Memory::VirtualToPhysicalAddress(params.end1) >> 3); 374 Memory::VirtualToPhysicalAddress(params.end1) >> 3);
375 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].size)), params.end1 - params.start1); 375 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].value_32bit)), params.value1);
376 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].value)), params.value1); 376 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].control)), params.control1);
377 377
378 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].address_start)), 378 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].address_start)),
379 Memory::VirtualToPhysicalAddress(params.start2) >> 3); 379 Memory::VirtualToPhysicalAddress(params.start2) >> 3);
380 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].address_end)), 380 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].address_end)),
381 Memory::VirtualToPhysicalAddress(params.end2) >> 3); 381 Memory::VirtualToPhysicalAddress(params.end2) >> 3);
382 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].size)), params.end2 - params.start2); 382 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].value_32bit)), params.value2);
383 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].value)), params.value2); 383 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].control)), params.control2);
384 break; 384 break;
385 } 385 }
386 386
387 case CommandId::SET_DISPLAY_TRANSFER: 387 case CommandId::SET_DISPLAY_TRANSFER:
388 { 388 {
389 auto& params = command.image_copy; 389 auto& params = command.image_copy;
390 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.input_address)), 390 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.input_address)),
391 Memory::VirtualToPhysicalAddress(params.in_buffer_address) >> 3); 391 Memory::VirtualToPhysicalAddress(params.in_buffer_address) >> 3);
392 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.output_address)), 392 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.output_address)),
393 Memory::VirtualToPhysicalAddress(params.out_buffer_address) >> 3); 393 Memory::VirtualToPhysicalAddress(params.out_buffer_address) >> 3);
394 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.input_size)), params.in_buffer_size); 394 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.input_size)), params.in_buffer_size);
395 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.output_size)), params.out_buffer_size); 395 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.output_size)), params.out_buffer_size);
@@ -402,9 +402,9 @@ static void ExecuteCommand(const Command& command, u32 thread_id) {
402 case CommandId::SET_TEXTURE_COPY: 402 case CommandId::SET_TEXTURE_COPY:
403 { 403 {
404 auto& params = command.image_copy; 404 auto& params = command.image_copy;
405 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.input_address)), 405 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.input_address)),
406 Memory::VirtualToPhysicalAddress(params.in_buffer_address) >> 3); 406 Memory::VirtualToPhysicalAddress(params.in_buffer_address) >> 3);
407 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.output_address)), 407 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.output_address)),
408 Memory::VirtualToPhysicalAddress(params.out_buffer_address) >> 3); 408 Memory::VirtualToPhysicalAddress(params.out_buffer_address) >> 3);
409 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.input_size)), params.in_buffer_size); 409 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.input_size)), params.in_buffer_size);
410 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.output_size)), params.out_buffer_size); 410 WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.output_size)), params.out_buffer_size);
diff --git a/src/core/hle/service/gsp_gpu.h b/src/core/hle/service/gsp_gpu.h
index 65abb194a..a435d418a 100644
--- a/src/core/hle/service/gsp_gpu.h
+++ b/src/core/hle/service/gsp_gpu.h
@@ -109,9 +109,13 @@ struct Command {
109 u32 start1; 109 u32 start1;
110 u32 value1; 110 u32 value1;
111 u32 end1; 111 u32 end1;
112
112 u32 start2; 113 u32 start2;
113 u32 value2; 114 u32 value2;
114 u32 end2; 115 u32 end2;
116
117 u16 control1;
118 u16 control2;
115 } memory_fill; 119 } memory_fill;
116 120
117 struct { 121 struct {