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| author | 2014-05-17 22:50:33 +0200 | |
|---|---|---|
| committer | 2014-06-12 06:10:49 -0400 | |
| commit | 1dfa3928242ad486040b1c65768faa2c7fce4654 (patch) | |
| tree | 50efedc7e5090c36df63043bd542e7e8508fa1c0 /src/core/hle/service/gsp.cpp | |
| parent | citra-qt: Add GX command history viewer. (diff) | |
| download | yuzu-1dfa3928242ad486040b1c65768faa2c7fce4654.tar.gz yuzu-1dfa3928242ad486040b1c65768faa2c7fce4654.tar.xz yuzu-1dfa3928242ad486040b1c65768faa2c7fce4654.zip | |
Rename LCD to GPU.
Diffstat (limited to 'src/core/hle/service/gsp.cpp')
| -rw-r--r-- | src/core/hle/service/gsp.cpp | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/core/hle/service/gsp.cpp b/src/core/hle/service/gsp.cpp index a42759053..d51e6c66d 100644 --- a/src/core/hle/service/gsp.cpp +++ b/src/core/hle/service/gsp.cpp | |||
| @@ -10,7 +10,7 @@ | |||
| 10 | #include "core/hle/hle.h" | 10 | #include "core/hle/hle.h" |
| 11 | #include "core/hle/service/gsp.h" | 11 | #include "core/hle/service/gsp.h" |
| 12 | 12 | ||
| 13 | #include "core/hw/lcd.h" | 13 | #include "core/hw/gpu.h" |
| 14 | 14 | ||
| 15 | #include "video_core/gpu_debugger.h" | 15 | #include "video_core/gpu_debugger.h" |
| 16 | 16 | ||
| @@ -69,8 +69,8 @@ enum { | |||
| 69 | 69 | ||
| 70 | /// Read a GSP GPU hardware register | 70 | /// Read a GSP GPU hardware register |
| 71 | void ReadHWRegs(Service::Interface* self) { | 71 | void ReadHWRegs(Service::Interface* self) { |
| 72 | static const u32 framebuffer_1[] = {LCD::PADDR_VRAM_TOP_LEFT_FRAME1, LCD::PADDR_VRAM_TOP_RIGHT_FRAME1}; | 72 | static const u32 framebuffer_1[] = {GPU::PADDR_VRAM_TOP_LEFT_FRAME1, GPU::PADDR_VRAM_TOP_RIGHT_FRAME1}; |
| 73 | static const u32 framebuffer_2[] = {LCD::PADDR_VRAM_TOP_LEFT_FRAME2, LCD::PADDR_VRAM_TOP_RIGHT_FRAME2}; | 73 | static const u32 framebuffer_2[] = {GPU::PADDR_VRAM_TOP_LEFT_FRAME2, GPU::PADDR_VRAM_TOP_RIGHT_FRAME2}; |
| 74 | 74 | ||
| 75 | u32* cmd_buff = Service::GetCommandBuffer(); | 75 | u32* cmd_buff = Service::GetCommandBuffer(); |
| 76 | u32 reg_addr = cmd_buff[1]; | 76 | u32 reg_addr = cmd_buff[1]; |
| @@ -85,13 +85,13 @@ void ReadHWRegs(Service::Interface* self) { | |||
| 85 | 85 | ||
| 86 | // Top framebuffer 1 addresses | 86 | // Top framebuffer 1 addresses |
| 87 | case REG_FRAMEBUFFER_1: | 87 | case REG_FRAMEBUFFER_1: |
| 88 | LCD::SetFramebufferLocation(LCD::FRAMEBUFFER_LOCATION_VRAM); | 88 | GPU::SetFramebufferLocation(GPU::FRAMEBUFFER_LOCATION_VRAM); |
| 89 | memcpy(dst, framebuffer_1, size); | 89 | memcpy(dst, framebuffer_1, size); |
| 90 | break; | 90 | break; |
| 91 | 91 | ||
| 92 | // Top framebuffer 2 addresses | 92 | // Top framebuffer 2 addresses |
| 93 | case REG_FRAMEBUFFER_2: | 93 | case REG_FRAMEBUFFER_2: |
| 94 | LCD::SetFramebufferLocation(LCD::FRAMEBUFFER_LOCATION_VRAM); | 94 | GPU::SetFramebufferLocation(GPU::FRAMEBUFFER_LOCATION_VRAM); |
| 95 | memcpy(dst, framebuffer_2, size); | 95 | memcpy(dst, framebuffer_2, size); |
| 96 | break; | 96 | break; |
| 97 | 97 | ||
| @@ -123,9 +123,9 @@ void TriggerCmdReqQueue(Service::Interface* self) { | |||
| 123 | break; | 123 | break; |
| 124 | 124 | ||
| 125 | case GXCommandId::SET_COMMAND_LIST_LAST: | 125 | case GXCommandId::SET_COMMAND_LIST_LAST: |
| 126 | LCD::Write<u32>(LCD::CommandListAddress, cmd_buff[1] >> 3); | 126 | GPU::Write<u32>(GPU::CommandListAddress, cmd_buff[1] >> 3); |
| 127 | LCD::Write<u32>(LCD::CommandListSize, cmd_buff[2] >> 3); | 127 | GPU::Write<u32>(GPU::CommandListSize, cmd_buff[2] >> 3); |
| 128 | LCD::Write<u32>(LCD::ProcessCommandList, 1); // TODO: Not sure if we are supposed to always write this | 128 | GPU::Write<u32>(GPU::ProcessCommandList, 1); // TODO: Not sure if we are supposed to always write this |
| 129 | break; | 129 | break; |
| 130 | 130 | ||
| 131 | case GXCommandId::SET_MEMORY_FILL: | 131 | case GXCommandId::SET_MEMORY_FILL: |