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authorGravatar bunnei2018-10-23 18:42:15 -0400
committerGravatar bunnei2018-10-25 18:03:54 -0400
commitc2049aa4e5e7a77b0f1988e7082921b2e5083fa6 (patch)
treed42024d6da32d202ed5927bf0e94d11887413c5a /src/core/hle/kernel/process.cpp
parentKernel/Memory: Added a function to first a suitable guest address at which to... (diff)
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process: LoadModule should clear JIT instruction cache.
Diffstat (limited to 'src/core/hle/kernel/process.cpp')
-rw-r--r--src/core/hle/kernel/process.cpp6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/core/hle/kernel/process.cpp b/src/core/hle/kernel/process.cpp
index 073dd5a7d..420218d59 100644
--- a/src/core/hle/kernel/process.cpp
+++ b/src/core/hle/kernel/process.cpp
@@ -232,6 +232,12 @@ void Process::LoadModule(CodeSet module_, VAddr base_addr) {
232 MapSegment(module_.CodeSegment(), VMAPermission::ReadExecute, MemoryState::CodeStatic); 232 MapSegment(module_.CodeSegment(), VMAPermission::ReadExecute, MemoryState::CodeStatic);
233 MapSegment(module_.RODataSegment(), VMAPermission::Read, MemoryState::CodeMutable); 233 MapSegment(module_.RODataSegment(), VMAPermission::Read, MemoryState::CodeMutable);
234 MapSegment(module_.DataSegment(), VMAPermission::ReadWrite, MemoryState::CodeMutable); 234 MapSegment(module_.DataSegment(), VMAPermission::ReadWrite, MemoryState::CodeMutable);
235
236 // Clear instruction cache in CPU JIT
237 Core::System::GetInstance().ArmInterface(0).ClearInstructionCache();
238 Core::System::GetInstance().ArmInterface(1).ClearInstructionCache();
239 Core::System::GetInstance().ArmInterface(2).ClearInstructionCache();
240 Core::System::GetInstance().ArmInterface(3).ClearInstructionCache();
235} 241}
236 242
237ResultVal<VAddr> Process::HeapAllocate(VAddr target, u64 size, VMAPermission perms) { 243ResultVal<VAddr> Process::HeapAllocate(VAddr target, u64 size, VMAPermission perms) {