summaryrefslogtreecommitdiff
path: root/src/core/gdbstub/gdbstub.cpp
diff options
context:
space:
mode:
authorGravatar Lioncash2018-09-18 02:49:40 -0400
committerGravatar Lioncash2018-09-18 03:20:04 -0400
commitb51e7e028839a5d1cb92024e327b7f8b8fb62f40 (patch)
tree93d109f54b71cb7635d1435ad4f12b678ef08d27 /src/core/gdbstub/gdbstub.cpp
parentMerge pull request #1311 from FernandoS27/fast-swizzle (diff)
downloadyuzu-b51e7e028839a5d1cb92024e327b7f8b8fb62f40.tar.gz
yuzu-b51e7e028839a5d1cb92024e327b7f8b8fb62f40.tar.xz
yuzu-b51e7e028839a5d1cb92024e327b7f8b8fb62f40.zip
arm_interface: Remove ARM11-isms from the CPU interface
This modifies the CPU interface to more accurately match an AArch64-supporting CPU as opposed to an ARM11 one. Two of the methods don't even make sense to keep around for this interface, as Adv Simd is used, rather than the VFP in the primary execution state. This is essentially a modernization change that should have occurred from the get-go.
Diffstat (limited to 'src/core/gdbstub/gdbstub.cpp')
-rw-r--r--src/core/gdbstub/gdbstub.cpp50
1 files changed, 25 insertions, 25 deletions
diff --git a/src/core/gdbstub/gdbstub.cpp b/src/core/gdbstub/gdbstub.cpp
index cfaf20a88..1b04f68bf 100644
--- a/src/core/gdbstub/gdbstub.cpp
+++ b/src/core/gdbstub/gdbstub.cpp
@@ -65,9 +65,9 @@ constexpr u32 MSG_WAITALL = 8;
65constexpr u32 LR_REGISTER = 30; 65constexpr u32 LR_REGISTER = 30;
66constexpr u32 SP_REGISTER = 31; 66constexpr u32 SP_REGISTER = 31;
67constexpr u32 PC_REGISTER = 32; 67constexpr u32 PC_REGISTER = 32;
68constexpr u32 CPSR_REGISTER = 33; 68constexpr u32 PSTATE_REGISTER = 33;
69constexpr u32 UC_ARM64_REG_Q0 = 34; 69constexpr u32 UC_ARM64_REG_Q0 = 34;
70constexpr u32 FPSCR_REGISTER = 66; 70constexpr u32 FPCR_REGISTER = 66;
71 71
72// TODO/WiP - Used while working on support for FPU 72// TODO/WiP - Used while working on support for FPU
73constexpr u32 TODO_DUMMY_REG_997 = 997; 73constexpr u32 TODO_DUMMY_REG_997 = 997;
@@ -116,7 +116,7 @@ constexpr char target_xml[] =
116 116
117 <reg name="pc" bitsize="64" type="code_ptr"/> 117 <reg name="pc" bitsize="64" type="code_ptr"/>
118 118
119 <flags id="cpsr_flags" size="4"> 119 <flags id="pstate_flags" size="4">
120 <field name="SP" start="0" end="0"/> 120 <field name="SP" start="0" end="0"/>
121 <field name="" start="1" end="1"/> 121 <field name="" start="1" end="1"/>
122 <field name="EL" start="2" end="3"/> 122 <field name="EL" start="2" end="3"/>
@@ -135,7 +135,7 @@ constexpr char target_xml[] =
135 <field name="Z" start="30" end="30"/> 135 <field name="Z" start="30" end="30"/>
136 <field name="N" start="31" end="31"/> 136 <field name="N" start="31" end="31"/>
137 </flags> 137 </flags>
138 <reg name="cpsr" bitsize="32" type="cpsr_flags"/> 138 <reg name="pstate" bitsize="32" type="pstate_flags"/>
139 </feature> 139 </feature>
140 <feature name="org.gnu.gdb.aarch64.fpu"> 140 <feature name="org.gnu.gdb.aarch64.fpu">
141 </feature> 141 </feature>
@@ -227,10 +227,10 @@ static u64 RegRead(std::size_t id, Kernel::Thread* thread = nullptr) {
227 return thread->context.sp; 227 return thread->context.sp;
228 } else if (id == PC_REGISTER) { 228 } else if (id == PC_REGISTER) {
229 return thread->context.pc; 229 return thread->context.pc;
230 } else if (id == CPSR_REGISTER) { 230 } else if (id == PSTATE_REGISTER) {
231 return thread->context.cpsr; 231 return thread->context.pstate;
232 } else if (id > CPSR_REGISTER && id < FPSCR_REGISTER) { 232 } else if (id > PSTATE_REGISTER && id < FPCR_REGISTER) {
233 return thread->context.fpu_registers[id - UC_ARM64_REG_Q0][0]; 233 return thread->context.vector_registers[id - UC_ARM64_REG_Q0][0];
234 } else { 234 } else {
235 return 0; 235 return 0;
236 } 236 }
@@ -247,10 +247,10 @@ static void RegWrite(std::size_t id, u64 val, Kernel::Thread* thread = nullptr)
247 thread->context.sp = val; 247 thread->context.sp = val;
248 } else if (id == PC_REGISTER) { 248 } else if (id == PC_REGISTER) {
249 thread->context.pc = val; 249 thread->context.pc = val;
250 } else if (id == CPSR_REGISTER) { 250 } else if (id == PSTATE_REGISTER) {
251 thread->context.cpsr = val; 251 thread->context.pstate = val;
252 } else if (id > CPSR_REGISTER && id < FPSCR_REGISTER) { 252 } else if (id > PSTATE_REGISTER && id < FPCR_REGISTER) {
253 thread->context.fpu_registers[id - (CPSR_REGISTER + 1)][0] = val; 253 thread->context.vector_registers[id - (PSTATE_REGISTER + 1)][0] = val;
254 } 254 }
255} 255}
256 256
@@ -781,11 +781,11 @@ static void ReadRegister() {
781 LongToGdbHex(reply, RegRead(id, current_thread)); 781 LongToGdbHex(reply, RegRead(id, current_thread));
782 } else if (id == PC_REGISTER) { 782 } else if (id == PC_REGISTER) {
783 LongToGdbHex(reply, RegRead(id, current_thread)); 783 LongToGdbHex(reply, RegRead(id, current_thread));
784 } else if (id == CPSR_REGISTER) { 784 } else if (id == PSTATE_REGISTER) {
785 IntToGdbHex(reply, (u32)RegRead(id, current_thread)); 785 IntToGdbHex(reply, static_cast<u32>(RegRead(id, current_thread)));
786 } else if (id >= UC_ARM64_REG_Q0 && id < FPSCR_REGISTER) { 786 } else if (id >= UC_ARM64_REG_Q0 && id < FPCR_REGISTER) {
787 LongToGdbHex(reply, RegRead(id, current_thread)); 787 LongToGdbHex(reply, RegRead(id, current_thread));
788 } else if (id == FPSCR_REGISTER) { 788 } else if (id == FPCR_REGISTER) {
789 LongToGdbHex(reply, RegRead(TODO_DUMMY_REG_998, current_thread)); 789 LongToGdbHex(reply, RegRead(TODO_DUMMY_REG_998, current_thread));
790 } else { 790 } else {
791 LongToGdbHex(reply, RegRead(TODO_DUMMY_REG_997, current_thread)); 791 LongToGdbHex(reply, RegRead(TODO_DUMMY_REG_997, current_thread));
@@ -811,7 +811,7 @@ static void ReadRegisters() {
811 811
812 bufptr += 16; 812 bufptr += 16;
813 813
814 IntToGdbHex(bufptr, (u32)RegRead(CPSR_REGISTER, current_thread)); 814 IntToGdbHex(bufptr, static_cast<u32>(RegRead(PSTATE_REGISTER, current_thread)));
815 815
816 bufptr += 8; 816 bufptr += 8;
817 817
@@ -843,11 +843,11 @@ static void WriteRegister() {
843 RegWrite(id, GdbHexToLong(buffer_ptr), current_thread); 843 RegWrite(id, GdbHexToLong(buffer_ptr), current_thread);
844 } else if (id == PC_REGISTER) { 844 } else if (id == PC_REGISTER) {
845 RegWrite(id, GdbHexToLong(buffer_ptr), current_thread); 845 RegWrite(id, GdbHexToLong(buffer_ptr), current_thread);
846 } else if (id == CPSR_REGISTER) { 846 } else if (id == PSTATE_REGISTER) {
847 RegWrite(id, GdbHexToInt(buffer_ptr), current_thread); 847 RegWrite(id, GdbHexToInt(buffer_ptr), current_thread);
848 } else if (id >= UC_ARM64_REG_Q0 && id < FPSCR_REGISTER) { 848 } else if (id >= UC_ARM64_REG_Q0 && id < FPCR_REGISTER) {
849 RegWrite(id, GdbHexToLong(buffer_ptr), current_thread); 849 RegWrite(id, GdbHexToLong(buffer_ptr), current_thread);
850 } else if (id == FPSCR_REGISTER) { 850 } else if (id == FPCR_REGISTER) {
851 RegWrite(TODO_DUMMY_REG_998, GdbHexToLong(buffer_ptr), current_thread); 851 RegWrite(TODO_DUMMY_REG_998, GdbHexToLong(buffer_ptr), current_thread);
852 } else { 852 } else {
853 RegWrite(TODO_DUMMY_REG_997, GdbHexToLong(buffer_ptr), current_thread); 853 RegWrite(TODO_DUMMY_REG_997, GdbHexToLong(buffer_ptr), current_thread);
@@ -866,16 +866,16 @@ static void WriteRegisters() {
866 if (command_buffer[0] != 'G') 866 if (command_buffer[0] != 'G')
867 return SendReply("E01"); 867 return SendReply("E01");
868 868
869 for (u32 i = 0, reg = 0; reg <= FPSCR_REGISTER; i++, reg++) { 869 for (u32 i = 0, reg = 0; reg <= FPCR_REGISTER; i++, reg++) {
870 if (reg <= SP_REGISTER) { 870 if (reg <= SP_REGISTER) {
871 RegWrite(reg, GdbHexToLong(buffer_ptr + i * 16), current_thread); 871 RegWrite(reg, GdbHexToLong(buffer_ptr + i * 16), current_thread);
872 } else if (reg == PC_REGISTER) { 872 } else if (reg == PC_REGISTER) {
873 RegWrite(PC_REGISTER, GdbHexToLong(buffer_ptr + i * 16), current_thread); 873 RegWrite(PC_REGISTER, GdbHexToLong(buffer_ptr + i * 16), current_thread);
874 } else if (reg == CPSR_REGISTER) { 874 } else if (reg == PSTATE_REGISTER) {
875 RegWrite(CPSR_REGISTER, GdbHexToInt(buffer_ptr + i * 16), current_thread); 875 RegWrite(PSTATE_REGISTER, GdbHexToInt(buffer_ptr + i * 16), current_thread);
876 } else if (reg >= UC_ARM64_REG_Q0 && reg < FPSCR_REGISTER) { 876 } else if (reg >= UC_ARM64_REG_Q0 && reg < FPCR_REGISTER) {
877 RegWrite(reg, GdbHexToLong(buffer_ptr + i * 16), current_thread); 877 RegWrite(reg, GdbHexToLong(buffer_ptr + i * 16), current_thread);
878 } else if (reg == FPSCR_REGISTER) { 878 } else if (reg == FPCR_REGISTER) {
879 RegWrite(TODO_DUMMY_REG_998, GdbHexToLong(buffer_ptr + i * 16), current_thread); 879 RegWrite(TODO_DUMMY_REG_998, GdbHexToLong(buffer_ptr + i * 16), current_thread);
880 } else { 880 } else {
881 UNIMPLEMENTED(); 881 UNIMPLEMENTED();