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authorGravatar MerryMage2018-07-24 11:03:24 +0100
committerGravatar MerryMage2018-07-24 11:03:24 +0100
commit44646e2ea0b87dffd9a1d175c53e3cea67bce344 (patch)
treefd2dcd57424487cf054d98a018ae9d5c62cfd60a /src/core/core_timing.h
parentCMakeLists: Sort filenames (diff)
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core_timing: Split off utility functions into core_timing_util
Diffstat (limited to 'src/core/core_timing.h')
-rw-r--r--src/core/core_timing.h53
1 files changed, 0 insertions, 53 deletions
diff --git a/src/core/core_timing.h b/src/core/core_timing.h
index dc31124a8..7fe6380ad 100644
--- a/src/core/core_timing.h
+++ b/src/core/core_timing.h
@@ -23,59 +23,6 @@
23 23
24namespace CoreTiming { 24namespace CoreTiming {
25 25
26// The below clock rate is based on Switch's clockspeed being widely known as 1.020GHz
27// The exact value used is of course unverified.
28constexpr u64 BASE_CLOCK_RATE = 1019215872; // Switch clock speed is 1020MHz un/docked
29
30inline s64 msToCycles(int ms) {
31 // since ms is int there is no way to overflow
32 return BASE_CLOCK_RATE * static_cast<s64>(ms) / 1000;
33}
34
35inline s64 msToCycles(float ms) {
36 return static_cast<s64>(BASE_CLOCK_RATE * (0.001f) * ms);
37}
38
39inline s64 msToCycles(double ms) {
40 return static_cast<s64>(BASE_CLOCK_RATE * (0.001) * ms);
41}
42
43inline s64 usToCycles(float us) {
44 return static_cast<s64>(BASE_CLOCK_RATE * (0.000001f) * us);
45}
46
47inline s64 usToCycles(int us) {
48 return (BASE_CLOCK_RATE * static_cast<s64>(us) / 1000000);
49}
50
51s64 usToCycles(s64 us);
52
53s64 usToCycles(u64 us);
54
55inline s64 nsToCycles(float ns) {
56 return static_cast<s64>(BASE_CLOCK_RATE * (0.000000001f) * ns);
57}
58
59inline s64 nsToCycles(int ns) {
60 return BASE_CLOCK_RATE * static_cast<s64>(ns) / 1000000000;
61}
62
63s64 nsToCycles(s64 ns);
64
65s64 nsToCycles(u64 ns);
66
67inline u64 cyclesToNs(s64 cycles) {
68 return cycles * 1000000000 / BASE_CLOCK_RATE;
69}
70
71inline s64 cyclesToUs(s64 cycles) {
72 return cycles * 1000000 / BASE_CLOCK_RATE;
73}
74
75inline u64 cyclesToMs(s64 cycles) {
76 return cycles * 1000 / BASE_CLOCK_RATE;
77}
78
79/** 26/**
80 * CoreTiming begins at the boundary of timing slice -1. An initial call to Advance() is 27 * CoreTiming begins at the boundary of timing slice -1. An initial call to Advance() is
81 * required to end slice -1 and start slice 0 before the first cycle of code is executed. 28 * required to end slice -1 and start slice 0 before the first cycle of code is executed.