arm_interface: Remove ARM11-isms from the CPU interface

This modifies the CPU interface to more accurately match an
AArch64-supporting CPU as opposed to an ARM11 one. Two of the methods
don't even make sense to keep around for this interface, as Adv Simd is
used, rather than the VFP in the primary execution state. This is
essentially a modernization change that should have occurred from the
get-go.

5 files changed, 59 insertions, 72 deletions

diff --git a/src/core/arm/arm_interface.h b/src/core/arm/arm_interface.h
index 0b2af2a9b..867e34932 100644
--- a/src/core/arm/arm_interface.h
+++ b/src/core/arm/arm_interface.h
@@ -10,7 +10,7 @@
 
 namespace Core {
 
-/// Generic ARM11 CPU interface
+/// Generic ARMv8 CPU interface
 class ARM_Interface : NonCopyable {
 public:
     virtual ~ARM_Interface() {}
@@ -19,9 +19,9 @@ public:
         std::array<u64, 31> cpu_registers;
         u64 sp;
         u64 pc;
-        u64 cpsr;
-        std::array<u128, 32> fpu_registers;
-        u64 fpscr;
+        u64 pstate;
+        std::array<u128, 32> vector_registers;
+        u64 fpcr;
     };
 
     /// Runs the CPU until an event happens
@@ -69,42 +69,50 @@ public:
      */
     virtual void SetReg(int index, u64 value) = 0;
 
-    virtual u128 GetExtReg(int index) const = 0;
-
-    virtual void SetExtReg(int index, u128 value) = 0;
-
     /**
-     * Gets the value of a VFP register
-     * @param index Register index (0-31)
-     * @return Returns the value in the register
+     * Gets the value of a specified vector register.
+     *
+     * @param index The index of the vector register.
+     * @return the value within the vector register.
      */
-    virtual u32 GetVFPReg(int index) const = 0;
+    virtual u128 GetVectorReg(int index) const = 0;
 
     /**
-     * Sets a VFP register to the given value
-     * @param index Register index (0-31)
-     * @param value Value to set register to
+     * Sets a given value into a vector register.
+     *
+     * @param index The index of the vector register.
+     * @param value The new value to place in the register.
      */
-    virtual void SetVFPReg(int index, u32 value) = 0;
+    virtual void SetVectorReg(int index, u128 value) = 0;
 
     /**
-     * Get the current CPSR register
-     * @return Returns the value of the CPSR register
+     * Get the current PSTATE register
+     * @return Returns the value of the PSTATE register
      */
-    virtual u32 GetCPSR() const = 0;
+    virtual u32 GetPSTATE() const = 0;
 
     /**
-     * Set the current CPSR register
-     * @param cpsr Value to set CPSR to
+     * Set the current PSTATE register
+     * @param pstate Value to set PSTATE to
      */
-    virtual void SetCPSR(u32 cpsr) = 0;
+    virtual void SetPSTATE(u32 pstate) = 0;
 
     virtual VAddr GetTlsAddress() const = 0;
 
     virtual void SetTlsAddress(VAddr address) = 0;
 
+    /**
+     * Gets the value within the TPIDR_EL0 (read/write software thread ID) register.
+     *
+     * @return the value within the register.
+     */
     virtual u64 GetTPIDR_EL0() const = 0;
 
+    /**
+     * Sets a new value within the TPIDR_EL0 (read/write software thread ID) register.
+     *
+     * @param value The new value to place in the register.
+     */
     virtual void SetTPIDR_EL0(u64 value) = 0;
 
     /**
@@ -119,6 +127,7 @@ public:
      */
     virtual void LoadContext(const ThreadContext& ctx) = 0;
 
+    /// Clears the exclusive monitor's state.
     virtual void ClearExclusiveState() = 0;
 
     /// Prepare core for thread reschedule (if needed to correctly handle state)
diff --git a/src/core/arm/dynarmic/arm_dynarmic.cpp b/src/core/arm/dynarmic/arm_dynarmic.cpp
index 0c175d872..725759554 100644
--- a/src/core/arm/dynarmic/arm_dynarmic.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic.cpp
@@ -194,29 +194,20 @@ void ARM_Dynarmic::SetReg(int index, u64 value) {
     jit->SetRegister(index, value);
 }
 
-u128 ARM_Dynarmic::GetExtReg(int index) const {
+u128 ARM_Dynarmic::GetVectorReg(int index) const {
     return jit->GetVector(index);
 }
 
-void ARM_Dynarmic::SetExtReg(int index, u128 value) {
+void ARM_Dynarmic::SetVectorReg(int index, u128 value) {
     jit->SetVector(index, value);
 }
 
-u32 ARM_Dynarmic::GetVFPReg(int /*index*/) const {
-    UNIMPLEMENTED();
-    return {};
-}
-
-void ARM_Dynarmic::SetVFPReg(int /*index*/, u32 /*value*/) {
-    UNIMPLEMENTED();
-}
-
-u32 ARM_Dynarmic::GetCPSR() const {
+u32 ARM_Dynarmic::GetPSTATE() const {
     return jit->GetPstate();
 }
 
-void ARM_Dynarmic::SetCPSR(u32 cpsr) {
-    jit->SetPstate(cpsr);
+void ARM_Dynarmic::SetPSTATE(u32 pstate) {
+    jit->SetPstate(pstate);
 }
 
 u64 ARM_Dynarmic::GetTlsAddress() const {
@@ -239,18 +230,18 @@ void ARM_Dynarmic::SaveContext(ThreadContext& ctx) {
     ctx.cpu_registers = jit->GetRegisters();
     ctx.sp = jit->GetSP();
     ctx.pc = jit->GetPC();
-    ctx.cpsr = jit->GetPstate();
-    ctx.fpu_registers = jit->GetVectors();
-    ctx.fpscr = jit->GetFpcr();
+    ctx.pstate = jit->GetPstate();
+    ctx.vector_registers = jit->GetVectors();
+    ctx.fpcr = jit->GetFpcr();
 }
 
 void ARM_Dynarmic::LoadContext(const ThreadContext& ctx) {
     jit->SetRegisters(ctx.cpu_registers);
     jit->SetSP(ctx.sp);
     jit->SetPC(ctx.pc);
-    jit->SetPstate(static_cast<u32>(ctx.cpsr));
-    jit->SetVectors(ctx.fpu_registers);
-    jit->SetFpcr(static_cast<u32>(ctx.fpscr));
+    jit->SetPstate(static_cast<u32>(ctx.pstate));
+    jit->SetVectors(ctx.vector_registers);
+    jit->SetFpcr(static_cast<u32>(ctx.fpcr));
 }
 
 void ARM_Dynarmic::PrepareReschedule() {
diff --git a/src/core/arm/dynarmic/arm_dynarmic.h b/src/core/arm/dynarmic/arm_dynarmic.h
index 56c60c853..e61382d3d 100644
--- a/src/core/arm/dynarmic/arm_dynarmic.h
+++ b/src/core/arm/dynarmic/arm_dynarmic.h
@@ -29,14 +29,12 @@ public:
     u64 GetPC() const override;
     u64 GetReg(int index) const override;
     void SetReg(int index, u64 value) override;
-    u128 GetExtReg(int index) const override;
-    void SetExtReg(int index, u128 value) override;
-    u32 GetVFPReg(int index) const override;
-    void SetVFPReg(int index, u32 value) override;
-    u32 GetCPSR() const override;
+    u128 GetVectorReg(int index) const override;
+    void SetVectorReg(int index, u128 value) override;
+    u32 GetPSTATE() const override;
+    void SetPSTATE(u32 pstate) override;
     void Run() override;
     void Step() override;
-    void SetCPSR(u32 cpsr) override;
     VAddr GetTlsAddress() const override;
     void SetTlsAddress(VAddr address) override;
     void SetTPIDR_EL0(u64 value) override;
diff --git a/src/core/arm/unicorn/arm_unicorn.cpp b/src/core/arm/unicorn/arm_unicorn.cpp
index 4e02b7cd4..e218a0b15 100644
--- a/src/core/arm/unicorn/arm_unicorn.cpp
+++ b/src/core/arm/unicorn/arm_unicorn.cpp
@@ -131,33 +131,24 @@ void ARM_Unicorn::SetReg(int regn, u64 val) {
     CHECKED(uc_reg_write(uc, treg, &val));
 }
 
-u128 ARM_Unicorn::GetExtReg(int /*index*/) const {
+u128 ARM_Unicorn::GetVectorReg(int /*index*/) const {
     UNIMPLEMENTED();
     static constexpr u128 res{};
     return res;
 }
 
-void ARM_Unicorn::SetExtReg(int /*index*/, u128 /*value*/) {
+void ARM_Unicorn::SetVectorReg(int /*index*/, u128 /*value*/) {
     UNIMPLEMENTED();
 }
 
-u32 ARM_Unicorn::GetVFPReg(int /*index*/) const {
-    UNIMPLEMENTED();
-    return {};
-}
-
-void ARM_Unicorn::SetVFPReg(int /*index*/, u32 /*value*/) {
-    UNIMPLEMENTED();
-}
-
-u32 ARM_Unicorn::GetCPSR() const {
+u32 ARM_Unicorn::GetPSTATE() const {
     u64 nzcv{};
     CHECKED(uc_reg_read(uc, UC_ARM64_REG_NZCV, &nzcv));
     return static_cast<u32>(nzcv);
 }
 
-void ARM_Unicorn::SetCPSR(u32 cpsr) {
-    u64 nzcv = cpsr;
+void ARM_Unicorn::SetPSTATE(u32 pstate) {
+    u64 nzcv = pstate;
     CHECKED(uc_reg_write(uc, UC_ARM64_REG_NZCV, &nzcv));
 }
 
@@ -219,7 +210,7 @@ void ARM_Unicorn::SaveContext(ThreadContext& ctx) {
 
     CHECKED(uc_reg_read(uc, UC_ARM64_REG_SP, &ctx.sp));
     CHECKED(uc_reg_read(uc, UC_ARM64_REG_PC, &ctx.pc));
-    CHECKED(uc_reg_read(uc, UC_ARM64_REG_NZCV, &ctx.cpsr));
+    CHECKED(uc_reg_read(uc, UC_ARM64_REG_NZCV, &ctx.pstate));
 
     for (auto i = 0; i < 29; ++i) {
         uregs[i] = UC_ARM64_REG_X0 + i;
@@ -234,7 +225,7 @@ void ARM_Unicorn::SaveContext(ThreadContext& ctx) {
 
     for (int i = 0; i < 32; ++i) {
         uregs[i] = UC_ARM64_REG_Q0 + i;
-        tregs[i] = &ctx.fpu_registers[i];
+        tregs[i] = &ctx.vector_registers[i];
     }
 
     CHECKED(uc_reg_read_batch(uc, uregs, tregs, 32));
@@ -246,7 +237,7 @@ void ARM_Unicorn::LoadContext(const ThreadContext& ctx) {
 
     CHECKED(uc_reg_write(uc, UC_ARM64_REG_SP, &ctx.sp));
     CHECKED(uc_reg_write(uc, UC_ARM64_REG_PC, &ctx.pc));
-    CHECKED(uc_reg_write(uc, UC_ARM64_REG_NZCV, &ctx.cpsr));
+    CHECKED(uc_reg_write(uc, UC_ARM64_REG_NZCV, &ctx.pstate));
 
     for (int i = 0; i < 29; ++i) {
         uregs[i] = UC_ARM64_REG_X0 + i;
@@ -261,7 +252,7 @@ void ARM_Unicorn::LoadContext(const ThreadContext& ctx) {
 
     for (auto i = 0; i < 32; ++i) {
         uregs[i] = UC_ARM64_REG_Q0 + i;
-        tregs[i] = (void*)&ctx.fpu_registers[i];
+        tregs[i] = (void*)&ctx.vector_registers[i];
     }
 
     CHECKED(uc_reg_write_batch(uc, uregs, tregs, 32));
diff --git a/src/core/arm/unicorn/arm_unicorn.h b/src/core/arm/unicorn/arm_unicorn.h
index d6f7cf4ab..75761950b 100644
--- a/src/core/arm/unicorn/arm_unicorn.h
+++ b/src/core/arm/unicorn/arm_unicorn.h
@@ -22,12 +22,10 @@ public:
     u64 GetPC() const override;
     u64 GetReg(int index) const override;
     void SetReg(int index, u64 value) override;
-    u128 GetExtReg(int index) const override;
-    void SetExtReg(int index, u128 value) override;
-    u32 GetVFPReg(int index) const override;
-    void SetVFPReg(int index, u32 value) override;
-    u32 GetCPSR() const override;
-    void SetCPSR(u32 cpsr) override;
+    u128 GetVectorReg(int index) const override;
+    void SetVectorReg(int index, u128 value) override;
+    u32 GetPSTATE() const override;
+    void SetPSTATE(u32 pstate) override;
     VAddr GetTlsAddress() const override;
     void SetTlsAddress(VAddr address) override;
     void SetTPIDR_EL0(u64 value) override;