diff options
| author | 2018-01-03 22:10:11 -0500 | |
|---|---|---|
| committer | 2018-01-03 22:10:11 -0500 | |
| commit | aa7e061e7173dbbafb93d7536667815dee221a02 (patch) | |
| tree | d0659b3c083dbcdcdff24ab8d15de2d173d25d67 /src/core/arm | |
| parent | externals: Point dynarmic at a real commit. (diff) | |
| download | yuzu-aa7e061e7173dbbafb93d7536667815dee221a02.tar.gz yuzu-aa7e061e7173dbbafb93d7536667815dee221a02.tar.xz yuzu-aa7e061e7173dbbafb93d7536667815dee221a02.zip | |
arm_dynarmic: Gut interface until dynarmic is ready for general use.
Diffstat (limited to 'src/core/arm')
| -rw-r--r-- | src/core/arm/dynarmic/arm_dynarmic.cpp | 175 | ||||
| -rw-r--r-- | src/core/arm/dynarmic/arm_dynarmic.h | 11 |
2 files changed, 44 insertions, 142 deletions
diff --git a/src/core/arm/dynarmic/arm_dynarmic.cpp b/src/core/arm/dynarmic/arm_dynarmic.cpp index 89754da17..12b7fc926 100644 --- a/src/core/arm/dynarmic/arm_dynarmic.cpp +++ b/src/core/arm/dynarmic/arm_dynarmic.cpp | |||
| @@ -1,186 +1,93 @@ | |||
| 1 | // Copyright 2016 Citra Emulator Project | 1 | // Copyright 2018 Yuzu Emulator Team |
| 2 | // Licensed under GPLv2 or any later version | 2 | // Licensed under GPLv2 or any later version |
| 3 | // Refer to the license.txt file included. | 3 | // Refer to the license.txt file included. |
| 4 | 4 | ||
| 5 | #include <cstring> | ||
| 6 | #include <dynarmic/dynarmic.h> | ||
| 7 | #include "common/assert.h" | ||
| 8 | #include "common/microprofile.h" | ||
| 9 | #include "core/arm/dynarmic/arm_dynarmic.h" | 5 | #include "core/arm/dynarmic/arm_dynarmic.h" |
| 10 | #include "core/core.h" | ||
| 11 | #include "core/core_timing.h" | ||
| 12 | #include "core/hle/kernel/svc.h" | ||
| 13 | #include "core/memory.h" | ||
| 14 | |||
| 15 | static void InterpreterFallback(u64 pc, Dynarmic::Jit* jit, void* user_arg) { | ||
| 16 | UNIMPLEMENTED_MSG("InterpreterFallback for ARM64 JIT does not exist!"); | ||
| 17 | } | ||
| 18 | |||
| 19 | static bool IsReadOnlyMemory(u64 vaddr) { | ||
| 20 | // TODO(bunnei): ImplementMe | ||
| 21 | return false; | ||
| 22 | } | ||
| 23 | |||
| 24 | u8 MemoryRead8(const u64 addr) { | ||
| 25 | return Memory::Read8(static_cast<VAddr>(addr)); | ||
| 26 | } | ||
| 27 | |||
| 28 | u16 MemoryRead16(const u64 addr) { | ||
| 29 | return Memory::Read16(static_cast<VAddr>(addr)); | ||
| 30 | } | ||
| 31 | |||
| 32 | u32 MemoryRead32(const u64 addr) { | ||
| 33 | return Memory::Read32(static_cast<VAddr>(addr)); | ||
| 34 | } | ||
| 35 | |||
| 36 | u64 MemoryRead64(const u64 addr) { | ||
| 37 | return Memory::Read64(static_cast<VAddr>(addr)); | ||
| 38 | } | ||
| 39 | |||
| 40 | void MemoryWrite8(const u64 addr, const u8 data) { | ||
| 41 | Memory::Write8(static_cast<VAddr>(addr), data); | ||
| 42 | } | ||
| 43 | |||
| 44 | void MemoryWrite16(const u64 addr, const u16 data) { | ||
| 45 | Memory::Write16(static_cast<VAddr>(addr), data); | ||
| 46 | } | ||
| 47 | |||
| 48 | void MemoryWrite32(const u64 addr, const u32 data) { | ||
| 49 | Memory::Write32(static_cast<VAddr>(addr), data); | ||
| 50 | } | ||
| 51 | |||
| 52 | void MemoryWrite64(const u64 addr, const u64 data) { | ||
| 53 | Memory::Write64(static_cast<VAddr>(addr), data); | ||
| 54 | } | ||
| 55 | |||
| 56 | static Dynarmic::UserCallbacks GetUserCallbacks(ARM_Interface* interpreter_fallback) { | ||
| 57 | Dynarmic::UserCallbacks user_callbacks{}; | ||
| 58 | user_callbacks.InterpreterFallback = &InterpreterFallback; | ||
| 59 | user_callbacks.user_arg = static_cast<void*>(interpreter_fallback); | ||
| 60 | user_callbacks.CallSVC = &Kernel::CallSVC; | ||
| 61 | user_callbacks.memory.IsReadOnlyMemory = &IsReadOnlyMemory; | ||
| 62 | user_callbacks.memory.ReadCode = &MemoryRead32; | ||
| 63 | user_callbacks.memory.Read8 = &MemoryRead8; | ||
| 64 | user_callbacks.memory.Read16 = &MemoryRead16; | ||
| 65 | user_callbacks.memory.Read32 = &MemoryRead32; | ||
| 66 | user_callbacks.memory.Read64 = &MemoryRead64; | ||
| 67 | user_callbacks.memory.Write8 = &MemoryWrite8; | ||
| 68 | user_callbacks.memory.Write16 = &MemoryWrite16; | ||
| 69 | user_callbacks.memory.Write32 = &MemoryWrite32; | ||
| 70 | user_callbacks.memory.Write64 = &MemoryWrite64; | ||
| 71 | //user_callbacks.page_table = Memory::GetCurrentPageTablePointers(); | ||
| 72 | return user_callbacks; | ||
| 73 | } | ||
| 74 | 6 | ||
| 75 | ARM_Dynarmic::ARM_Dynarmic() { | 7 | ARM_Dynarmic::ARM_Dynarmic() { |
| 8 | UNIMPLEMENTED(); | ||
| 76 | } | 9 | } |
| 77 | 10 | ||
| 78 | void ARM_Dynarmic::MapBackingMemory(VAddr address, size_t size, u8* memory, Kernel::VMAPermission perms) { | 11 | void ARM_Dynarmic::MapBackingMemory(VAddr /*address*/, size_t /*size*/, u8* /*memory*/, |
| 12 | Kernel::VMAPermission /*perms*/) { | ||
| 13 | UNIMPLEMENTED(); | ||
| 79 | } | 14 | } |
| 80 | 15 | ||
| 81 | void ARM_Dynarmic::SetPC(u64 pc) { | 16 | void ARM_Dynarmic::SetPC(u64 /*pc*/) { |
| 82 | jit->Regs64()[32] = pc; | 17 | UNIMPLEMENTED(); |
| 83 | } | 18 | } |
| 84 | 19 | ||
| 85 | u64 ARM_Dynarmic::GetPC() const { | 20 | u64 ARM_Dynarmic::GetPC() const { |
| 86 | return jit->Regs64()[32]; | 21 | UNIMPLEMENTED(); |
| 22 | return {}; | ||
| 87 | } | 23 | } |
| 88 | 24 | ||
| 89 | u64 ARM_Dynarmic::GetReg(int index) const { | 25 | u64 ARM_Dynarmic::GetReg(int /*index*/) const { |
| 90 | return jit->Regs64()[index]; | 26 | UNIMPLEMENTED(); |
| 27 | return {}; | ||
| 91 | } | 28 | } |
| 92 | 29 | ||
| 93 | void ARM_Dynarmic::SetReg(int index, u64 value) { | 30 | void ARM_Dynarmic::SetReg(int /*index*/, u64 /*value*/) { |
| 94 | jit->Regs64()[index] = value; | 31 | UNIMPLEMENTED(); |
| 95 | } | 32 | } |
| 96 | 33 | ||
| 97 | const u128& ARM_Dynarmic::GetExtReg(int index) const { | 34 | const u128& ARM_Dynarmic::GetExtReg(int /*index*/) const { |
| 98 | return jit->ExtRegs64()[index]; | 35 | UNIMPLEMENTED(); |
| 36 | static constexpr u128 res{}; | ||
| 37 | return res; | ||
| 99 | } | 38 | } |
| 100 | 39 | ||
| 101 | void ARM_Dynarmic::SetExtReg(int index, u128& value) { | 40 | void ARM_Dynarmic::SetExtReg(int /*index*/, u128& /*value*/) { |
| 102 | jit->ExtRegs64()[index] = value; | 41 | UNIMPLEMENTED(); |
| 103 | } | 42 | } |
| 104 | 43 | ||
| 105 | u32 ARM_Dynarmic::GetVFPReg(int index) const { | 44 | u32 ARM_Dynarmic::GetVFPReg(int /*index*/) const { |
| 45 | UNIMPLEMENTED(); | ||
| 106 | return {}; | 46 | return {}; |
| 107 | } | 47 | } |
| 108 | 48 | ||
| 109 | void ARM_Dynarmic::SetVFPReg(int index, u32 value) { | 49 | void ARM_Dynarmic::SetVFPReg(int /*index*/, u32 /*value*/) { |
| 50 | UNIMPLEMENTED(); | ||
| 110 | } | 51 | } |
| 111 | 52 | ||
| 112 | u32 ARM_Dynarmic::GetCPSR() const { | 53 | u32 ARM_Dynarmic::GetCPSR() const { |
| 113 | return jit->Cpsr(); | 54 | UNIMPLEMENTED(); |
| 55 | return {}; | ||
| 114 | } | 56 | } |
| 115 | 57 | ||
| 116 | void ARM_Dynarmic::SetCPSR(u32 cpsr) { | 58 | void ARM_Dynarmic::SetCPSR(u32 /*cpsr*/) { |
| 117 | jit->Cpsr() = cpsr; | 59 | UNIMPLEMENTED(); |
| 118 | } | 60 | } |
| 119 | 61 | ||
| 120 | VAddr ARM_Dynarmic::GetTlsAddress() const { | 62 | VAddr ARM_Dynarmic::GetTlsAddress() const { |
| 121 | return jit->TlsAddr(); | 63 | UNIMPLEMENTED(); |
| 64 | return {}; | ||
| 122 | } | 65 | } |
| 123 | 66 | ||
| 124 | void ARM_Dynarmic::SetTlsAddress(VAddr address) { | 67 | void ARM_Dynarmic::SetTlsAddress(VAddr /*address*/) { |
| 125 | jit->TlsAddr() = address; | 68 | UNIMPLEMENTED(); |
| 126 | } | 69 | } |
| 127 | 70 | ||
| 128 | MICROPROFILE_DEFINE(ARM_Jit, "ARM JIT", "ARM JIT", MP_RGB(255, 64, 64)); | 71 | void ARM_Dynarmic::ExecuteInstructions(int /*num_instructions*/) { |
| 129 | 72 | UNIMPLEMENTED(); | |
| 130 | void ARM_Dynarmic::ExecuteInstructions(int num_instructions) { | ||
| 131 | ASSERT(Memory::GetCurrentPageTable() == current_page_table); | ||
| 132 | MICROPROFILE_SCOPE(ARM_Jit); | ||
| 133 | |||
| 134 | std::size_t ticks_executed = jit->Run(static_cast<unsigned>(num_instructions)); | ||
| 135 | |||
| 136 | CoreTiming::AddTicks(ticks_executed); | ||
| 137 | } | 73 | } |
| 138 | 74 | ||
| 139 | void ARM_Dynarmic::SaveContext(ARM_Interface::ThreadContext& ctx) { | 75 | void ARM_Dynarmic::SaveContext(ARM_Interface::ThreadContext& /*ctx*/) { |
| 140 | memcpy(ctx.cpu_registers, jit->Regs64().data(), sizeof(ctx.cpu_registers)); | 76 | UNIMPLEMENTED(); |
| 141 | memcpy(ctx.fpu_registers, jit->ExtRegs64().data(), sizeof(ctx.fpu_registers)); | ||
| 142 | |||
| 143 | ctx.lr = jit->Regs64()[30]; | ||
| 144 | ctx.sp = jit->Regs64()[31]; | ||
| 145 | ctx.pc = jit->Regs64()[32]; | ||
| 146 | ctx.cpsr = jit->Cpsr(); | ||
| 147 | |||
| 148 | // TODO(bunnei): Fix once we have proper support for tpidrro_el0, etc. in the JIT | ||
| 149 | ctx.tls_address = jit->TlsAddr(); | ||
| 150 | } | 77 | } |
| 151 | 78 | ||
| 152 | void ARM_Dynarmic::LoadContext(const ARM_Interface::ThreadContext& ctx) { | 79 | void ARM_Dynarmic::LoadContext(const ARM_Interface::ThreadContext& /*ctx*/) { |
| 153 | memcpy(jit->Regs64().data(), ctx.cpu_registers, sizeof(ctx.cpu_registers)); | 80 | UNIMPLEMENTED(); |
| 154 | memcpy(jit->ExtRegs64().data(), ctx.fpu_registers, sizeof(ctx.fpu_registers)); | ||
| 155 | |||
| 156 | jit->Regs64()[30] = ctx.lr; | ||
| 157 | jit->Regs64()[31] = ctx.sp; | ||
| 158 | jit->Regs64()[32] = ctx.pc; | ||
| 159 | jit->Cpsr() = ctx.cpsr; | ||
| 160 | |||
| 161 | // TODO(bunnei): Fix once we have proper support for tpidrro_el0, etc. in the JIT | ||
| 162 | jit->TlsAddr() = ctx.tls_address; | ||
| 163 | } | 81 | } |
| 164 | 82 | ||
| 165 | void ARM_Dynarmic::PrepareReschedule() { | 83 | void ARM_Dynarmic::PrepareReschedule() { |
| 166 | if (jit->IsExecuting()) { | 84 | UNIMPLEMENTED(); |
| 167 | jit->HaltExecution(); | ||
| 168 | } | ||
| 169 | } | 85 | } |
| 170 | 86 | ||
| 171 | void ARM_Dynarmic::ClearInstructionCache() { | 87 | void ARM_Dynarmic::ClearInstructionCache() { |
| 172 | jit->ClearCache(); | 88 | UNIMPLEMENTED(); |
| 173 | } | 89 | } |
| 174 | 90 | ||
| 175 | void ARM_Dynarmic::PageTableChanged() { | 91 | void ARM_Dynarmic::PageTableChanged() { |
| 176 | current_page_table = Memory::GetCurrentPageTable(); | 92 | UNIMPLEMENTED(); |
| 177 | |||
| 178 | auto iter = jits.find(current_page_table); | ||
| 179 | if (iter != jits.end()) { | ||
| 180 | jit = iter->second.get(); | ||
| 181 | return; | ||
| 182 | } | ||
| 183 | |||
| 184 | jit = new Dynarmic::Jit(GetUserCallbacks(this), Dynarmic::Arch::ARM64); | ||
| 185 | jits.emplace(current_page_table, std::unique_ptr<Dynarmic::Jit>(jit)); | ||
| 186 | } | 93 | } |
diff --git a/src/core/arm/dynarmic/arm_dynarmic.h b/src/core/arm/dynarmic/arm_dynarmic.h index 5c7f516d8..2d89df965 100644 --- a/src/core/arm/dynarmic/arm_dynarmic.h +++ b/src/core/arm/dynarmic/arm_dynarmic.h | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | // Copyright 2016 Citra Emulator Project | 1 | // Copyright 2018 Yuzu Emulator Team |
| 2 | // Licensed under GPLv2 or any later version | 2 | // Licensed under GPLv2 or any later version |
| 3 | // Refer to the license.txt file included. | 3 | // Refer to the license.txt file included. |
| 4 | 4 | ||
| @@ -6,7 +6,6 @@ | |||
| 6 | 6 | ||
| 7 | #include <map> | 7 | #include <map> |
| 8 | #include <memory> | 8 | #include <memory> |
| 9 | #include <dynarmic/dynarmic.h> | ||
| 10 | #include "common/common_types.h" | 9 | #include "common/common_types.h" |
| 11 | #include "core/arm/arm_interface.h" | 10 | #include "core/arm/arm_interface.h" |
| 12 | 11 | ||
| @@ -18,7 +17,8 @@ class ARM_Dynarmic final : public ARM_Interface { | |||
| 18 | public: | 17 | public: |
| 19 | ARM_Dynarmic(); | 18 | ARM_Dynarmic(); |
| 20 | 19 | ||
| 21 | void MapBackingMemory(VAddr address, size_t size, u8* memory, Kernel::VMAPermission perms) override; | 20 | void MapBackingMemory(VAddr address, size_t size, u8* memory, |
| 21 | Kernel::VMAPermission perms) override; | ||
| 22 | 22 | ||
| 23 | void SetPC(u64 pc) override; | 23 | void SetPC(u64 pc) override; |
| 24 | u64 GetPC() const override; | 24 | u64 GetPC() const override; |
| @@ -41,9 +41,4 @@ public: | |||
| 41 | 41 | ||
| 42 | void ClearInstructionCache() override; | 42 | void ClearInstructionCache() override; |
| 43 | void PageTableChanged() override; | 43 | void PageTableChanged() override; |
| 44 | |||
| 45 | private: | ||
| 46 | Dynarmic::Jit* jit = nullptr; | ||
| 47 | Memory::PageTable* current_page_table = nullptr; | ||
| 48 | std::map<Memory::PageTable*, std::unique_ptr<Dynarmic::Jit>> jits; | ||
| 49 | }; | 44 | }; |