Merge pull request #818 from linkmauve/no-trailing-whitespace

Ban trailing whitespace from the entire project, forever

6 files changed, 24 insertions, 24 deletions

diff --git a/src/core/arm/disassembler/arm_disasm.cpp b/src/core/arm/disassembler/arm_disasm.cpp
index 913dc1454..f6d44d85a 100644
--- a/src/core/arm/disassembler/arm_disasm.cpp
+++ b/src/core/arm/disassembler/arm_disasm.cpp
@@ -813,7 +813,7 @@ Opcode ARM_Disasm::Decode11(uint32_t insn) {
         // SWI
         return OP_SWI;
     }
-  
+
     uint8_t bit4 = (insn >> 4) & 0x1;
     uint8_t cpnum = (insn >> 8) & 0xf;
 
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index b5d1b43cd..b00eb49a9 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -134,7 +134,7 @@ static unsigned int DPO(Immediate)(ARMul_State* cpu, unsigned int sht_oper) {
     unsigned int immed_8 = BITS(sht_oper, 0, 7);
     unsigned int rotate_imm = BITS(sht_oper, 8, 11);
     unsigned int shifter_operand = ROTATE_RIGHT_32(immed_8, rotate_imm * 2);
-    if (rotate_imm == 0) 
+    if (rotate_imm == 0)
         cpu->shifter_carry_out = cpu->CFlag;
     else
         cpu->shifter_carry_out = BIT(shifter_operand, 31);
@@ -521,7 +521,7 @@ static void MLnS(ImmediateOffset)(ARMul_State* cpu, unsigned int inst, unsigned
         addr = CHECK_READ_REG15_WA(cpu, Rn) + offset_8;
     else
         addr = CHECK_READ_REG15_WA(cpu, Rn) - offset_8;
-    
+
     virt_addr = addr;
 }
 
@@ -550,7 +550,7 @@ static void MLnS(ImmediatePreIndexed)(ARMul_State* cpu, unsigned int inst, unsig
 
     if (U_BIT)
         addr = rn + offset_8;
-    else 
+    else
         addr = rn - offset_8;
 
     virt_addr = addr;
@@ -1306,8 +1306,8 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(and)(unsigned int inst, int index)
     inst_cream->Rd = BITS(inst, 12, 15);
     inst_cream->shifter_operand = BITS(inst, 0, 11);
     inst_cream->shtop_func = get_shtop(inst);
-        
-    if (inst_cream->Rd == 15) 
+
+    if (inst_cream->Rd == 15)
         inst_base->br = INDIRECT_BRANCH;
 
     return inst_base;
@@ -1350,7 +1350,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(bic)(unsigned int inst, int index)
     inst_cream->shifter_operand = BITS(inst, 0, 11);
     inst_cream->shtop_func = get_shtop(inst);
 
-    if (inst_cream->Rd == 15) 
+    if (inst_cream->Rd == 15)
         inst_base->br = INDIRECT_BRANCH;
     return inst_base;
 }
@@ -3269,7 +3269,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(yield)(unsigned int inst, int index)
 #define VFP_INTERPRETER_STRUCT
 #include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
 #undef VFP_INTERPRETER_STRUCT
- 
+
 #define VFP_INTERPRETER_TRANS
 #include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
 #undef VFP_INTERPRETER_TRANS
@@ -3478,9 +3478,9 @@ const transop_fp_t arm_instruction_trans[] = {
     INTERPRETER_TRANSLATE(bbl),
 
     // All the thumb instructions should be placed the end of table
-    INTERPRETER_TRANSLATE(b_2_thumb), 
-    INTERPRETER_TRANSLATE(b_cond_thumb), 
-    INTERPRETER_TRANSLATE(bl_1_thumb), 
+    INTERPRETER_TRANSLATE(b_2_thumb),
+    INTERPRETER_TRANSLATE(b_cond_thumb),
+    INTERPRETER_TRANSLATE(bl_1_thumb),
     INTERPRETER_TRANSLATE(bl_2_thumb),
     INTERPRETER_TRANSLATE(blx_1_thumb)
 };
@@ -4338,7 +4338,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                     }
                 }
                 if (BIT(inst, 13)) {
-                    if (cpu->Mode == USER32MODE) 
+                    if (cpu->Mode == USER32MODE)
                         cpu->Reg[13] = ReadMemory32(cpu, addr);
                     else
                         cpu->Reg_usr[0] = ReadMemory32(cpu, addr);
@@ -4346,7 +4346,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                     addr += 4;
                 }
                 if (BIT(inst, 14)) {
-                    if (cpu->Mode == USER32MODE) 
+                    if (cpu->Mode == USER32MODE)
                         cpu->Reg[14] = ReadMemory32(cpu, addr);
                     else
                         cpu->Reg_usr[1] = ReadMemory32(cpu, addr);
@@ -5148,7 +5148,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
     REV16_INST:
     REVSH_INST:
     {
-        
+
         if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
             rev_inst* const inst_cream = (rev_inst*)inst_base->component;
 
@@ -5721,7 +5721,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
 
             if (do_swap)
                 rm_val = (((rm_val & 0xFFFF) << 16) | (rm_val >> 16));
-            
+
             const s32 product1 = (s16)(rn_val & 0xFFFF) * (s16)(rm_val & 0xFFFF);
             const s32 product2 = (s16)((rn_val >> 16) & 0xFFFF) * (s16)((rm_val >> 16) & 0xFFFF);
             s64 result;
@@ -6583,7 +6583,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             {
                 u32 lo_val = 0;
                 u32 hi_val = 0;
-                
+
                 // UHADD16
                 if (op2 == 0x00) {
                     lo_val = (rn_val & 0xFFFF) + (rm_val & 0xFFFF);
@@ -6772,7 +6772,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
 
             u16 lo_val = 0;
             u16 hi_val = 0;
-            
+
             // UQADD16
             if (op2 == 0x00) {
                 lo_val = ARMul_UnsignedSaturatedAdd16(rn_val & 0xFFFF, rm_val & 0xFFFF);
diff --git a/src/core/arm/dyncom/arm_dyncom_thumb.cpp b/src/core/arm/dyncom/arm_dyncom_thumb.cpp
index cdaf21450..2fc8170be 100644
--- a/src/core/arm/dyncom/arm_dyncom_thumb.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_thumb.cpp
@@ -184,7 +184,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
     case 9: // LDR Rd,[PC,#imm8]
         *ainstr = 0xE59F0000                    // base
             | ((tinstr & 0x0700) << (12 - 8))   // Rd
-            |((tinstr & 0x00FF) << (2 - 0));    // off8 
+            |((tinstr & 0x00FF) << (2 - 0));    // off8
         break;
 
     case 10:
diff --git a/src/core/arm/interpreter/armsupp.cpp b/src/core/arm/interpreter/armsupp.cpp
index 1b078dc71..83f7f3e2c 100644
--- a/src/core/arm/interpreter/armsupp.cpp
+++ b/src/core/arm/interpreter/armsupp.cpp
@@ -628,7 +628,7 @@ void WriteCP15Register(ARMul_State* cpu, u32 value, u32 crn, u32 opcode_1, u32 c
            cpu->CP15[CP15_DATA_SYNC_BARRIER] = value;
        else if (opcode_2 == 5)
            cpu->CP15[CP15_DATA_MEMORY_BARRIER] = value;
-           
+
     }
     else if (crn == 13 && opcode_1 == 0 && crm == 0 && opcode_2 == 2)
     {
diff --git a/src/core/arm/skyeye_common/armdefs.h b/src/core/arm/skyeye_common/armdefs.h
index 08ece69b6..d2c901100 100644
--- a/src/core/arm/skyeye_common/armdefs.h
+++ b/src/core/arm/skyeye_common/armdefs.h
@@ -1,16 +1,16 @@
 /*  armdefs.h -- ARMulator common definitions:  ARM6 Instruction Emulator.
     Copyright (C) 1994 Advanced RISC Machines Ltd.
- 
+
     This program is free software; you can redistribute it and/or modify
     it under the terms of the GNU General Public License as published by
     the Free Software Foundation; either version 2 of the License, or
     (at your option) any later version.
- 
+
     This program is distributed in the hope that it will be useful,
     but WITHOUT ANY WARRANTY; without even the implied warranty of
     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     GNU General Public License for more details.
- 
+
     You should have received a copy of the GNU General Public License
     along with this program; if not, write to the Free Software
     Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
diff --git a/src/core/arm/skyeye_common/vfp/vfp_helper.h b/src/core/arm/skyeye_common/vfp/vfp_helper.h
index ccc0212ab..2007d6dc4 100644
--- a/src/core/arm/skyeye_common/vfp/vfp_helper.h
+++ b/src/core/arm/skyeye_common/vfp/vfp_helper.h
@@ -18,10 +18,10 @@
     Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
 
-/* 
+/*
  *  The following code is derivative from Linux Android kernel vfp
  *  floating point support.
- * 
+ *
  *  Copyright (C) 2004 ARM Limited.
  *  Written by Deep Blue Solutions Limited.
  *