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authorGravatar bunnei2014-04-18 17:52:49 -0400
committerGravatar bunnei2014-04-18 17:52:49 -0400
commit958bca606e80110e05d7c142dda3097fddc96503 (patch)
tree576917751444b4dfdb476d040b4e075bde431b7b /src/core/arm
parentInit window size from VideoCore. Start changing the default window behavior... (diff)
parentrenamed hw_lcd module to just lcd (diff)
downloadyuzu-958bca606e80110e05d7c142dda3097fddc96503.tar.gz
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Merge branch 'hle-interface'
Diffstat (limited to 'src/core/arm')
-rw-r--r--src/core/arm/arm_interface.h11
-rw-r--r--src/core/arm/interpreter/arm_interpreter.cpp39
-rw-r--r--src/core/arm/interpreter/arm_interpreter.h37
-rw-r--r--src/core/arm/interpreter/armemu.cpp3
-rw-r--r--src/core/arm/interpreter/armemu.h11
-rw-r--r--src/core/arm/interpreter/arminit.cpp8
-rw-r--r--src/core/arm/interpreter/armsupp.cpp68
7 files changed, 135 insertions, 42 deletions
diff --git a/src/core/arm/arm_interface.h b/src/core/arm/arm_interface.h
index dafde8368..eee4726db 100644
--- a/src/core/arm/arm_interface.h
+++ b/src/core/arm/arm_interface.h
@@ -43,6 +43,13 @@ public:
43 virtual u32 GetReg(int index) const = 0; 43 virtual u32 GetReg(int index) const = 0;
44 44
45 /** 45 /**
46 * Set an ARM register
47 * @param index Register index (0-15)
48 * @param value Value to set register to
49 */
50 virtual void SetReg(int index, u32 value) = 0;
51
52 /**
46 * Get the current CPSR register 53 * Get the current CPSR register
47 * @return Returns the value of the CPSR register 54 * @return Returns the value of the CPSR register
48 */ 55 */
@@ -59,11 +66,13 @@ public:
59 return m_num_instructions; 66 return m_num_instructions;
60 } 67 }
61 68
62private: 69protected:
63 70
64 /// Execture next instruction 71 /// Execture next instruction
65 virtual void ExecuteInstruction() = 0; 72 virtual void ExecuteInstruction() = 0;
66 73
74private:
75
67 u64 m_num_instructions; ///< Number of instructions executed 76 u64 m_num_instructions; ///< Number of instructions executed
68 77
69 DISALLOW_COPY_AND_ASSIGN(ARM_Interface); 78 DISALLOW_COPY_AND_ASSIGN(ARM_Interface);
diff --git a/src/core/arm/interpreter/arm_interpreter.cpp b/src/core/arm/interpreter/arm_interpreter.cpp
index 81f38f016..4045779d7 100644
--- a/src/core/arm/interpreter/arm_interpreter.cpp
+++ b/src/core/arm/interpreter/arm_interpreter.cpp
@@ -31,30 +31,61 @@ ARM_Interpreter::ARM_Interpreter() {
31 m_state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack 31 m_state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack
32} 32}
33 33
34ARM_Interpreter::~ARM_Interpreter() {
35 delete m_state;
36}
37
38/**
39 * Set the Program Counter to an address
40 * @param addr Address to set PC to
41 */
34void ARM_Interpreter::SetPC(u32 pc) { 42void ARM_Interpreter::SetPC(u32 pc) {
35 m_state->pc = m_state->Reg[15] = pc; 43 m_state->pc = m_state->Reg[15] = pc;
36} 44}
37 45
46/*
47 * Get the current Program Counter
48 * @return Returns current PC
49 */
38u32 ARM_Interpreter::GetPC() const { 50u32 ARM_Interpreter::GetPC() const {
39 return m_state->pc; 51 return m_state->pc;
40} 52}
41 53
54/**
55 * Get an ARM register
56 * @param index Register index (0-15)
57 * @return Returns the value in the register
58 */
42u32 ARM_Interpreter::GetReg(int index) const { 59u32 ARM_Interpreter::GetReg(int index) const {
43 return m_state->Reg[index]; 60 return m_state->Reg[index];
44} 61}
45 62
63/**
64 * Set an ARM register
65 * @param index Register index (0-15)
66 * @param value Value to set register to
67 */
68void ARM_Interpreter::SetReg(int index, u32 value) {
69 m_state->Reg[index] = value;
70}
71
72/**
73 * Get the current CPSR register
74 * @return Returns the value of the CPSR register
75 */
46u32 ARM_Interpreter::GetCPSR() const { 76u32 ARM_Interpreter::GetCPSR() const {
47 return m_state->Cpsr; 77 return m_state->Cpsr;
48} 78}
49 79
80/**
81 * Returns the number of clock ticks since the last reset
82 * @return Returns number of clock ticks
83 */
50u64 ARM_Interpreter::GetTicks() const { 84u64 ARM_Interpreter::GetTicks() const {
51 return ARMul_Time(m_state); 85 return ARMul_Time(m_state);
52} 86}
53 87
54ARM_Interpreter::~ARM_Interpreter() { 88/// Execture next instruction
55 delete m_state;
56}
57
58void ARM_Interpreter::ExecuteInstruction() { 89void ARM_Interpreter::ExecuteInstruction() {
59 m_state->step++; 90 m_state->step++;
60 m_state->cycle++; 91 m_state->cycle++;
diff --git a/src/core/arm/interpreter/arm_interpreter.h b/src/core/arm/interpreter/arm_interpreter.h
index 932046d9a..f3c86f8dd 100644
--- a/src/core/arm/interpreter/arm_interpreter.h
+++ b/src/core/arm/interpreter/arm_interpreter.h
@@ -12,22 +12,55 @@
12 12
13class ARM_Interpreter : virtual public ARM_Interface { 13class ARM_Interpreter : virtual public ARM_Interface {
14public: 14public:
15
15 ARM_Interpreter(); 16 ARM_Interpreter();
16 ~ARM_Interpreter(); 17 ~ARM_Interpreter();
17 18
18 void ExecuteInstruction(); 19 /**
19 20 * Set the Program Counter to an address
21 * @param addr Address to set PC to
22 */
20 void SetPC(u32 pc); 23 void SetPC(u32 pc);
21 24
25 /*
26 * Get the current Program Counter
27 * @return Returns current PC
28 */
22 u32 GetPC() const; 29 u32 GetPC() const;
23 30
31 /**
32 * Get an ARM register
33 * @param index Register index (0-15)
34 * @return Returns the value in the register
35 */
24 u32 GetReg(int index) const; 36 u32 GetReg(int index) const;
25 37
38 /**
39 * Set an ARM register
40 * @param index Register index (0-15)
41 * @param value Value to set register to
42 */
43 void SetReg(int index, u32 value);
44
45 /**
46 * Get the current CPSR register
47 * @return Returns the value of the CPSR register
48 */
26 u32 GetCPSR() const; 49 u32 GetCPSR() const;
27 50
51 /**
52 * Returns the number of clock ticks since the last reset
53 * @return Returns number of clock ticks
54 */
28 u64 GetTicks() const; 55 u64 GetTicks() const;
29 56
57protected:
58
59 /// Execture next instruction
60 void ExecuteInstruction();
61
30private: 62private:
63
31 ARMul_State* m_state; 64 ARMul_State* m_state;
32 65
33 DISALLOW_COPY_AND_ASSIGN(ARM_Interpreter); 66 DISALLOW_COPY_AND_ASSIGN(ARM_Interpreter);
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp
index 46c51fbe8..6074ff480 100644
--- a/src/core/arm/interpreter/armemu.cpp
+++ b/src/core/arm/interpreter/armemu.cpp
@@ -16,6 +16,8 @@
16 along with this program; if not, write to the Free Software 16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
18 18
19#include "core/hle/hle.h"
20
19#include "arm_regformat.h" 21#include "arm_regformat.h"
20#include "armdefs.h" 22#include "armdefs.h"
21#include "armemu.h" 23#include "armemu.h"
@@ -4558,6 +4560,7 @@ ARMul_Emulate26 (ARMul_State * state)
4558 // ARMul_OSHandleSWI (state, BITS (0, 23)); 4560 // ARMul_OSHandleSWI (state, BITS (0, 23));
4559 // break; 4561 // break;
4560 //} 4562 //}
4563 HLE::CallSyscall(instr);
4561 ARMul_Abort (state, ARMul_SWIV); 4564 ARMul_Abort (state, ARMul_SWIV);
4562 break; 4565 break;
4563 } 4566 }
diff --git a/src/core/arm/interpreter/armemu.h b/src/core/arm/interpreter/armemu.h
index 7391dea7f..7c118948a 100644
--- a/src/core/arm/interpreter/armemu.h
+++ b/src/core/arm/interpreter/armemu.h
@@ -229,6 +229,17 @@ extern ARMword isize;
229 } \ 229 } \
230 while (0) 230 while (0)
231 231
232#define SETABORT_SKIPBRANCH(i, m, d) \
233 do \
234 { \
235 int SETABORT_mode = (m); \
236 \
237 ARMul_SetSPSR (state, SETABORT_mode, ARMul_GetCPSR (state)); \
238 ARMul_SetCPSR (state, ((ARMul_GetCPSR (state) & ~(EMODE | TBIT)) \
239 | (i) | SETABORT_mode)); \
240 } \
241 while (0)
242
232//#ifndef MODE32 243//#ifndef MODE32
233#define VECTORS 0x20 244#define VECTORS 0x20
234#define LEGALADDR 0x03ffffff 245#define LEGALADDR 0x03ffffff
diff --git a/src/core/arm/interpreter/arminit.cpp b/src/core/arm/interpreter/arminit.cpp
index cdbd02f3c..a8aeecdea 100644
--- a/src/core/arm/interpreter/arminit.cpp
+++ b/src/core/arm/interpreter/arminit.cpp
@@ -530,9 +530,13 @@ ARMul_Abort (ARMul_State * state, ARMword vector)
530 isize); 530 isize);
531 break; 531 break;
532 case ARMul_SWIV: /* Software Interrupt */ 532 case ARMul_SWIV: /* Software Interrupt */
533 SETABORT (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE, 533 // Modified SETABORT that doesn't branch to a SVC vector as we are implementing this in HLE
534 // Instead of doing normal routine, backup R15 by one instruction (this is what PC will get
535 // set to, making it the next instruction after the SVC call), and skip setting the LR.
536 SETABORT_SKIPBRANCH (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE,
534 isize); 537 isize);
535 break; 538 state->Reg[15] -= 4;
539 return;
536 case ARMul_PrefetchAbortV: /* Prefetch Abort */ 540 case ARMul_PrefetchAbortV: /* Prefetch Abort */
537 state->AbortAddr = 1; 541 state->AbortAddr = 1;
538 SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, 542 SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE,
diff --git a/src/core/arm/interpreter/armsupp.cpp b/src/core/arm/interpreter/armsupp.cpp
index a0c866c15..101b9807a 100644
--- a/src/core/arm/interpreter/armsupp.cpp
+++ b/src/core/arm/interpreter/armsupp.cpp
@@ -19,6 +19,8 @@
19#include "armemu.h" 19#include "armemu.h"
20//#include "ansidecl.h" 20//#include "ansidecl.h"
21#include "skyeye_defs.h" 21#include "skyeye_defs.h"
22#include "core/hle/hle.h"
23
22unsigned xscale_cp15_cp_access_allowed (ARMul_State * state, unsigned reg, 24unsigned xscale_cp15_cp_access_allowed (ARMul_State * state, unsigned reg,
23 unsigned cpnum); 25 unsigned cpnum);
24//extern int skyeye_instr_debug; 26//extern int skyeye_instr_debug;
@@ -734,39 +736,39 @@ ARMword
734ARMul_MRC (ARMul_State * state, ARMword instr) 736ARMul_MRC (ARMul_State * state, ARMword instr)
735{ 737{
736 unsigned cpab; 738 unsigned cpab;
737 ARMword result = 0; 739 ARMword result = HLE::CallGetThreadCommandBuffer();
738 740
739 //printf("SKYEYE ARMul_MRC, CPnum is %x, instr %x\n",CPNum, instr); 741 ////printf("SKYEYE ARMul_MRC, CPnum is %x, instr %x\n",CPNum, instr);
740 if (!CP_ACCESS_ALLOWED (state, CPNum)) { 742 //if (!CP_ACCESS_ALLOWED (state, CPNum)) {
741 //chy 2004-07-19 should fix in the future????!!!! 743 // //chy 2004-07-19 should fix in the future????!!!!
742 //printf("SKYEYE ARMul_MRC,NOT ALLOWed UndefInstr CPnum is %x, instr %x\n",CPNum, instr); 744 // //printf("SKYEYE ARMul_MRC,NOT ALLOWed UndefInstr CPnum is %x, instr %x\n",CPNum, instr);
743 ARMul_UndefInstr (state, instr); 745 // ARMul_UndefInstr (state, instr);
744 return -1; 746 // return -1;
745 } 747 //}
746 748
747 cpab = (state->MRC[CPNum]) (state, ARMul_FIRST, instr, &result); 749 //cpab = (state->MRC[CPNum]) (state, ARMul_FIRST, instr, &result);
748 while (cpab == ARMul_BUSY) { 750 //while (cpab == ARMul_BUSY) {
749 ARMul_Icycles (state, 1, 0); 751 // ARMul_Icycles (state, 1, 0);
750 if (IntPending (state)) { 752 // if (IntPending (state)) {
751 cpab = (state->MRC[CPNum]) (state, ARMul_INTERRUPT, 753 // cpab = (state->MRC[CPNum]) (state, ARMul_INTERRUPT,
752 instr, 0); 754 // instr, 0);
753 return (0); 755 // return (0);
754 } 756 // }
755 else 757 // else
756 cpab = (state->MRC[CPNum]) (state, ARMul_BUSY, instr, 758 // cpab = (state->MRC[CPNum]) (state, ARMul_BUSY, instr,
757 &result); 759 // &result);
758 } 760 //}
759 if (cpab == ARMul_CANT) { 761 //if (cpab == ARMul_CANT) {
760 printf ("SKYEYE ARMul_MRC,CANT UndefInstr CPnum is %x, instr %x\n", CPNum, instr); 762 // printf ("SKYEYE ARMul_MRC,CANT UndefInstr CPnum is %x, instr %x\n", CPNum, instr);
761 ARMul_Abort (state, ARMul_UndefinedInstrV); 763 // ARMul_Abort (state, ARMul_UndefinedInstrV);
762 /* Parent will destroy the flags otherwise. */ 764 // /* Parent will destroy the flags otherwise. */
763 result = ECC; 765 // result = ECC;
764 } 766 //}
765 else { 767 //else {
766 BUSUSEDINCPCN; 768 // BUSUSEDINCPCN;
767 ARMul_Ccycles (state, 1, 0); 769 // ARMul_Ccycles (state, 1, 0);
768 ARMul_Icycles (state, 1, 0); 770 // ARMul_Icycles (state, 1, 0);
769 } 771 //}
770 772
771 return result; 773 return result;
772} 774}